1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * I2C bus driver for the Cadence I2C controller. 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/pm_runtime.h> 17 18 /* Register offsets for the I2C device. */ 19 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ 20 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ 21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ 22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ 23 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ 24 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ 25 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ 26 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */ 27 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ 28 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ 29 30 /* Control Register Bit mask definitions */ 31 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ 32 #define CDNS_I2C_CR_ACK_EN BIT(3) 33 #define CDNS_I2C_CR_NEA BIT(2) 34 #define CDNS_I2C_CR_MS BIT(1) 35 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ 36 #define CDNS_I2C_CR_RW BIT(0) 37 /* 1 = Auto init FIFO to zeroes */ 38 #define CDNS_I2C_CR_CLR_FIFO BIT(6) 39 #define CDNS_I2C_CR_DIVA_SHIFT 14 40 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) 41 #define CDNS_I2C_CR_DIVB_SHIFT 8 42 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) 43 44 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \ 45 CDNS_I2C_CR_ACK_EN | \ 46 CDNS_I2C_CR_MS) 47 48 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK 49 50 /* Status Register Bit mask definitions */ 51 #define CDNS_I2C_SR_BA BIT(8) 52 #define CDNS_I2C_SR_TXDV BIT(6) 53 #define CDNS_I2C_SR_RXDV BIT(5) 54 #define CDNS_I2C_SR_RXRW BIT(3) 55 56 /* 57 * I2C Address Register Bit mask definitions 58 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] 59 * bits. A write access to this register always initiates a transfer if the I2C 60 * is in master mode. 61 */ 62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ 63 64 /* 65 * I2C Interrupt Registers Bit mask definitions 66 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 67 * bit definitions. 68 */ 69 #define CDNS_I2C_IXR_ARB_LOST BIT(9) 70 #define CDNS_I2C_IXR_RX_UNF BIT(7) 71 #define CDNS_I2C_IXR_TX_OVF BIT(6) 72 #define CDNS_I2C_IXR_RX_OVF BIT(5) 73 #define CDNS_I2C_IXR_SLV_RDY BIT(4) 74 #define CDNS_I2C_IXR_TO BIT(3) 75 #define CDNS_I2C_IXR_NACK BIT(2) 76 #define CDNS_I2C_IXR_DATA BIT(1) 77 #define CDNS_I2C_IXR_COMP BIT(0) 78 79 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 80 CDNS_I2C_IXR_RX_UNF | \ 81 CDNS_I2C_IXR_TX_OVF | \ 82 CDNS_I2C_IXR_RX_OVF | \ 83 CDNS_I2C_IXR_SLV_RDY | \ 84 CDNS_I2C_IXR_TO | \ 85 CDNS_I2C_IXR_NACK | \ 86 CDNS_I2C_IXR_DATA | \ 87 CDNS_I2C_IXR_COMP) 88 89 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 90 CDNS_I2C_IXR_RX_UNF | \ 91 CDNS_I2C_IXR_TX_OVF | \ 92 CDNS_I2C_IXR_RX_OVF | \ 93 CDNS_I2C_IXR_NACK) 94 95 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 96 CDNS_I2C_IXR_RX_UNF | \ 97 CDNS_I2C_IXR_TX_OVF | \ 98 CDNS_I2C_IXR_RX_OVF | \ 99 CDNS_I2C_IXR_NACK | \ 100 CDNS_I2C_IXR_DATA | \ 101 CDNS_I2C_IXR_COMP) 102 103 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \ 104 CDNS_I2C_IXR_TX_OVF | \ 105 CDNS_I2C_IXR_RX_OVF | \ 106 CDNS_I2C_IXR_TO | \ 107 CDNS_I2C_IXR_NACK | \ 108 CDNS_I2C_IXR_DATA | \ 109 CDNS_I2C_IXR_COMP) 110 111 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) 112 /* timeout for pm runtime autosuspend */ 113 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ 114 115 #define CDNS_I2C_FIFO_DEPTH 16 116 /* FIFO depth at which the DATA interrupt occurs */ 117 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2) 118 #define CDNS_I2C_MAX_TRANSFER_SIZE 255 119 /* Transfer size in multiples of data interrupt depth */ 120 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3) 121 122 #define DRIVER_NAME "cdns-i2c" 123 124 #define CDNS_I2C_DIVA_MAX 4 125 #define CDNS_I2C_DIVB_MAX 64 126 127 #define CDNS_I2C_TIMEOUT_MAX 0xFF 128 129 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 130 131 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) 132 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) 133 134 #if IS_ENABLED(CONFIG_I2C_SLAVE) 135 /** 136 * enum cdns_i2c_mode - I2C Controller current operating mode 137 * 138 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode 139 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode 140 */ 141 enum cdns_i2c_mode { 142 CDNS_I2C_MODE_SLAVE, 143 CDNS_I2C_MODE_MASTER, 144 }; 145 146 /** 147 * enum cdns_i2c_slave_mode - Slave state when I2C is operating in slave mode 148 * 149 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle 150 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master 151 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master 152 */ 153 enum cdns_i2c_slave_state { 154 CDNS_I2C_SLAVE_STATE_IDLE, 155 CDNS_I2C_SLAVE_STATE_SEND, 156 CDNS_I2C_SLAVE_STATE_RECV, 157 }; 158 #endif 159 160 /** 161 * struct cdns_i2c - I2C device private data structure 162 * 163 * @dev: Pointer to device structure 164 * @membase: Base address of the I2C device 165 * @adap: I2C adapter instance 166 * @p_msg: Message pointer 167 * @err_status: Error status in Interrupt Status Register 168 * @xfer_done: Transfer complete status 169 * @p_send_buf: Pointer to transmit buffer 170 * @p_recv_buf: Pointer to receive buffer 171 * @send_count: Number of bytes still expected to send 172 * @recv_count: Number of bytes still expected to receive 173 * @curr_recv_count: Number of bytes to be received in current transfer 174 * @irq: IRQ number 175 * @input_clk: Input clock to I2C controller 176 * @i2c_clk: Maximum I2C clock speed 177 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit 178 * @clk: Pointer to struct clk 179 * @clk_rate_change_nb: Notifier block for clock rate changes 180 * @quirks: flag for broken hold bit usage in r1p10 181 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register 182 * @slave: Registered slave instance. 183 * @dev_mode: I2C operating role(master/slave). 184 * @slave_state: I2C Slave state(idle/read/write). 185 */ 186 struct cdns_i2c { 187 struct device *dev; 188 void __iomem *membase; 189 struct i2c_adapter adap; 190 struct i2c_msg *p_msg; 191 int err_status; 192 struct completion xfer_done; 193 unsigned char *p_send_buf; 194 unsigned char *p_recv_buf; 195 unsigned int send_count; 196 unsigned int recv_count; 197 unsigned int curr_recv_count; 198 int irq; 199 unsigned long input_clk; 200 unsigned int i2c_clk; 201 unsigned int bus_hold_flag; 202 struct clk *clk; 203 struct notifier_block clk_rate_change_nb; 204 u32 quirks; 205 #if IS_ENABLED(CONFIG_I2C_SLAVE) 206 u16 ctrl_reg_diva_divb; 207 struct i2c_client *slave; 208 enum cdns_i2c_mode dev_mode; 209 enum cdns_i2c_slave_state slave_state; 210 #endif 211 }; 212 213 struct cdns_platform_data { 214 u32 quirks; 215 }; 216 217 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ 218 clk_rate_change_nb) 219 220 /** 221 * cdns_i2c_clear_bus_hold - Clear bus hold bit 222 * @id: Pointer to driver data struct 223 * 224 * Helper to clear the controller's bus hold bit. 225 */ 226 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) 227 { 228 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 229 if (reg & CDNS_I2C_CR_HOLD) 230 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); 231 } 232 233 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) 234 { 235 return (hold_wrkaround && 236 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); 237 } 238 239 #if IS_ENABLED(CONFIG_I2C_SLAVE) 240 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) 241 { 242 /* Disable all interrupts */ 243 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 244 245 /* Clear FIFO and transfer size */ 246 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 247 248 /* Update device mode and state */ 249 id->dev_mode = mode; 250 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 251 252 switch (mode) { 253 case CDNS_I2C_MODE_MASTER: 254 /* Enable i2c master */ 255 cdns_i2c_writereg(id->ctrl_reg_diva_divb | 256 CDNS_I2C_CR_MASTER_EN_MASK, 257 CDNS_I2C_CR_OFFSET); 258 /* 259 * This delay is needed to give the IP some time to switch to 260 * the master mode. With lower values(like 110 us) i2cdetect 261 * will not detect any slave and without this delay, the IP will 262 * trigger a timeout interrupt. 263 */ 264 usleep_range(115, 125); 265 break; 266 case CDNS_I2C_MODE_SLAVE: 267 /* Enable i2c slave */ 268 cdns_i2c_writereg(id->ctrl_reg_diva_divb & 269 CDNS_I2C_CR_SLAVE_EN_MASK, 270 CDNS_I2C_CR_OFFSET); 271 272 /* Setting slave address */ 273 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK, 274 CDNS_I2C_ADDR_OFFSET); 275 276 /* Enable slave send/receive interrupts */ 277 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK, 278 CDNS_I2C_IER_OFFSET); 279 break; 280 } 281 } 282 283 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) 284 { 285 u8 bytes; 286 unsigned char data; 287 288 /* Prepare backend for data reception */ 289 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 290 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV; 291 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL); 292 } 293 294 /* Fetch number of bytes to receive */ 295 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 296 297 /* Read data and send to backend */ 298 while (bytes--) { 299 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 300 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data); 301 } 302 } 303 304 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) 305 { 306 u8 data; 307 308 /* Prepare backend for data transmission */ 309 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 310 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND; 311 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data); 312 } else { 313 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data); 314 } 315 316 /* Send data over bus */ 317 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET); 318 } 319 320 /** 321 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role 322 * @ptr: Pointer to I2C device private data 323 * 324 * This function handles the data interrupt and transfer complete interrupt of 325 * the I2C device in slave role. 326 * 327 * Return: IRQ_HANDLED always 328 */ 329 static irqreturn_t cdns_i2c_slave_isr(void *ptr) 330 { 331 struct cdns_i2c *id = ptr; 332 unsigned int isr_status, i2c_status; 333 334 /* Fetch the interrupt status */ 335 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 336 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 337 338 /* Ignore masked interrupts */ 339 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET); 340 341 /* Fetch transfer mode (send/receive) */ 342 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 343 344 /* Handle data send/receive */ 345 if (i2c_status & CDNS_I2C_SR_RXRW) { 346 /* Send data to master */ 347 if (isr_status & CDNS_I2C_IXR_DATA) 348 cdns_i2c_slave_send_data(id); 349 350 if (isr_status & CDNS_I2C_IXR_COMP) { 351 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 352 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 353 } 354 } else { 355 /* Receive data from master */ 356 if (isr_status & CDNS_I2C_IXR_DATA) 357 cdns_i2c_slave_rcv_data(id); 358 359 if (isr_status & CDNS_I2C_IXR_COMP) { 360 cdns_i2c_slave_rcv_data(id); 361 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 362 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 363 } 364 } 365 366 /* Master indicated xfer stop or fifo underflow/overflow */ 367 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF | 368 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) { 369 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 370 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 371 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 372 } 373 374 return IRQ_HANDLED; 375 } 376 #endif 377 378 /** 379 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role 380 * @ptr: Pointer to I2C device private data 381 * 382 * This function handles the data interrupt, transfer complete interrupt and 383 * the error interrupts of the I2C device in master role. 384 * 385 * Return: IRQ_HANDLED always 386 */ 387 static irqreturn_t cdns_i2c_master_isr(void *ptr) 388 { 389 unsigned int isr_status, avail_bytes, updatetx; 390 unsigned int bytes_to_send; 391 bool hold_quirk; 392 struct cdns_i2c *id = ptr; 393 /* Signal completion only after everything is updated */ 394 int done_flag = 0; 395 irqreturn_t status = IRQ_NONE; 396 397 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 398 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 399 id->err_status = 0; 400 401 /* Handling nack and arbitration lost interrupt */ 402 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { 403 done_flag = 1; 404 status = IRQ_HANDLED; 405 } 406 407 /* 408 * Check if transfer size register needs to be updated again for a 409 * large data receive operation. 410 */ 411 updatetx = 0; 412 if (id->recv_count > id->curr_recv_count) 413 updatetx = 1; 414 415 hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx; 416 417 /* When receiving, handle data interrupt and completion interrupt */ 418 if (id->p_recv_buf && 419 ((isr_status & CDNS_I2C_IXR_COMP) || 420 (isr_status & CDNS_I2C_IXR_DATA))) { 421 /* Read data if receive data valid is set */ 422 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 423 CDNS_I2C_SR_RXDV) { 424 /* 425 * Clear hold bit that was set for FIFO control if 426 * RX data left is less than FIFO depth, unless 427 * repeated start is selected. 428 */ 429 if ((id->recv_count < CDNS_I2C_FIFO_DEPTH) && 430 !id->bus_hold_flag) 431 cdns_i2c_clear_bus_hold(id); 432 433 if (id->recv_count > 0) { 434 *(id->p_recv_buf)++ = 435 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 436 id->recv_count--; 437 id->curr_recv_count--; 438 } else { 439 dev_err(id->adap.dev.parent, 440 "xfer_size reg rollover. xfer aborted!\n"); 441 id->err_status |= CDNS_I2C_IXR_TO; 442 break; 443 } 444 445 if (cdns_is_holdquirk(id, hold_quirk)) 446 break; 447 } 448 449 /* 450 * The controller sends NACK to the slave when transfer size 451 * register reaches zero without considering the HOLD bit. 452 * This workaround is implemented for large data transfers to 453 * maintain transfer size non-zero while performing a large 454 * receive operation. 455 */ 456 if (cdns_is_holdquirk(id, hold_quirk)) { 457 /* wait while fifo is full */ 458 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 459 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) 460 ; 461 462 /* 463 * Check number of bytes to be received against maximum 464 * transfer size and update register accordingly. 465 */ 466 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > 467 CDNS_I2C_TRANSFER_SIZE) { 468 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 469 CDNS_I2C_XFER_SIZE_OFFSET); 470 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + 471 CDNS_I2C_FIFO_DEPTH; 472 } else { 473 cdns_i2c_writereg(id->recv_count - 474 CDNS_I2C_FIFO_DEPTH, 475 CDNS_I2C_XFER_SIZE_OFFSET); 476 id->curr_recv_count = id->recv_count; 477 } 478 } else if (id->recv_count && !hold_quirk && 479 !id->curr_recv_count) { 480 481 /* Set the slave address in address register*/ 482 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 483 CDNS_I2C_ADDR_OFFSET); 484 485 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 486 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 487 CDNS_I2C_XFER_SIZE_OFFSET); 488 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 489 } else { 490 cdns_i2c_writereg(id->recv_count, 491 CDNS_I2C_XFER_SIZE_OFFSET); 492 id->curr_recv_count = id->recv_count; 493 } 494 } 495 496 /* Clear hold (if not repeated start) and signal completion */ 497 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { 498 if (!id->bus_hold_flag) 499 cdns_i2c_clear_bus_hold(id); 500 done_flag = 1; 501 } 502 503 status = IRQ_HANDLED; 504 } 505 506 /* When sending, handle transfer complete interrupt */ 507 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { 508 /* 509 * If there is more data to be sent, calculate the 510 * space available in FIFO and fill with that many bytes. 511 */ 512 if (id->send_count) { 513 avail_bytes = CDNS_I2C_FIFO_DEPTH - 514 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 515 if (id->send_count > avail_bytes) 516 bytes_to_send = avail_bytes; 517 else 518 bytes_to_send = id->send_count; 519 520 while (bytes_to_send--) { 521 cdns_i2c_writereg( 522 (*(id->p_send_buf)++), 523 CDNS_I2C_DATA_OFFSET); 524 id->send_count--; 525 } 526 } else { 527 /* 528 * Signal the completion of transaction and 529 * clear the hold bus bit if there are no 530 * further messages to be processed. 531 */ 532 done_flag = 1; 533 } 534 if (!id->send_count && !id->bus_hold_flag) 535 cdns_i2c_clear_bus_hold(id); 536 537 status = IRQ_HANDLED; 538 } 539 540 /* Update the status for errors */ 541 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 542 if (id->err_status) 543 status = IRQ_HANDLED; 544 545 if (done_flag) 546 complete(&id->xfer_done); 547 548 return status; 549 } 550 551 /** 552 * cdns_i2c_isr - Interrupt handler for the I2C device 553 * @irq: irq number for the I2C device 554 * @ptr: void pointer to cdns_i2c structure 555 * 556 * This function passes the control to slave/master based on current role of 557 * i2c controller. 558 * 559 * Return: IRQ_HANDLED always 560 */ 561 static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 562 { 563 #if IS_ENABLED(CONFIG_I2C_SLAVE) 564 struct cdns_i2c *id = ptr; 565 566 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) 567 return cdns_i2c_slave_isr(ptr); 568 #endif 569 return cdns_i2c_master_isr(ptr); 570 } 571 572 /** 573 * cdns_i2c_mrecv - Prepare and start a master receive operation 574 * @id: pointer to the i2c device structure 575 */ 576 static void cdns_i2c_mrecv(struct cdns_i2c *id) 577 { 578 unsigned int ctrl_reg; 579 unsigned int isr_status; 580 581 id->p_recv_buf = id->p_msg->buf; 582 id->recv_count = id->p_msg->len; 583 584 /* Put the controller in master receive mode and clear the FIFO */ 585 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 586 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; 587 588 if (id->p_msg->flags & I2C_M_RECV_LEN) 589 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; 590 591 id->curr_recv_count = id->recv_count; 592 593 /* 594 * Check for the message size against FIFO depth and set the 595 * 'hold bus' bit if it is greater than FIFO depth. 596 */ 597 if ((id->recv_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) 598 ctrl_reg |= CDNS_I2C_CR_HOLD; 599 else 600 ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; 601 602 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 603 604 /* Clear the interrupts in interrupt status register */ 605 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 606 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 607 608 /* 609 * The no. of bytes to receive is checked against the limit of 610 * max transfer size. Set transfer size register with no of bytes 611 * receive if it is less than transfer size and transfer size if 612 * it is more. Enable the interrupts. 613 */ 614 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 615 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 616 CDNS_I2C_XFER_SIZE_OFFSET); 617 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 618 } else { 619 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 620 } 621 622 /* Set the slave address in address register - triggers operation */ 623 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 624 CDNS_I2C_ADDR_OFFSET); 625 /* Clear the bus hold flag if bytes to receive is less than FIFO size */ 626 if (!id->bus_hold_flag && 627 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && 628 (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) 629 cdns_i2c_clear_bus_hold(id); 630 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 631 } 632 633 /** 634 * cdns_i2c_msend - Prepare and start a master send operation 635 * @id: pointer to the i2c device 636 */ 637 static void cdns_i2c_msend(struct cdns_i2c *id) 638 { 639 unsigned int avail_bytes; 640 unsigned int bytes_to_send; 641 unsigned int ctrl_reg; 642 unsigned int isr_status; 643 644 id->p_recv_buf = NULL; 645 id->p_send_buf = id->p_msg->buf; 646 id->send_count = id->p_msg->len; 647 648 /* Set the controller in Master transmit mode and clear the FIFO. */ 649 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 650 ctrl_reg &= ~CDNS_I2C_CR_RW; 651 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; 652 653 /* 654 * Check for the message size against FIFO depth and set the 655 * 'hold bus' bit if it is greater than FIFO depth. 656 */ 657 if ((id->send_count > CDNS_I2C_FIFO_DEPTH) || id->bus_hold_flag) 658 ctrl_reg |= CDNS_I2C_CR_HOLD; 659 else 660 ctrl_reg = ctrl_reg & ~CDNS_I2C_CR_HOLD; 661 662 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 663 664 /* Clear the interrupts in interrupt status register. */ 665 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 666 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 667 668 /* 669 * Calculate the space available in FIFO. Check the message length 670 * against the space available, and fill the FIFO accordingly. 671 * Enable the interrupts. 672 */ 673 avail_bytes = CDNS_I2C_FIFO_DEPTH - 674 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 675 676 if (id->send_count > avail_bytes) 677 bytes_to_send = avail_bytes; 678 else 679 bytes_to_send = id->send_count; 680 681 while (bytes_to_send--) { 682 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); 683 id->send_count--; 684 } 685 686 /* 687 * Clear the bus hold flag if there is no more data 688 * and if it is the last message. 689 */ 690 if (!id->bus_hold_flag && !id->send_count) 691 cdns_i2c_clear_bus_hold(id); 692 /* Set the slave address in address register - triggers operation. */ 693 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 694 CDNS_I2C_ADDR_OFFSET); 695 696 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 697 } 698 699 /** 700 * cdns_i2c_master_reset - Reset the interface 701 * @adap: pointer to the i2c adapter driver instance 702 * 703 * This function cleanup the fifos, clear the hold bit and status 704 * and disable the interrupts. 705 */ 706 static void cdns_i2c_master_reset(struct i2c_adapter *adap) 707 { 708 struct cdns_i2c *id = adap->algo_data; 709 u32 regval; 710 711 /* Disable the interrupts */ 712 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 713 /* Clear the hold bit and fifos */ 714 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 715 regval &= ~CDNS_I2C_CR_HOLD; 716 regval |= CDNS_I2C_CR_CLR_FIFO; 717 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); 718 /* Update the transfercount register to zero */ 719 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); 720 /* Clear the interrupt status register */ 721 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 722 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); 723 /* Clear the status register */ 724 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 725 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); 726 } 727 728 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, 729 struct i2c_adapter *adap) 730 { 731 unsigned long time_left; 732 u32 reg; 733 734 id->p_msg = msg; 735 id->err_status = 0; 736 reinit_completion(&id->xfer_done); 737 738 /* Check for the TEN Bit mode on each msg */ 739 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 740 if (msg->flags & I2C_M_TEN) { 741 if (reg & CDNS_I2C_CR_NEA) 742 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, 743 CDNS_I2C_CR_OFFSET); 744 } else { 745 if (!(reg & CDNS_I2C_CR_NEA)) 746 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, 747 CDNS_I2C_CR_OFFSET); 748 } 749 750 /* Check for the R/W flag on each msg */ 751 if (msg->flags & I2C_M_RD) 752 cdns_i2c_mrecv(id); 753 else 754 cdns_i2c_msend(id); 755 756 /* Wait for the signal of completion */ 757 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout); 758 if (time_left == 0) { 759 cdns_i2c_master_reset(adap); 760 dev_err(id->adap.dev.parent, 761 "timeout waiting on completion\n"); 762 return -ETIMEDOUT; 763 } 764 765 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, 766 CDNS_I2C_IDR_OFFSET); 767 768 /* If it is bus arbitration error, try again */ 769 if (id->err_status & CDNS_I2C_IXR_ARB_LOST) 770 return -EAGAIN; 771 772 return 0; 773 } 774 775 /** 776 * cdns_i2c_master_xfer - The main i2c transfer function 777 * @adap: pointer to the i2c adapter driver instance 778 * @msgs: pointer to the i2c message structure 779 * @num: the number of messages to transfer 780 * 781 * Initiates the send/recv activity based on the transfer message received. 782 * 783 * Return: number of msgs processed on success, negative error otherwise 784 */ 785 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 786 int num) 787 { 788 int ret, count; 789 u32 reg; 790 struct cdns_i2c *id = adap->algo_data; 791 bool hold_quirk; 792 #if IS_ENABLED(CONFIG_I2C_SLAVE) 793 bool change_role = false; 794 #endif 795 796 ret = pm_runtime_get_sync(id->dev); 797 if (ret < 0) 798 return ret; 799 800 #if IS_ENABLED(CONFIG_I2C_SLAVE) 801 /* Check i2c operating mode and switch if possible */ 802 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) { 803 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) 804 return -EAGAIN; 805 806 /* Set mode to master */ 807 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 808 809 /* Mark flag to change role once xfer is completed */ 810 change_role = true; 811 } 812 #endif 813 814 /* Check if the bus is free */ 815 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) { 816 ret = -EAGAIN; 817 goto out; 818 } 819 820 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 821 /* 822 * Set the flag to one when multiple messages are to be 823 * processed with a repeated start. 824 */ 825 if (num > 1) { 826 /* 827 * This controller does not give completion interrupt after a 828 * master receive message if HOLD bit is set (repeated start), 829 * resulting in SW timeout. Hence, if a receive message is 830 * followed by any other message, an error is returned 831 * indicating that this sequence is not supported. 832 */ 833 for (count = 0; (count < num - 1 && hold_quirk); count++) { 834 if (msgs[count].flags & I2C_M_RD) { 835 dev_warn(adap->dev.parent, 836 "Can't do repeated start after a receive message\n"); 837 ret = -EOPNOTSUPP; 838 goto out; 839 } 840 } 841 id->bus_hold_flag = 1; 842 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 843 reg |= CDNS_I2C_CR_HOLD; 844 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); 845 } else { 846 id->bus_hold_flag = 0; 847 } 848 849 /* Process the msg one by one */ 850 for (count = 0; count < num; count++, msgs++) { 851 if (count == (num - 1)) 852 id->bus_hold_flag = 0; 853 854 ret = cdns_i2c_process_msg(id, msgs, adap); 855 if (ret) 856 goto out; 857 858 /* Report the other error interrupts to application */ 859 if (id->err_status) { 860 cdns_i2c_master_reset(adap); 861 862 if (id->err_status & CDNS_I2C_IXR_NACK) { 863 ret = -ENXIO; 864 goto out; 865 } 866 ret = -EIO; 867 goto out; 868 } 869 } 870 871 ret = num; 872 873 out: 874 875 #if IS_ENABLED(CONFIG_I2C_SLAVE) 876 /* Switch i2c mode to slave */ 877 if (change_role) 878 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 879 #endif 880 881 pm_runtime_mark_last_busy(id->dev); 882 pm_runtime_put_autosuspend(id->dev); 883 return ret; 884 } 885 886 /** 887 * cdns_i2c_func - Returns the supported features of the I2C driver 888 * @adap: pointer to the i2c adapter structure 889 * 890 * Return: 32 bit value, each bit corresponding to a feature 891 */ 892 static u32 cdns_i2c_func(struct i2c_adapter *adap) 893 { 894 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 895 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 896 I2C_FUNC_SMBUS_BLOCK_DATA; 897 898 #if IS_ENABLED(CONFIG_I2C_SLAVE) 899 func |= I2C_FUNC_SLAVE; 900 #endif 901 902 return func; 903 } 904 905 #if IS_ENABLED(CONFIG_I2C_SLAVE) 906 static int cdns_reg_slave(struct i2c_client *slave) 907 { 908 int ret; 909 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 910 adap); 911 912 if (id->slave) 913 return -EBUSY; 914 915 if (slave->flags & I2C_CLIENT_TEN) 916 return -EAFNOSUPPORT; 917 918 ret = pm_runtime_get_sync(id->dev); 919 if (ret < 0) 920 return ret; 921 922 /* Store slave information */ 923 id->slave = slave; 924 925 /* Enable I2C slave */ 926 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 927 928 return 0; 929 } 930 931 static int cdns_unreg_slave(struct i2c_client *slave) 932 { 933 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 934 adap); 935 936 pm_runtime_put(id->dev); 937 938 /* Remove slave information */ 939 id->slave = NULL; 940 941 /* Enable I2C master */ 942 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 943 944 return 0; 945 } 946 #endif 947 948 static const struct i2c_algorithm cdns_i2c_algo = { 949 .master_xfer = cdns_i2c_master_xfer, 950 .functionality = cdns_i2c_func, 951 #if IS_ENABLED(CONFIG_I2C_SLAVE) 952 .reg_slave = cdns_reg_slave, 953 .unreg_slave = cdns_unreg_slave, 954 #endif 955 }; 956 957 /** 958 * cdns_i2c_calc_divs - Calculate clock dividers 959 * @f: I2C clock frequency 960 * @input_clk: Input clock frequency 961 * @a: First divider (return value) 962 * @b: Second divider (return value) 963 * 964 * f is used as input and output variable. As input it is used as target I2C 965 * frequency. On function exit f holds the actually resulting I2C frequency. 966 * 967 * Return: 0 on success, negative errno otherwise. 968 */ 969 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 970 unsigned int *a, unsigned int *b) 971 { 972 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 973 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 974 unsigned int last_error, current_error; 975 976 /* calculate (divisor_a+1) x (divisor_b+1) */ 977 temp = input_clk / (22 * fscl); 978 979 /* 980 * If the calculated value is negative or 0, the fscl input is out of 981 * range. Return error. 982 */ 983 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 984 return -EINVAL; 985 986 last_error = -1; 987 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 988 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 989 990 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 991 continue; 992 div_b--; 993 994 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 995 996 if (actual_fscl > fscl) 997 continue; 998 999 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 1000 (fscl - actual_fscl)); 1001 1002 if (last_error > current_error) { 1003 calc_div_a = div_a; 1004 calc_div_b = div_b; 1005 best_fscl = actual_fscl; 1006 last_error = current_error; 1007 } 1008 } 1009 1010 *a = calc_div_a; 1011 *b = calc_div_b; 1012 *f = best_fscl; 1013 1014 return 0; 1015 } 1016 1017 /** 1018 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device 1019 * @clk_in: I2C clock input frequency in Hz 1020 * @id: Pointer to the I2C device structure 1021 * 1022 * The device must be idle rather than busy transferring data before setting 1023 * these device options. 1024 * The data rate is set by values in the control register. 1025 * The formula for determining the correct register values is 1026 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) 1027 * See the hardware data sheet for a full explanation of setting the serial 1028 * clock rate. The clock can not be faster than the input clock divide by 22. 1029 * The two most common clock rates are 100KHz and 400KHz. 1030 * 1031 * Return: 0 on success, negative error otherwise 1032 */ 1033 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) 1034 { 1035 unsigned int div_a, div_b; 1036 unsigned int ctrl_reg; 1037 int ret = 0; 1038 unsigned long fscl = id->i2c_clk; 1039 1040 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); 1041 if (ret) 1042 return ret; 1043 1044 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 1045 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); 1046 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | 1047 (div_b << CDNS_I2C_CR_DIVB_SHIFT)); 1048 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 1049 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1050 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK | 1051 CDNS_I2C_CR_DIVB_MASK); 1052 #endif 1053 return 0; 1054 } 1055 1056 /** 1057 * cdns_i2c_clk_notifier_cb - Clock rate change callback 1058 * @nb: Pointer to notifier block 1059 * @event: Notification reason 1060 * @data: Pointer to notification data object 1061 * 1062 * This function is called when the cdns_i2c input clock frequency changes. 1063 * The callback checks whether a valid bus frequency can be generated after the 1064 * change. If so, the change is acknowledged, otherwise the change is aborted. 1065 * New dividers are written to the HW in the pre- or post change notification 1066 * depending on the scaling direction. 1067 * 1068 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 1069 * to acknowledge the change, NOTIFY_DONE if the notification is 1070 * considered irrelevant. 1071 */ 1072 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 1073 event, void *data) 1074 { 1075 struct clk_notifier_data *ndata = data; 1076 struct cdns_i2c *id = to_cdns_i2c(nb); 1077 1078 if (pm_runtime_suspended(id->dev)) 1079 return NOTIFY_OK; 1080 1081 switch (event) { 1082 case PRE_RATE_CHANGE: 1083 { 1084 unsigned long input_clk = ndata->new_rate; 1085 unsigned long fscl = id->i2c_clk; 1086 unsigned int div_a, div_b; 1087 int ret; 1088 1089 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); 1090 if (ret) { 1091 dev_warn(id->adap.dev.parent, 1092 "clock rate change rejected\n"); 1093 return NOTIFY_STOP; 1094 } 1095 1096 /* scale up */ 1097 if (ndata->new_rate > ndata->old_rate) 1098 cdns_i2c_setclk(ndata->new_rate, id); 1099 1100 return NOTIFY_OK; 1101 } 1102 case POST_RATE_CHANGE: 1103 id->input_clk = ndata->new_rate; 1104 /* scale down */ 1105 if (ndata->new_rate < ndata->old_rate) 1106 cdns_i2c_setclk(ndata->new_rate, id); 1107 return NOTIFY_OK; 1108 case ABORT_RATE_CHANGE: 1109 /* scale up */ 1110 if (ndata->new_rate > ndata->old_rate) 1111 cdns_i2c_setclk(ndata->old_rate, id); 1112 return NOTIFY_OK; 1113 default: 1114 return NOTIFY_DONE; 1115 } 1116 } 1117 1118 /** 1119 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver 1120 * @dev: Address of the platform_device structure 1121 * 1122 * Put the driver into low power mode. 1123 * 1124 * Return: 0 always 1125 */ 1126 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 1127 { 1128 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1129 1130 clk_disable(xi2c->clk); 1131 1132 return 0; 1133 } 1134 1135 /** 1136 * cdns_i2c_runtime_resume - Runtime resume 1137 * @dev: Address of the platform_device structure 1138 * 1139 * Runtime resume callback. 1140 * 1141 * Return: 0 on success and error value on error 1142 */ 1143 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 1144 { 1145 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1146 int ret; 1147 1148 ret = clk_enable(xi2c->clk); 1149 if (ret) { 1150 dev_err(dev, "Cannot enable clock.\n"); 1151 return ret; 1152 } 1153 1154 return 0; 1155 } 1156 1157 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { 1158 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, 1159 cdns_i2c_runtime_resume, NULL) 1160 }; 1161 1162 static const struct cdns_platform_data r1p10_i2c_def = { 1163 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 1164 }; 1165 1166 static const struct of_device_id cdns_i2c_of_match[] = { 1167 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, 1168 { .compatible = "cdns,i2c-r1p14",}, 1169 { /* end of table */ } 1170 }; 1171 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); 1172 1173 /** 1174 * cdns_i2c_probe - Platform registration call 1175 * @pdev: Handle to the platform device structure 1176 * 1177 * This function does all the memory allocation and registration for the i2c 1178 * device. User can modify the address mode to 10 bit address mode using the 1179 * ioctl call with option I2C_TENBIT. 1180 * 1181 * Return: 0 on success, negative error otherwise 1182 */ 1183 static int cdns_i2c_probe(struct platform_device *pdev) 1184 { 1185 struct resource *r_mem; 1186 struct cdns_i2c *id; 1187 int ret; 1188 const struct of_device_id *match; 1189 1190 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); 1191 if (!id) 1192 return -ENOMEM; 1193 1194 id->dev = &pdev->dev; 1195 platform_set_drvdata(pdev, id); 1196 1197 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); 1198 if (match && match->data) { 1199 const struct cdns_platform_data *data = match->data; 1200 id->quirks = data->quirks; 1201 } 1202 1203 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem); 1204 if (IS_ERR(id->membase)) 1205 return PTR_ERR(id->membase); 1206 1207 id->irq = platform_get_irq(pdev, 0); 1208 1209 id->adap.owner = THIS_MODULE; 1210 id->adap.dev.of_node = pdev->dev.of_node; 1211 id->adap.algo = &cdns_i2c_algo; 1212 id->adap.timeout = CDNS_I2C_TIMEOUT; 1213 id->adap.retries = 3; /* Default retry value. */ 1214 id->adap.algo_data = id; 1215 id->adap.dev.parent = &pdev->dev; 1216 init_completion(&id->xfer_done); 1217 snprintf(id->adap.name, sizeof(id->adap.name), 1218 "Cadence I2C at %08lx", (unsigned long)r_mem->start); 1219 1220 id->clk = devm_clk_get(&pdev->dev, NULL); 1221 if (IS_ERR(id->clk)) { 1222 if (PTR_ERR(id->clk) != -EPROBE_DEFER) 1223 dev_err(&pdev->dev, "input clock not found.\n"); 1224 return PTR_ERR(id->clk); 1225 } 1226 ret = clk_prepare_enable(id->clk); 1227 if (ret) 1228 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1229 1230 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); 1231 pm_runtime_use_autosuspend(id->dev); 1232 pm_runtime_set_active(id->dev); 1233 pm_runtime_enable(id->dev); 1234 1235 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; 1236 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) 1237 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1238 id->input_clk = clk_get_rate(id->clk); 1239 1240 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1241 &id->i2c_clk); 1242 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ)) 1243 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ; 1244 1245 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1246 /* Set initial mode to master */ 1247 id->dev_mode = CDNS_I2C_MODE_MASTER; 1248 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 1249 #endif 1250 cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET); 1251 1252 ret = cdns_i2c_setclk(id->input_clk, id); 1253 if (ret) { 1254 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); 1255 ret = -EINVAL; 1256 goto err_clk_dis; 1257 } 1258 1259 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0, 1260 DRIVER_NAME, id); 1261 if (ret) { 1262 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq); 1263 goto err_clk_dis; 1264 } 1265 1266 /* 1267 * Cadence I2C controller has a bug wherein it generates 1268 * invalid read transaction after HW timeout in master receiver mode. 1269 * HW timeout is not used by this driver and the interrupt is disabled. 1270 * But the feature itself cannot be disabled. Hence maximum value 1271 * is written to this register to reduce the chances of error. 1272 */ 1273 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); 1274 1275 ret = i2c_add_adapter(&id->adap); 1276 if (ret < 0) 1277 goto err_clk_dis; 1278 1279 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", 1280 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq); 1281 1282 return 0; 1283 1284 err_clk_dis: 1285 clk_disable_unprepare(id->clk); 1286 pm_runtime_disable(&pdev->dev); 1287 pm_runtime_set_suspended(&pdev->dev); 1288 return ret; 1289 } 1290 1291 /** 1292 * cdns_i2c_remove - Unregister the device after releasing the resources 1293 * @pdev: Handle to the platform device structure 1294 * 1295 * This function frees all the resources allocated to the device. 1296 * 1297 * Return: 0 always 1298 */ 1299 static int cdns_i2c_remove(struct platform_device *pdev) 1300 { 1301 struct cdns_i2c *id = platform_get_drvdata(pdev); 1302 1303 pm_runtime_disable(&pdev->dev); 1304 pm_runtime_set_suspended(&pdev->dev); 1305 pm_runtime_dont_use_autosuspend(&pdev->dev); 1306 1307 i2c_del_adapter(&id->adap); 1308 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1309 clk_disable_unprepare(id->clk); 1310 1311 return 0; 1312 } 1313 1314 static struct platform_driver cdns_i2c_drv = { 1315 .driver = { 1316 .name = DRIVER_NAME, 1317 .of_match_table = cdns_i2c_of_match, 1318 .pm = &cdns_i2c_dev_pm_ops, 1319 }, 1320 .probe = cdns_i2c_probe, 1321 .remove = cdns_i2c_remove, 1322 }; 1323 1324 module_platform_driver(cdns_i2c_drv); 1325 1326 MODULE_AUTHOR("Xilinx Inc."); 1327 MODULE_DESCRIPTION("Cadence I2C bus driver"); 1328 MODULE_LICENSE("GPL"); 1329