1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * I2C bus driver for the Cadence I2C controller. 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pinctrl/consumer.h> 19 20 /* Register offsets for the I2C device. */ 21 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ 22 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ 23 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ 24 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ 25 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ 26 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ 27 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ 28 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */ 29 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ 30 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ 31 32 /* Control Register Bit mask definitions */ 33 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ 34 #define CDNS_I2C_CR_ACK_EN BIT(3) 35 #define CDNS_I2C_CR_NEA BIT(2) 36 #define CDNS_I2C_CR_MS BIT(1) 37 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ 38 #define CDNS_I2C_CR_RW BIT(0) 39 /* 1 = Auto init FIFO to zeroes */ 40 #define CDNS_I2C_CR_CLR_FIFO BIT(6) 41 #define CDNS_I2C_CR_DIVA_SHIFT 14 42 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) 43 #define CDNS_I2C_CR_DIVB_SHIFT 8 44 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) 45 46 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \ 47 CDNS_I2C_CR_ACK_EN | \ 48 CDNS_I2C_CR_MS) 49 50 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK 51 52 /* Status Register Bit mask definitions */ 53 #define CDNS_I2C_SR_BA BIT(8) 54 #define CDNS_I2C_SR_TXDV BIT(6) 55 #define CDNS_I2C_SR_RXDV BIT(5) 56 #define CDNS_I2C_SR_RXRW BIT(3) 57 58 /* 59 * I2C Address Register Bit mask definitions 60 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] 61 * bits. A write access to this register always initiates a transfer if the I2C 62 * is in master mode. 63 */ 64 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ 65 66 /* 67 * I2C Interrupt Registers Bit mask definitions 68 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 69 * bit definitions. 70 */ 71 #define CDNS_I2C_IXR_ARB_LOST BIT(9) 72 #define CDNS_I2C_IXR_RX_UNF BIT(7) 73 #define CDNS_I2C_IXR_TX_OVF BIT(6) 74 #define CDNS_I2C_IXR_RX_OVF BIT(5) 75 #define CDNS_I2C_IXR_SLV_RDY BIT(4) 76 #define CDNS_I2C_IXR_TO BIT(3) 77 #define CDNS_I2C_IXR_NACK BIT(2) 78 #define CDNS_I2C_IXR_DATA BIT(1) 79 #define CDNS_I2C_IXR_COMP BIT(0) 80 81 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 82 CDNS_I2C_IXR_RX_UNF | \ 83 CDNS_I2C_IXR_TX_OVF | \ 84 CDNS_I2C_IXR_RX_OVF | \ 85 CDNS_I2C_IXR_SLV_RDY | \ 86 CDNS_I2C_IXR_TO | \ 87 CDNS_I2C_IXR_NACK | \ 88 CDNS_I2C_IXR_DATA | \ 89 CDNS_I2C_IXR_COMP) 90 91 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 92 CDNS_I2C_IXR_RX_UNF | \ 93 CDNS_I2C_IXR_TX_OVF | \ 94 CDNS_I2C_IXR_RX_OVF | \ 95 CDNS_I2C_IXR_NACK) 96 97 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 98 CDNS_I2C_IXR_RX_UNF | \ 99 CDNS_I2C_IXR_TX_OVF | \ 100 CDNS_I2C_IXR_RX_OVF | \ 101 CDNS_I2C_IXR_NACK | \ 102 CDNS_I2C_IXR_DATA | \ 103 CDNS_I2C_IXR_COMP) 104 105 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \ 106 CDNS_I2C_IXR_TX_OVF | \ 107 CDNS_I2C_IXR_RX_OVF | \ 108 CDNS_I2C_IXR_TO | \ 109 CDNS_I2C_IXR_NACK | \ 110 CDNS_I2C_IXR_DATA | \ 111 CDNS_I2C_IXR_COMP) 112 113 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) 114 /* timeout for pm runtime autosuspend */ 115 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ 116 117 #define CDNS_I2C_FIFO_DEPTH 16 118 #define CDNS_I2C_MAX_TRANSFER_SIZE 255 119 /* Transfer size in multiples of data interrupt depth */ 120 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3) 121 122 #define DRIVER_NAME "cdns-i2c" 123 124 #define CDNS_I2C_DIVA_MAX 4 125 #define CDNS_I2C_DIVB_MAX 64 126 127 #define CDNS_I2C_TIMEOUT_MAX 0xFF 128 129 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 130 #define CDNS_I2C_POLL_US 100000 131 #define CDNS_I2C_TIMEOUT_US 500000 132 133 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) 134 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) 135 136 #if IS_ENABLED(CONFIG_I2C_SLAVE) 137 /** 138 * enum cdns_i2c_mode - I2C Controller current operating mode 139 * 140 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode 141 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode 142 */ 143 enum cdns_i2c_mode { 144 CDNS_I2C_MODE_SLAVE, 145 CDNS_I2C_MODE_MASTER, 146 }; 147 148 /** 149 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode 150 * 151 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle 152 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master 153 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master 154 */ 155 enum cdns_i2c_slave_state { 156 CDNS_I2C_SLAVE_STATE_IDLE, 157 CDNS_I2C_SLAVE_STATE_SEND, 158 CDNS_I2C_SLAVE_STATE_RECV, 159 }; 160 #endif 161 162 /** 163 * struct cdns_i2c - I2C device private data structure 164 * 165 * @dev: Pointer to device structure 166 * @membase: Base address of the I2C device 167 * @adap: I2C adapter instance 168 * @p_msg: Message pointer 169 * @err_status: Error status in Interrupt Status Register 170 * @xfer_done: Transfer complete status 171 * @p_send_buf: Pointer to transmit buffer 172 * @p_recv_buf: Pointer to receive buffer 173 * @send_count: Number of bytes still expected to send 174 * @recv_count: Number of bytes still expected to receive 175 * @curr_recv_count: Number of bytes to be received in current transfer 176 * @input_clk: Input clock to I2C controller 177 * @i2c_clk: Maximum I2C clock speed 178 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit 179 * @clk: Pointer to struct clk 180 * @clk_rate_change_nb: Notifier block for clock rate changes 181 * @quirks: flag for broken hold bit usage in r1p10 182 * @ctrl_reg: Cached value of the control register. 183 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register 184 * @slave: Registered slave instance. 185 * @dev_mode: I2C operating role(master/slave). 186 * @slave_state: I2C Slave state(idle/read/write). 187 */ 188 struct cdns_i2c { 189 struct device *dev; 190 void __iomem *membase; 191 struct i2c_adapter adap; 192 struct i2c_msg *p_msg; 193 int err_status; 194 struct completion xfer_done; 195 unsigned char *p_send_buf; 196 unsigned char *p_recv_buf; 197 unsigned int send_count; 198 unsigned int recv_count; 199 unsigned int curr_recv_count; 200 unsigned long input_clk; 201 unsigned int i2c_clk; 202 unsigned int bus_hold_flag; 203 struct clk *clk; 204 struct notifier_block clk_rate_change_nb; 205 u32 quirks; 206 u32 ctrl_reg; 207 struct i2c_bus_recovery_info rinfo; 208 #if IS_ENABLED(CONFIG_I2C_SLAVE) 209 u16 ctrl_reg_diva_divb; 210 struct i2c_client *slave; 211 enum cdns_i2c_mode dev_mode; 212 enum cdns_i2c_slave_state slave_state; 213 #endif 214 }; 215 216 struct cdns_platform_data { 217 u32 quirks; 218 }; 219 220 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ 221 clk_rate_change_nb) 222 223 /** 224 * cdns_i2c_clear_bus_hold - Clear bus hold bit 225 * @id: Pointer to driver data struct 226 * 227 * Helper to clear the controller's bus hold bit. 228 */ 229 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) 230 { 231 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 232 if (reg & CDNS_I2C_CR_HOLD) 233 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); 234 } 235 236 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) 237 { 238 return (hold_wrkaround && 239 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); 240 } 241 242 #if IS_ENABLED(CONFIG_I2C_SLAVE) 243 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) 244 { 245 /* Disable all interrupts */ 246 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 247 248 /* Clear FIFO and transfer size */ 249 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 250 251 /* Update device mode and state */ 252 id->dev_mode = mode; 253 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 254 255 switch (mode) { 256 case CDNS_I2C_MODE_MASTER: 257 /* Enable i2c master */ 258 cdns_i2c_writereg(id->ctrl_reg_diva_divb | 259 CDNS_I2C_CR_MASTER_EN_MASK, 260 CDNS_I2C_CR_OFFSET); 261 /* 262 * This delay is needed to give the IP some time to switch to 263 * the master mode. With lower values(like 110 us) i2cdetect 264 * will not detect any slave and without this delay, the IP will 265 * trigger a timeout interrupt. 266 */ 267 usleep_range(115, 125); 268 break; 269 case CDNS_I2C_MODE_SLAVE: 270 /* Enable i2c slave */ 271 cdns_i2c_writereg(id->ctrl_reg_diva_divb & 272 CDNS_I2C_CR_SLAVE_EN_MASK, 273 CDNS_I2C_CR_OFFSET); 274 275 /* Setting slave address */ 276 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK, 277 CDNS_I2C_ADDR_OFFSET); 278 279 /* Enable slave send/receive interrupts */ 280 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK, 281 CDNS_I2C_IER_OFFSET); 282 break; 283 } 284 } 285 286 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) 287 { 288 u8 bytes; 289 unsigned char data; 290 291 /* Prepare backend for data reception */ 292 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 293 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV; 294 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL); 295 } 296 297 /* Fetch number of bytes to receive */ 298 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 299 300 /* Read data and send to backend */ 301 while (bytes--) { 302 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 303 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data); 304 } 305 } 306 307 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) 308 { 309 u8 data; 310 311 /* Prepare backend for data transmission */ 312 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 313 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND; 314 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data); 315 } else { 316 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data); 317 } 318 319 /* Send data over bus */ 320 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET); 321 } 322 323 /** 324 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role 325 * @ptr: Pointer to I2C device private data 326 * 327 * This function handles the data interrupt and transfer complete interrupt of 328 * the I2C device in slave role. 329 * 330 * Return: IRQ_HANDLED always 331 */ 332 static irqreturn_t cdns_i2c_slave_isr(void *ptr) 333 { 334 struct cdns_i2c *id = ptr; 335 unsigned int isr_status, i2c_status; 336 337 /* Fetch the interrupt status */ 338 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 339 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 340 341 /* Ignore masked interrupts */ 342 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET); 343 344 /* Fetch transfer mode (send/receive) */ 345 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 346 347 /* Handle data send/receive */ 348 if (i2c_status & CDNS_I2C_SR_RXRW) { 349 /* Send data to master */ 350 if (isr_status & CDNS_I2C_IXR_DATA) 351 cdns_i2c_slave_send_data(id); 352 353 if (isr_status & CDNS_I2C_IXR_COMP) { 354 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 355 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 356 } 357 } else { 358 /* Receive data from master */ 359 if (isr_status & CDNS_I2C_IXR_DATA) 360 cdns_i2c_slave_rcv_data(id); 361 362 if (isr_status & CDNS_I2C_IXR_COMP) { 363 cdns_i2c_slave_rcv_data(id); 364 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 365 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 366 } 367 } 368 369 /* Master indicated xfer stop or fifo underflow/overflow */ 370 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF | 371 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) { 372 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 373 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 374 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 375 } 376 377 return IRQ_HANDLED; 378 } 379 #endif 380 381 /** 382 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role 383 * @ptr: Pointer to I2C device private data 384 * 385 * This function handles the data interrupt, transfer complete interrupt and 386 * the error interrupts of the I2C device in master role. 387 * 388 * Return: IRQ_HANDLED always 389 */ 390 static irqreturn_t cdns_i2c_master_isr(void *ptr) 391 { 392 unsigned int isr_status, avail_bytes; 393 unsigned int bytes_to_send; 394 bool updatetx; 395 struct cdns_i2c *id = ptr; 396 /* Signal completion only after everything is updated */ 397 int done_flag = 0; 398 irqreturn_t status = IRQ_NONE; 399 400 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 401 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 402 id->err_status = 0; 403 404 /* Handling nack and arbitration lost interrupt */ 405 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { 406 done_flag = 1; 407 status = IRQ_HANDLED; 408 } 409 410 /* 411 * Check if transfer size register needs to be updated again for a 412 * large data receive operation. 413 */ 414 updatetx = id->recv_count > id->curr_recv_count; 415 416 /* When receiving, handle data interrupt and completion interrupt */ 417 if (id->p_recv_buf && 418 ((isr_status & CDNS_I2C_IXR_COMP) || 419 (isr_status & CDNS_I2C_IXR_DATA))) { 420 /* Read data if receive data valid is set */ 421 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 422 CDNS_I2C_SR_RXDV) { 423 if (id->recv_count > 0) { 424 *(id->p_recv_buf)++ = 425 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 426 id->recv_count--; 427 id->curr_recv_count--; 428 429 /* 430 * Clear hold bit that was set for FIFO control 431 * if RX data left is less than or equal to 432 * FIFO DEPTH unless repeated start is selected 433 */ 434 if (id->recv_count <= CDNS_I2C_FIFO_DEPTH && 435 !id->bus_hold_flag) 436 cdns_i2c_clear_bus_hold(id); 437 438 } else { 439 dev_err(id->adap.dev.parent, 440 "xfer_size reg rollover. xfer aborted!\n"); 441 id->err_status |= CDNS_I2C_IXR_TO; 442 break; 443 } 444 445 if (cdns_is_holdquirk(id, updatetx)) 446 break; 447 } 448 449 /* 450 * The controller sends NACK to the slave when transfer size 451 * register reaches zero without considering the HOLD bit. 452 * This workaround is implemented for large data transfers to 453 * maintain transfer size non-zero while performing a large 454 * receive operation. 455 */ 456 if (cdns_is_holdquirk(id, updatetx)) { 457 /* wait while fifo is full */ 458 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 459 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) 460 ; 461 462 /* 463 * Check number of bytes to be received against maximum 464 * transfer size and update register accordingly. 465 */ 466 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > 467 CDNS_I2C_TRANSFER_SIZE) { 468 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 469 CDNS_I2C_XFER_SIZE_OFFSET); 470 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + 471 CDNS_I2C_FIFO_DEPTH; 472 } else { 473 cdns_i2c_writereg(id->recv_count - 474 CDNS_I2C_FIFO_DEPTH, 475 CDNS_I2C_XFER_SIZE_OFFSET); 476 id->curr_recv_count = id->recv_count; 477 } 478 } 479 480 /* Clear hold (if not repeated start) and signal completion */ 481 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { 482 if (!id->bus_hold_flag) 483 cdns_i2c_clear_bus_hold(id); 484 done_flag = 1; 485 } 486 487 status = IRQ_HANDLED; 488 } 489 490 /* When sending, handle transfer complete interrupt */ 491 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { 492 /* 493 * If there is more data to be sent, calculate the 494 * space available in FIFO and fill with that many bytes. 495 */ 496 if (id->send_count) { 497 avail_bytes = CDNS_I2C_FIFO_DEPTH - 498 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 499 if (id->send_count > avail_bytes) 500 bytes_to_send = avail_bytes; 501 else 502 bytes_to_send = id->send_count; 503 504 while (bytes_to_send--) { 505 cdns_i2c_writereg( 506 (*(id->p_send_buf)++), 507 CDNS_I2C_DATA_OFFSET); 508 id->send_count--; 509 } 510 } else { 511 /* 512 * Signal the completion of transaction and 513 * clear the hold bus bit if there are no 514 * further messages to be processed. 515 */ 516 done_flag = 1; 517 } 518 if (!id->send_count && !id->bus_hold_flag) 519 cdns_i2c_clear_bus_hold(id); 520 521 status = IRQ_HANDLED; 522 } 523 524 /* Update the status for errors */ 525 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 526 if (id->err_status) 527 status = IRQ_HANDLED; 528 529 if (done_flag) 530 complete(&id->xfer_done); 531 532 return status; 533 } 534 535 /** 536 * cdns_i2c_isr - Interrupt handler for the I2C device 537 * @irq: irq number for the I2C device 538 * @ptr: void pointer to cdns_i2c structure 539 * 540 * This function passes the control to slave/master based on current role of 541 * i2c controller. 542 * 543 * Return: IRQ_HANDLED always 544 */ 545 static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 546 { 547 #if IS_ENABLED(CONFIG_I2C_SLAVE) 548 struct cdns_i2c *id = ptr; 549 550 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) 551 return cdns_i2c_slave_isr(ptr); 552 #endif 553 return cdns_i2c_master_isr(ptr); 554 } 555 556 /** 557 * cdns_i2c_mrecv - Prepare and start a master receive operation 558 * @id: pointer to the i2c device structure 559 */ 560 static void cdns_i2c_mrecv(struct cdns_i2c *id) 561 { 562 unsigned int ctrl_reg; 563 unsigned int isr_status; 564 unsigned long flags; 565 bool hold_clear = false; 566 bool irq_save = false; 567 568 u32 addr; 569 570 id->p_recv_buf = id->p_msg->buf; 571 id->recv_count = id->p_msg->len; 572 573 /* Put the controller in master receive mode and clear the FIFO */ 574 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 575 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; 576 577 /* 578 * Receive up to I2C_SMBUS_BLOCK_MAX data bytes, plus one message length 579 * byte, plus one checksum byte if PEC is enabled. p_msg->len will be 2 if 580 * PEC is enabled, otherwise 1. 581 */ 582 if (id->p_msg->flags & I2C_M_RECV_LEN) 583 id->recv_count = I2C_SMBUS_BLOCK_MAX + id->p_msg->len; 584 585 id->curr_recv_count = id->recv_count; 586 587 /* 588 * Check for the message size against FIFO depth and set the 589 * 'hold bus' bit if it is greater than FIFO depth. 590 */ 591 if (id->recv_count > CDNS_I2C_FIFO_DEPTH) 592 ctrl_reg |= CDNS_I2C_CR_HOLD; 593 594 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 595 596 /* Clear the interrupts in interrupt status register */ 597 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 598 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 599 600 /* 601 * The no. of bytes to receive is checked against the limit of 602 * max transfer size. Set transfer size register with no of bytes 603 * receive if it is less than transfer size and transfer size if 604 * it is more. Enable the interrupts. 605 */ 606 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 607 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 608 CDNS_I2C_XFER_SIZE_OFFSET); 609 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 610 } else { 611 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 612 } 613 614 /* Determine hold_clear based on number of bytes to receive and hold flag */ 615 if (!id->bus_hold_flag && id->recv_count <= CDNS_I2C_FIFO_DEPTH) { 616 if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) { 617 hold_clear = true; 618 if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) 619 irq_save = true; 620 } 621 } 622 623 addr = id->p_msg->addr; 624 addr &= CDNS_I2C_ADDR_MASK; 625 626 if (hold_clear) { 627 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD; 628 /* 629 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size 630 * register reaches '0'. This is an IP bug which causes transfer size 631 * register overflow to 0xFF. To satisfy this timing requirement, 632 * disable the interrupts on current processor core between register 633 * writes to slave address register and control register. 634 */ 635 if (irq_save) 636 local_irq_save(flags); 637 638 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 639 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 640 /* Read it back to avoid bufferring and make sure write happens */ 641 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 642 643 if (irq_save) 644 local_irq_restore(flags); 645 } else { 646 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 647 } 648 649 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 650 } 651 652 /** 653 * cdns_i2c_msend - Prepare and start a master send operation 654 * @id: pointer to the i2c device 655 */ 656 static void cdns_i2c_msend(struct cdns_i2c *id) 657 { 658 unsigned int avail_bytes; 659 unsigned int bytes_to_send; 660 unsigned int ctrl_reg; 661 unsigned int isr_status; 662 663 id->p_recv_buf = NULL; 664 id->p_send_buf = id->p_msg->buf; 665 id->send_count = id->p_msg->len; 666 667 /* Set the controller in Master transmit mode and clear the FIFO. */ 668 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 669 ctrl_reg &= ~CDNS_I2C_CR_RW; 670 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; 671 672 /* 673 * Check for the message size against FIFO depth and set the 674 * 'hold bus' bit if it is greater than FIFO depth. 675 */ 676 if (id->send_count > CDNS_I2C_FIFO_DEPTH) 677 ctrl_reg |= CDNS_I2C_CR_HOLD; 678 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 679 680 /* Clear the interrupts in interrupt status register. */ 681 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 682 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 683 684 /* 685 * Calculate the space available in FIFO. Check the message length 686 * against the space available, and fill the FIFO accordingly. 687 * Enable the interrupts. 688 */ 689 avail_bytes = CDNS_I2C_FIFO_DEPTH - 690 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 691 692 if (id->send_count > avail_bytes) 693 bytes_to_send = avail_bytes; 694 else 695 bytes_to_send = id->send_count; 696 697 while (bytes_to_send--) { 698 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); 699 id->send_count--; 700 } 701 702 /* 703 * Clear the bus hold flag if there is no more data 704 * and if it is the last message. 705 */ 706 if (!id->bus_hold_flag && !id->send_count) 707 cdns_i2c_clear_bus_hold(id); 708 /* Set the slave address in address register - triggers operation. */ 709 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 710 CDNS_I2C_ADDR_OFFSET); 711 712 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 713 } 714 715 /** 716 * cdns_i2c_master_reset - Reset the interface 717 * @adap: pointer to the i2c adapter driver instance 718 * 719 * This function cleanup the fifos, clear the hold bit and status 720 * and disable the interrupts. 721 */ 722 static void cdns_i2c_master_reset(struct i2c_adapter *adap) 723 { 724 struct cdns_i2c *id = adap->algo_data; 725 u32 regval; 726 727 /* Disable the interrupts */ 728 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 729 /* Clear the hold bit and fifos */ 730 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 731 regval &= ~CDNS_I2C_CR_HOLD; 732 regval |= CDNS_I2C_CR_CLR_FIFO; 733 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); 734 /* Update the transfercount register to zero */ 735 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); 736 /* Clear the interrupt status register */ 737 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 738 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); 739 /* Clear the status register */ 740 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 741 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); 742 } 743 744 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, 745 struct i2c_adapter *adap) 746 { 747 unsigned long time_left, msg_timeout; 748 u32 reg; 749 750 id->p_msg = msg; 751 id->err_status = 0; 752 reinit_completion(&id->xfer_done); 753 754 /* Check for the TEN Bit mode on each msg */ 755 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 756 if (msg->flags & I2C_M_TEN) { 757 if (reg & CDNS_I2C_CR_NEA) 758 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, 759 CDNS_I2C_CR_OFFSET); 760 } else { 761 if (!(reg & CDNS_I2C_CR_NEA)) 762 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, 763 CDNS_I2C_CR_OFFSET); 764 } 765 766 /* Check for the R/W flag on each msg */ 767 if (msg->flags & I2C_M_RD) 768 cdns_i2c_mrecv(id); 769 else 770 cdns_i2c_msend(id); 771 772 /* Minimal time to execute this message */ 773 msg_timeout = msecs_to_jiffies((1000 * msg->len * BITS_PER_BYTE) / id->i2c_clk); 774 /* Plus some wiggle room */ 775 msg_timeout += msecs_to_jiffies(500); 776 777 if (msg_timeout < adap->timeout) 778 msg_timeout = adap->timeout; 779 780 /* Wait for the signal of completion */ 781 time_left = wait_for_completion_timeout(&id->xfer_done, msg_timeout); 782 if (time_left == 0) { 783 cdns_i2c_master_reset(adap); 784 dev_err(id->adap.dev.parent, 785 "timeout waiting on completion\n"); 786 return -ETIMEDOUT; 787 } 788 789 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, 790 CDNS_I2C_IDR_OFFSET); 791 792 /* If it is bus arbitration error, try again */ 793 if (id->err_status & CDNS_I2C_IXR_ARB_LOST) 794 return -EAGAIN; 795 796 if (msg->flags & I2C_M_RECV_LEN) 797 msg->len += min_t(unsigned int, msg->buf[0], I2C_SMBUS_BLOCK_MAX); 798 799 return 0; 800 } 801 802 /** 803 * cdns_i2c_master_xfer - The main i2c transfer function 804 * @adap: pointer to the i2c adapter driver instance 805 * @msgs: pointer to the i2c message structure 806 * @num: the number of messages to transfer 807 * 808 * Initiates the send/recv activity based on the transfer message received. 809 * 810 * Return: number of msgs processed on success, negative error otherwise 811 */ 812 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 813 int num) 814 { 815 int ret, count; 816 u32 reg; 817 struct cdns_i2c *id = adap->algo_data; 818 bool hold_quirk; 819 #if IS_ENABLED(CONFIG_I2C_SLAVE) 820 bool change_role = false; 821 #endif 822 823 ret = pm_runtime_resume_and_get(id->dev); 824 if (ret < 0) 825 return ret; 826 827 #if IS_ENABLED(CONFIG_I2C_SLAVE) 828 /* Check i2c operating mode and switch if possible */ 829 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) { 830 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) 831 return -EAGAIN; 832 833 /* Set mode to master */ 834 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 835 836 /* Mark flag to change role once xfer is completed */ 837 change_role = true; 838 } 839 #endif 840 841 /* Check if the bus is free */ 842 843 ret = readl_relaxed_poll_timeout(id->membase + CDNS_I2C_SR_OFFSET, 844 reg, 845 !(reg & CDNS_I2C_SR_BA), 846 CDNS_I2C_POLL_US, CDNS_I2C_TIMEOUT_US); 847 if (ret) { 848 ret = -EAGAIN; 849 if (id->adap.bus_recovery_info) 850 i2c_recover_bus(adap); 851 goto out; 852 } 853 854 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 855 /* 856 * Set the flag to one when multiple messages are to be 857 * processed with a repeated start. 858 */ 859 if (num > 1) { 860 /* 861 * This controller does not give completion interrupt after a 862 * master receive message if HOLD bit is set (repeated start), 863 * resulting in SW timeout. Hence, if a receive message is 864 * followed by any other message, an error is returned 865 * indicating that this sequence is not supported. 866 */ 867 for (count = 0; (count < num - 1 && hold_quirk); count++) { 868 if (msgs[count].flags & I2C_M_RD) { 869 dev_warn(adap->dev.parent, 870 "Can't do repeated start after a receive message\n"); 871 ret = -EOPNOTSUPP; 872 goto out; 873 } 874 } 875 id->bus_hold_flag = 1; 876 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 877 reg |= CDNS_I2C_CR_HOLD; 878 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); 879 } else { 880 id->bus_hold_flag = 0; 881 } 882 883 /* Process the msg one by one */ 884 for (count = 0; count < num; count++, msgs++) { 885 if (count == (num - 1)) 886 id->bus_hold_flag = 0; 887 888 ret = cdns_i2c_process_msg(id, msgs, adap); 889 if (ret) 890 goto out; 891 892 /* Report the other error interrupts to application */ 893 if (id->err_status) { 894 cdns_i2c_master_reset(adap); 895 896 if (id->err_status & CDNS_I2C_IXR_NACK) { 897 ret = -ENXIO; 898 goto out; 899 } 900 ret = -EIO; 901 goto out; 902 } 903 } 904 905 ret = num; 906 907 out: 908 909 #if IS_ENABLED(CONFIG_I2C_SLAVE) 910 /* Switch i2c mode to slave */ 911 if (change_role) 912 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 913 #endif 914 915 pm_runtime_mark_last_busy(id->dev); 916 pm_runtime_put_autosuspend(id->dev); 917 return ret; 918 } 919 920 /** 921 * cdns_i2c_func - Returns the supported features of the I2C driver 922 * @adap: pointer to the i2c adapter structure 923 * 924 * Return: 32 bit value, each bit corresponding to a feature 925 */ 926 static u32 cdns_i2c_func(struct i2c_adapter *adap) 927 { 928 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 929 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 930 I2C_FUNC_SMBUS_BLOCK_DATA; 931 932 #if IS_ENABLED(CONFIG_I2C_SLAVE) 933 func |= I2C_FUNC_SLAVE; 934 #endif 935 936 return func; 937 } 938 939 #if IS_ENABLED(CONFIG_I2C_SLAVE) 940 static int cdns_reg_slave(struct i2c_client *slave) 941 { 942 int ret; 943 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 944 adap); 945 946 if (id->slave) 947 return -EBUSY; 948 949 if (slave->flags & I2C_CLIENT_TEN) 950 return -EAFNOSUPPORT; 951 952 ret = pm_runtime_resume_and_get(id->dev); 953 if (ret < 0) 954 return ret; 955 956 /* Store slave information */ 957 id->slave = slave; 958 959 /* Enable I2C slave */ 960 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 961 962 return 0; 963 } 964 965 static int cdns_unreg_slave(struct i2c_client *slave) 966 { 967 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 968 adap); 969 970 pm_runtime_put(id->dev); 971 972 /* Remove slave information */ 973 id->slave = NULL; 974 975 /* Enable I2C master */ 976 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 977 978 return 0; 979 } 980 #endif 981 982 static const struct i2c_algorithm cdns_i2c_algo = { 983 .master_xfer = cdns_i2c_master_xfer, 984 .functionality = cdns_i2c_func, 985 #if IS_ENABLED(CONFIG_I2C_SLAVE) 986 .reg_slave = cdns_reg_slave, 987 .unreg_slave = cdns_unreg_slave, 988 #endif 989 }; 990 991 /** 992 * cdns_i2c_calc_divs - Calculate clock dividers 993 * @f: I2C clock frequency 994 * @input_clk: Input clock frequency 995 * @a: First divider (return value) 996 * @b: Second divider (return value) 997 * 998 * f is used as input and output variable. As input it is used as target I2C 999 * frequency. On function exit f holds the actually resulting I2C frequency. 1000 * 1001 * Return: 0 on success, negative errno otherwise. 1002 */ 1003 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 1004 unsigned int *a, unsigned int *b) 1005 { 1006 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 1007 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 1008 unsigned int last_error, current_error; 1009 1010 /* calculate (divisor_a+1) x (divisor_b+1) */ 1011 temp = input_clk / (22 * fscl); 1012 1013 /* 1014 * If the calculated value is negative or 0, the fscl input is out of 1015 * range. Return error. 1016 */ 1017 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 1018 return -EINVAL; 1019 1020 last_error = -1; 1021 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 1022 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 1023 1024 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 1025 continue; 1026 div_b--; 1027 1028 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 1029 1030 if (actual_fscl > fscl) 1031 continue; 1032 1033 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 1034 (fscl - actual_fscl)); 1035 1036 if (last_error > current_error) { 1037 calc_div_a = div_a; 1038 calc_div_b = div_b; 1039 best_fscl = actual_fscl; 1040 last_error = current_error; 1041 } 1042 } 1043 1044 *a = calc_div_a; 1045 *b = calc_div_b; 1046 *f = best_fscl; 1047 1048 return 0; 1049 } 1050 1051 /** 1052 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device 1053 * @clk_in: I2C clock input frequency in Hz 1054 * @id: Pointer to the I2C device structure 1055 * 1056 * The device must be idle rather than busy transferring data before setting 1057 * these device options. 1058 * The data rate is set by values in the control register. 1059 * The formula for determining the correct register values is 1060 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) 1061 * See the hardware data sheet for a full explanation of setting the serial 1062 * clock rate. The clock can not be faster than the input clock divide by 22. 1063 * The two most common clock rates are 100KHz and 400KHz. 1064 * 1065 * Return: 0 on success, negative error otherwise 1066 */ 1067 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) 1068 { 1069 unsigned int div_a, div_b; 1070 unsigned int ctrl_reg; 1071 int ret = 0; 1072 unsigned long fscl = id->i2c_clk; 1073 1074 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); 1075 if (ret) 1076 return ret; 1077 1078 ctrl_reg = id->ctrl_reg; 1079 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); 1080 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | 1081 (div_b << CDNS_I2C_CR_DIVB_SHIFT)); 1082 id->ctrl_reg = ctrl_reg; 1083 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 1084 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1085 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK | 1086 CDNS_I2C_CR_DIVB_MASK); 1087 #endif 1088 return 0; 1089 } 1090 1091 /** 1092 * cdns_i2c_clk_notifier_cb - Clock rate change callback 1093 * @nb: Pointer to notifier block 1094 * @event: Notification reason 1095 * @data: Pointer to notification data object 1096 * 1097 * This function is called when the cdns_i2c input clock frequency changes. 1098 * The callback checks whether a valid bus frequency can be generated after the 1099 * change. If so, the change is acknowledged, otherwise the change is aborted. 1100 * New dividers are written to the HW in the pre- or post change notification 1101 * depending on the scaling direction. 1102 * 1103 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 1104 * to acknowledge the change, NOTIFY_DONE if the notification is 1105 * considered irrelevant. 1106 */ 1107 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 1108 event, void *data) 1109 { 1110 struct clk_notifier_data *ndata = data; 1111 struct cdns_i2c *id = to_cdns_i2c(nb); 1112 1113 if (pm_runtime_suspended(id->dev)) 1114 return NOTIFY_OK; 1115 1116 switch (event) { 1117 case PRE_RATE_CHANGE: 1118 { 1119 unsigned long input_clk = ndata->new_rate; 1120 unsigned long fscl = id->i2c_clk; 1121 unsigned int div_a, div_b; 1122 int ret; 1123 1124 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); 1125 if (ret) { 1126 dev_warn(id->adap.dev.parent, 1127 "clock rate change rejected\n"); 1128 return NOTIFY_STOP; 1129 } 1130 1131 /* scale up */ 1132 if (ndata->new_rate > ndata->old_rate) 1133 cdns_i2c_setclk(ndata->new_rate, id); 1134 1135 return NOTIFY_OK; 1136 } 1137 case POST_RATE_CHANGE: 1138 id->input_clk = ndata->new_rate; 1139 /* scale down */ 1140 if (ndata->new_rate < ndata->old_rate) 1141 cdns_i2c_setclk(ndata->new_rate, id); 1142 return NOTIFY_OK; 1143 case ABORT_RATE_CHANGE: 1144 /* scale up */ 1145 if (ndata->new_rate > ndata->old_rate) 1146 cdns_i2c_setclk(ndata->old_rate, id); 1147 return NOTIFY_OK; 1148 default: 1149 return NOTIFY_DONE; 1150 } 1151 } 1152 1153 /** 1154 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver 1155 * @dev: Address of the platform_device structure 1156 * 1157 * Put the driver into low power mode. 1158 * 1159 * Return: 0 always 1160 */ 1161 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 1162 { 1163 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1164 1165 clk_disable(xi2c->clk); 1166 1167 return 0; 1168 } 1169 1170 /** 1171 * cdns_i2c_init - Controller initialisation 1172 * @id: Device private data structure 1173 * 1174 * Initialise the i2c controller. 1175 * 1176 */ 1177 static void cdns_i2c_init(struct cdns_i2c *id) 1178 { 1179 cdns_i2c_writereg(id->ctrl_reg, CDNS_I2C_CR_OFFSET); 1180 /* 1181 * Cadence I2C controller has a bug wherein it generates 1182 * invalid read transaction after HW timeout in master receiver mode. 1183 * HW timeout is not used by this driver and the interrupt is disabled. 1184 * But the feature itself cannot be disabled. Hence maximum value 1185 * is written to this register to reduce the chances of error. 1186 */ 1187 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); 1188 } 1189 1190 /** 1191 * cdns_i2c_runtime_resume - Runtime resume 1192 * @dev: Address of the platform_device structure 1193 * 1194 * Runtime resume callback. 1195 * 1196 * Return: 0 on success and error value on error 1197 */ 1198 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 1199 { 1200 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1201 int ret; 1202 1203 ret = clk_enable(xi2c->clk); 1204 if (ret) { 1205 dev_err(dev, "Cannot enable clock.\n"); 1206 return ret; 1207 } 1208 cdns_i2c_init(xi2c); 1209 1210 return 0; 1211 } 1212 1213 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { 1214 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, 1215 cdns_i2c_runtime_resume, NULL) 1216 }; 1217 1218 static const struct cdns_platform_data r1p10_i2c_def = { 1219 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 1220 }; 1221 1222 static const struct of_device_id cdns_i2c_of_match[] = { 1223 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, 1224 { .compatible = "cdns,i2c-r1p14",}, 1225 { /* end of table */ } 1226 }; 1227 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); 1228 1229 /** 1230 * cdns_i2c_probe - Platform registration call 1231 * @pdev: Handle to the platform device structure 1232 * 1233 * This function does all the memory allocation and registration for the i2c 1234 * device. User can modify the address mode to 10 bit address mode using the 1235 * ioctl call with option I2C_TENBIT. 1236 * 1237 * Return: 0 on success, negative error otherwise 1238 */ 1239 static int cdns_i2c_probe(struct platform_device *pdev) 1240 { 1241 struct resource *r_mem; 1242 struct cdns_i2c *id; 1243 int ret, irq; 1244 const struct of_device_id *match; 1245 1246 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); 1247 if (!id) 1248 return -ENOMEM; 1249 1250 id->dev = &pdev->dev; 1251 platform_set_drvdata(pdev, id); 1252 1253 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); 1254 if (match && match->data) { 1255 const struct cdns_platform_data *data = match->data; 1256 id->quirks = data->quirks; 1257 } 1258 1259 id->rinfo.pinctrl = devm_pinctrl_get(&pdev->dev); 1260 if (IS_ERR(id->rinfo.pinctrl)) { 1261 int err = PTR_ERR(id->rinfo.pinctrl); 1262 1263 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1264 if (err != -ENODEV) 1265 return err; 1266 } else { 1267 id->adap.bus_recovery_info = &id->rinfo; 1268 } 1269 1270 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem); 1271 if (IS_ERR(id->membase)) 1272 return PTR_ERR(id->membase); 1273 1274 irq = platform_get_irq(pdev, 0); 1275 if (irq < 0) 1276 return irq; 1277 1278 id->adap.owner = THIS_MODULE; 1279 id->adap.dev.of_node = pdev->dev.of_node; 1280 id->adap.algo = &cdns_i2c_algo; 1281 id->adap.timeout = CDNS_I2C_TIMEOUT; 1282 id->adap.retries = 3; /* Default retry value. */ 1283 id->adap.algo_data = id; 1284 id->adap.dev.parent = &pdev->dev; 1285 init_completion(&id->xfer_done); 1286 snprintf(id->adap.name, sizeof(id->adap.name), 1287 "Cadence I2C at %08lx", (unsigned long)r_mem->start); 1288 1289 id->clk = devm_clk_get(&pdev->dev, NULL); 1290 if (IS_ERR(id->clk)) 1291 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk), 1292 "input clock not found.\n"); 1293 1294 ret = clk_prepare_enable(id->clk); 1295 if (ret) 1296 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1297 1298 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); 1299 pm_runtime_use_autosuspend(id->dev); 1300 pm_runtime_set_active(id->dev); 1301 pm_runtime_enable(id->dev); 1302 1303 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; 1304 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) 1305 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1306 id->input_clk = clk_get_rate(id->clk); 1307 1308 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1309 &id->i2c_clk); 1310 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ)) 1311 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ; 1312 1313 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1314 /* Set initial mode to master */ 1315 id->dev_mode = CDNS_I2C_MODE_MASTER; 1316 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 1317 #endif 1318 id->ctrl_reg = CDNS_I2C_CR_ACK_EN | CDNS_I2C_CR_NEA | CDNS_I2C_CR_MS; 1319 1320 ret = cdns_i2c_setclk(id->input_clk, id); 1321 if (ret) { 1322 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); 1323 ret = -EINVAL; 1324 goto err_clk_dis; 1325 } 1326 1327 ret = devm_request_irq(&pdev->dev, irq, cdns_i2c_isr, 0, 1328 DRIVER_NAME, id); 1329 if (ret) { 1330 dev_err(&pdev->dev, "cannot get irq %d\n", irq); 1331 goto err_clk_dis; 1332 } 1333 cdns_i2c_init(id); 1334 1335 ret = i2c_add_adapter(&id->adap); 1336 if (ret < 0) 1337 goto err_clk_dis; 1338 1339 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", 1340 id->i2c_clk / 1000, (unsigned long)r_mem->start, irq); 1341 1342 return 0; 1343 1344 err_clk_dis: 1345 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1346 clk_disable_unprepare(id->clk); 1347 pm_runtime_disable(&pdev->dev); 1348 pm_runtime_set_suspended(&pdev->dev); 1349 return ret; 1350 } 1351 1352 /** 1353 * cdns_i2c_remove - Unregister the device after releasing the resources 1354 * @pdev: Handle to the platform device structure 1355 * 1356 * This function frees all the resources allocated to the device. 1357 * 1358 * Return: 0 always 1359 */ 1360 static int cdns_i2c_remove(struct platform_device *pdev) 1361 { 1362 struct cdns_i2c *id = platform_get_drvdata(pdev); 1363 1364 pm_runtime_disable(&pdev->dev); 1365 pm_runtime_set_suspended(&pdev->dev); 1366 pm_runtime_dont_use_autosuspend(&pdev->dev); 1367 1368 i2c_del_adapter(&id->adap); 1369 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1370 clk_disable_unprepare(id->clk); 1371 1372 return 0; 1373 } 1374 1375 static struct platform_driver cdns_i2c_drv = { 1376 .driver = { 1377 .name = DRIVER_NAME, 1378 .of_match_table = cdns_i2c_of_match, 1379 .pm = &cdns_i2c_dev_pm_ops, 1380 }, 1381 .probe = cdns_i2c_probe, 1382 .remove = cdns_i2c_remove, 1383 }; 1384 1385 module_platform_driver(cdns_i2c_drv); 1386 1387 MODULE_AUTHOR("Xilinx Inc."); 1388 MODULE_DESCRIPTION("Cadence I2C bus driver"); 1389 MODULE_LICENSE("GPL"); 1390