1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * I2C bus driver for the Cadence I2C controller. 4 * 5 * Copyright (C) 2009 - 2014 Xilinx, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/i2c.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/pm_runtime.h> 17 18 /* Register offsets for the I2C device. */ 19 #define CDNS_I2C_CR_OFFSET 0x00 /* Control Register, RW */ 20 #define CDNS_I2C_SR_OFFSET 0x04 /* Status Register, RO */ 21 #define CDNS_I2C_ADDR_OFFSET 0x08 /* I2C Address Register, RW */ 22 #define CDNS_I2C_DATA_OFFSET 0x0C /* I2C Data Register, RW */ 23 #define CDNS_I2C_ISR_OFFSET 0x10 /* IRQ Status Register, RW */ 24 #define CDNS_I2C_XFER_SIZE_OFFSET 0x14 /* Transfer Size Register, RW */ 25 #define CDNS_I2C_TIME_OUT_OFFSET 0x1C /* Time Out Register, RW */ 26 #define CDNS_I2C_IMR_OFFSET 0x20 /* IRQ Mask Register, RO */ 27 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */ 28 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */ 29 30 /* Control Register Bit mask definitions */ 31 #define CDNS_I2C_CR_HOLD BIT(4) /* Hold Bus bit */ 32 #define CDNS_I2C_CR_ACK_EN BIT(3) 33 #define CDNS_I2C_CR_NEA BIT(2) 34 #define CDNS_I2C_CR_MS BIT(1) 35 /* Read or Write Master transfer 0 = Transmitter, 1 = Receiver */ 36 #define CDNS_I2C_CR_RW BIT(0) 37 /* 1 = Auto init FIFO to zeroes */ 38 #define CDNS_I2C_CR_CLR_FIFO BIT(6) 39 #define CDNS_I2C_CR_DIVA_SHIFT 14 40 #define CDNS_I2C_CR_DIVA_MASK (3 << CDNS_I2C_CR_DIVA_SHIFT) 41 #define CDNS_I2C_CR_DIVB_SHIFT 8 42 #define CDNS_I2C_CR_DIVB_MASK (0x3f << CDNS_I2C_CR_DIVB_SHIFT) 43 44 #define CDNS_I2C_CR_MASTER_EN_MASK (CDNS_I2C_CR_NEA | \ 45 CDNS_I2C_CR_ACK_EN | \ 46 CDNS_I2C_CR_MS) 47 48 #define CDNS_I2C_CR_SLAVE_EN_MASK ~CDNS_I2C_CR_MASTER_EN_MASK 49 50 /* Status Register Bit mask definitions */ 51 #define CDNS_I2C_SR_BA BIT(8) 52 #define CDNS_I2C_SR_TXDV BIT(6) 53 #define CDNS_I2C_SR_RXDV BIT(5) 54 #define CDNS_I2C_SR_RXRW BIT(3) 55 56 /* 57 * I2C Address Register Bit mask definitions 58 * Normal addressing mode uses [6:0] bits. Extended addressing mode uses [9:0] 59 * bits. A write access to this register always initiates a transfer if the I2C 60 * is in master mode. 61 */ 62 #define CDNS_I2C_ADDR_MASK 0x000003FF /* I2C Address Mask */ 63 64 /* 65 * I2C Interrupt Registers Bit mask definitions 66 * All the four interrupt registers (Status/Mask/Enable/Disable) have the same 67 * bit definitions. 68 */ 69 #define CDNS_I2C_IXR_ARB_LOST BIT(9) 70 #define CDNS_I2C_IXR_RX_UNF BIT(7) 71 #define CDNS_I2C_IXR_TX_OVF BIT(6) 72 #define CDNS_I2C_IXR_RX_OVF BIT(5) 73 #define CDNS_I2C_IXR_SLV_RDY BIT(4) 74 #define CDNS_I2C_IXR_TO BIT(3) 75 #define CDNS_I2C_IXR_NACK BIT(2) 76 #define CDNS_I2C_IXR_DATA BIT(1) 77 #define CDNS_I2C_IXR_COMP BIT(0) 78 79 #define CDNS_I2C_IXR_ALL_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 80 CDNS_I2C_IXR_RX_UNF | \ 81 CDNS_I2C_IXR_TX_OVF | \ 82 CDNS_I2C_IXR_RX_OVF | \ 83 CDNS_I2C_IXR_SLV_RDY | \ 84 CDNS_I2C_IXR_TO | \ 85 CDNS_I2C_IXR_NACK | \ 86 CDNS_I2C_IXR_DATA | \ 87 CDNS_I2C_IXR_COMP) 88 89 #define CDNS_I2C_IXR_ERR_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 90 CDNS_I2C_IXR_RX_UNF | \ 91 CDNS_I2C_IXR_TX_OVF | \ 92 CDNS_I2C_IXR_RX_OVF | \ 93 CDNS_I2C_IXR_NACK) 94 95 #define CDNS_I2C_ENABLED_INTR_MASK (CDNS_I2C_IXR_ARB_LOST | \ 96 CDNS_I2C_IXR_RX_UNF | \ 97 CDNS_I2C_IXR_TX_OVF | \ 98 CDNS_I2C_IXR_RX_OVF | \ 99 CDNS_I2C_IXR_NACK | \ 100 CDNS_I2C_IXR_DATA | \ 101 CDNS_I2C_IXR_COMP) 102 103 #define CDNS_I2C_IXR_SLAVE_INTR_MASK (CDNS_I2C_IXR_RX_UNF | \ 104 CDNS_I2C_IXR_TX_OVF | \ 105 CDNS_I2C_IXR_RX_OVF | \ 106 CDNS_I2C_IXR_TO | \ 107 CDNS_I2C_IXR_NACK | \ 108 CDNS_I2C_IXR_DATA | \ 109 CDNS_I2C_IXR_COMP) 110 111 #define CDNS_I2C_TIMEOUT msecs_to_jiffies(1000) 112 /* timeout for pm runtime autosuspend */ 113 #define CNDS_I2C_PM_TIMEOUT 1000 /* ms */ 114 115 #define CDNS_I2C_FIFO_DEPTH 16 116 /* FIFO depth at which the DATA interrupt occurs */ 117 #define CDNS_I2C_DATA_INTR_DEPTH (CDNS_I2C_FIFO_DEPTH - 2) 118 #define CDNS_I2C_MAX_TRANSFER_SIZE 255 119 /* Transfer size in multiples of data interrupt depth */ 120 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_MAX_TRANSFER_SIZE - 3) 121 122 #define DRIVER_NAME "cdns-i2c" 123 124 #define CDNS_I2C_DIVA_MAX 4 125 #define CDNS_I2C_DIVB_MAX 64 126 127 #define CDNS_I2C_TIMEOUT_MAX 0xFF 128 129 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 130 131 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset) 132 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset) 133 134 #if IS_ENABLED(CONFIG_I2C_SLAVE) 135 /** 136 * enum cdns_i2c_mode - I2C Controller current operating mode 137 * 138 * @CDNS_I2C_MODE_SLAVE: I2C controller operating in slave mode 139 * @CDNS_I2C_MODE_MASTER: I2C Controller operating in master mode 140 */ 141 enum cdns_i2c_mode { 142 CDNS_I2C_MODE_SLAVE, 143 CDNS_I2C_MODE_MASTER, 144 }; 145 146 /** 147 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode 148 * 149 * @CDNS_I2C_SLAVE_STATE_IDLE: I2C slave idle 150 * @CDNS_I2C_SLAVE_STATE_SEND: I2C slave sending data to master 151 * @CDNS_I2C_SLAVE_STATE_RECV: I2C slave receiving data from master 152 */ 153 enum cdns_i2c_slave_state { 154 CDNS_I2C_SLAVE_STATE_IDLE, 155 CDNS_I2C_SLAVE_STATE_SEND, 156 CDNS_I2C_SLAVE_STATE_RECV, 157 }; 158 #endif 159 160 /** 161 * struct cdns_i2c - I2C device private data structure 162 * 163 * @dev: Pointer to device structure 164 * @membase: Base address of the I2C device 165 * @adap: I2C adapter instance 166 * @p_msg: Message pointer 167 * @err_status: Error status in Interrupt Status Register 168 * @xfer_done: Transfer complete status 169 * @p_send_buf: Pointer to transmit buffer 170 * @p_recv_buf: Pointer to receive buffer 171 * @send_count: Number of bytes still expected to send 172 * @recv_count: Number of bytes still expected to receive 173 * @curr_recv_count: Number of bytes to be received in current transfer 174 * @irq: IRQ number 175 * @input_clk: Input clock to I2C controller 176 * @i2c_clk: Maximum I2C clock speed 177 * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit 178 * @clk: Pointer to struct clk 179 * @clk_rate_change_nb: Notifier block for clock rate changes 180 * @quirks: flag for broken hold bit usage in r1p10 181 * @ctrl_reg_diva_divb: value of fields DIV_A and DIV_B from CR register 182 * @slave: Registered slave instance. 183 * @dev_mode: I2C operating role(master/slave). 184 * @slave_state: I2C Slave state(idle/read/write). 185 */ 186 struct cdns_i2c { 187 struct device *dev; 188 void __iomem *membase; 189 struct i2c_adapter adap; 190 struct i2c_msg *p_msg; 191 int err_status; 192 struct completion xfer_done; 193 unsigned char *p_send_buf; 194 unsigned char *p_recv_buf; 195 unsigned int send_count; 196 unsigned int recv_count; 197 unsigned int curr_recv_count; 198 int irq; 199 unsigned long input_clk; 200 unsigned int i2c_clk; 201 unsigned int bus_hold_flag; 202 struct clk *clk; 203 struct notifier_block clk_rate_change_nb; 204 u32 quirks; 205 #if IS_ENABLED(CONFIG_I2C_SLAVE) 206 u16 ctrl_reg_diva_divb; 207 struct i2c_client *slave; 208 enum cdns_i2c_mode dev_mode; 209 enum cdns_i2c_slave_state slave_state; 210 #endif 211 }; 212 213 struct cdns_platform_data { 214 u32 quirks; 215 }; 216 217 #define to_cdns_i2c(_nb) container_of(_nb, struct cdns_i2c, \ 218 clk_rate_change_nb) 219 220 /** 221 * cdns_i2c_clear_bus_hold - Clear bus hold bit 222 * @id: Pointer to driver data struct 223 * 224 * Helper to clear the controller's bus hold bit. 225 */ 226 static void cdns_i2c_clear_bus_hold(struct cdns_i2c *id) 227 { 228 u32 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 229 if (reg & CDNS_I2C_CR_HOLD) 230 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET); 231 } 232 233 static inline bool cdns_is_holdquirk(struct cdns_i2c *id, bool hold_wrkaround) 234 { 235 return (hold_wrkaround && 236 (id->curr_recv_count == CDNS_I2C_FIFO_DEPTH + 1)); 237 } 238 239 #if IS_ENABLED(CONFIG_I2C_SLAVE) 240 static void cdns_i2c_set_mode(enum cdns_i2c_mode mode, struct cdns_i2c *id) 241 { 242 /* Disable all interrupts */ 243 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 244 245 /* Clear FIFO and transfer size */ 246 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 247 248 /* Update device mode and state */ 249 id->dev_mode = mode; 250 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 251 252 switch (mode) { 253 case CDNS_I2C_MODE_MASTER: 254 /* Enable i2c master */ 255 cdns_i2c_writereg(id->ctrl_reg_diva_divb | 256 CDNS_I2C_CR_MASTER_EN_MASK, 257 CDNS_I2C_CR_OFFSET); 258 /* 259 * This delay is needed to give the IP some time to switch to 260 * the master mode. With lower values(like 110 us) i2cdetect 261 * will not detect any slave and without this delay, the IP will 262 * trigger a timeout interrupt. 263 */ 264 usleep_range(115, 125); 265 break; 266 case CDNS_I2C_MODE_SLAVE: 267 /* Enable i2c slave */ 268 cdns_i2c_writereg(id->ctrl_reg_diva_divb & 269 CDNS_I2C_CR_SLAVE_EN_MASK, 270 CDNS_I2C_CR_OFFSET); 271 272 /* Setting slave address */ 273 cdns_i2c_writereg(id->slave->addr & CDNS_I2C_ADDR_MASK, 274 CDNS_I2C_ADDR_OFFSET); 275 276 /* Enable slave send/receive interrupts */ 277 cdns_i2c_writereg(CDNS_I2C_IXR_SLAVE_INTR_MASK, 278 CDNS_I2C_IER_OFFSET); 279 break; 280 } 281 } 282 283 static void cdns_i2c_slave_rcv_data(struct cdns_i2c *id) 284 { 285 u8 bytes; 286 unsigned char data; 287 288 /* Prepare backend for data reception */ 289 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 290 id->slave_state = CDNS_I2C_SLAVE_STATE_RECV; 291 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_REQUESTED, NULL); 292 } 293 294 /* Fetch number of bytes to receive */ 295 bytes = cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 296 297 /* Read data and send to backend */ 298 while (bytes--) { 299 data = cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 300 i2c_slave_event(id->slave, I2C_SLAVE_WRITE_RECEIVED, &data); 301 } 302 } 303 304 static void cdns_i2c_slave_send_data(struct cdns_i2c *id) 305 { 306 u8 data; 307 308 /* Prepare backend for data transmission */ 309 if (id->slave_state == CDNS_I2C_SLAVE_STATE_IDLE) { 310 id->slave_state = CDNS_I2C_SLAVE_STATE_SEND; 311 i2c_slave_event(id->slave, I2C_SLAVE_READ_REQUESTED, &data); 312 } else { 313 i2c_slave_event(id->slave, I2C_SLAVE_READ_PROCESSED, &data); 314 } 315 316 /* Send data over bus */ 317 cdns_i2c_writereg(data, CDNS_I2C_DATA_OFFSET); 318 } 319 320 /** 321 * cdns_i2c_slave_isr - Interrupt handler for the I2C device in slave role 322 * @ptr: Pointer to I2C device private data 323 * 324 * This function handles the data interrupt and transfer complete interrupt of 325 * the I2C device in slave role. 326 * 327 * Return: IRQ_HANDLED always 328 */ 329 static irqreturn_t cdns_i2c_slave_isr(void *ptr) 330 { 331 struct cdns_i2c *id = ptr; 332 unsigned int isr_status, i2c_status; 333 334 /* Fetch the interrupt status */ 335 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 336 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 337 338 /* Ignore masked interrupts */ 339 isr_status &= ~cdns_i2c_readreg(CDNS_I2C_IMR_OFFSET); 340 341 /* Fetch transfer mode (send/receive) */ 342 i2c_status = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 343 344 /* Handle data send/receive */ 345 if (i2c_status & CDNS_I2C_SR_RXRW) { 346 /* Send data to master */ 347 if (isr_status & CDNS_I2C_IXR_DATA) 348 cdns_i2c_slave_send_data(id); 349 350 if (isr_status & CDNS_I2C_IXR_COMP) { 351 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 352 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 353 } 354 } else { 355 /* Receive data from master */ 356 if (isr_status & CDNS_I2C_IXR_DATA) 357 cdns_i2c_slave_rcv_data(id); 358 359 if (isr_status & CDNS_I2C_IXR_COMP) { 360 cdns_i2c_slave_rcv_data(id); 361 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 362 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 363 } 364 } 365 366 /* Master indicated xfer stop or fifo underflow/overflow */ 367 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_RX_OVF | 368 CDNS_I2C_IXR_RX_UNF | CDNS_I2C_IXR_TX_OVF)) { 369 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 370 i2c_slave_event(id->slave, I2C_SLAVE_STOP, NULL); 371 cdns_i2c_writereg(CDNS_I2C_CR_CLR_FIFO, CDNS_I2C_CR_OFFSET); 372 } 373 374 return IRQ_HANDLED; 375 } 376 #endif 377 378 /** 379 * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role 380 * @ptr: Pointer to I2C device private data 381 * 382 * This function handles the data interrupt, transfer complete interrupt and 383 * the error interrupts of the I2C device in master role. 384 * 385 * Return: IRQ_HANDLED always 386 */ 387 static irqreturn_t cdns_i2c_master_isr(void *ptr) 388 { 389 unsigned int isr_status, avail_bytes, updatetx; 390 unsigned int bytes_to_send; 391 bool hold_quirk; 392 struct cdns_i2c *id = ptr; 393 /* Signal completion only after everything is updated */ 394 int done_flag = 0; 395 irqreturn_t status = IRQ_NONE; 396 397 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 398 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 399 id->err_status = 0; 400 401 /* Handling nack and arbitration lost interrupt */ 402 if (isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) { 403 done_flag = 1; 404 status = IRQ_HANDLED; 405 } 406 407 /* 408 * Check if transfer size register needs to be updated again for a 409 * large data receive operation. 410 */ 411 updatetx = 0; 412 if (id->recv_count > id->curr_recv_count) 413 updatetx = 1; 414 415 hold_quirk = (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) && updatetx; 416 417 /* When receiving, handle data interrupt and completion interrupt */ 418 if (id->p_recv_buf && 419 ((isr_status & CDNS_I2C_IXR_COMP) || 420 (isr_status & CDNS_I2C_IXR_DATA))) { 421 /* Read data if receive data valid is set */ 422 while (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & 423 CDNS_I2C_SR_RXDV) { 424 if (id->recv_count > 0) { 425 *(id->p_recv_buf)++ = 426 cdns_i2c_readreg(CDNS_I2C_DATA_OFFSET); 427 id->recv_count--; 428 id->curr_recv_count--; 429 430 /* 431 * Clear hold bit that was set for FIFO control 432 * if RX data left is less than or equal to 433 * FIFO DEPTH unless repeated start is selected 434 */ 435 if (id->recv_count <= CDNS_I2C_FIFO_DEPTH && 436 !id->bus_hold_flag) 437 cdns_i2c_clear_bus_hold(id); 438 439 } else { 440 dev_err(id->adap.dev.parent, 441 "xfer_size reg rollover. xfer aborted!\n"); 442 id->err_status |= CDNS_I2C_IXR_TO; 443 break; 444 } 445 446 if (cdns_is_holdquirk(id, hold_quirk)) 447 break; 448 } 449 450 /* 451 * The controller sends NACK to the slave when transfer size 452 * register reaches zero without considering the HOLD bit. 453 * This workaround is implemented for large data transfers to 454 * maintain transfer size non-zero while performing a large 455 * receive operation. 456 */ 457 if (cdns_is_holdquirk(id, hold_quirk)) { 458 /* wait while fifo is full */ 459 while (cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET) != 460 (id->curr_recv_count - CDNS_I2C_FIFO_DEPTH)) 461 ; 462 463 /* 464 * Check number of bytes to be received against maximum 465 * transfer size and update register accordingly. 466 */ 467 if (((int)(id->recv_count) - CDNS_I2C_FIFO_DEPTH) > 468 CDNS_I2C_TRANSFER_SIZE) { 469 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 470 CDNS_I2C_XFER_SIZE_OFFSET); 471 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE + 472 CDNS_I2C_FIFO_DEPTH; 473 } else { 474 cdns_i2c_writereg(id->recv_count - 475 CDNS_I2C_FIFO_DEPTH, 476 CDNS_I2C_XFER_SIZE_OFFSET); 477 id->curr_recv_count = id->recv_count; 478 } 479 } else if (id->recv_count && !hold_quirk && 480 !id->curr_recv_count) { 481 482 /* Set the slave address in address register*/ 483 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 484 CDNS_I2C_ADDR_OFFSET); 485 486 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 487 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 488 CDNS_I2C_XFER_SIZE_OFFSET); 489 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 490 } else { 491 cdns_i2c_writereg(id->recv_count, 492 CDNS_I2C_XFER_SIZE_OFFSET); 493 id->curr_recv_count = id->recv_count; 494 } 495 } 496 497 /* Clear hold (if not repeated start) and signal completion */ 498 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->recv_count) { 499 if (!id->bus_hold_flag) 500 cdns_i2c_clear_bus_hold(id); 501 done_flag = 1; 502 } 503 504 status = IRQ_HANDLED; 505 } 506 507 /* When sending, handle transfer complete interrupt */ 508 if ((isr_status & CDNS_I2C_IXR_COMP) && !id->p_recv_buf) { 509 /* 510 * If there is more data to be sent, calculate the 511 * space available in FIFO and fill with that many bytes. 512 */ 513 if (id->send_count) { 514 avail_bytes = CDNS_I2C_FIFO_DEPTH - 515 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 516 if (id->send_count > avail_bytes) 517 bytes_to_send = avail_bytes; 518 else 519 bytes_to_send = id->send_count; 520 521 while (bytes_to_send--) { 522 cdns_i2c_writereg( 523 (*(id->p_send_buf)++), 524 CDNS_I2C_DATA_OFFSET); 525 id->send_count--; 526 } 527 } else { 528 /* 529 * Signal the completion of transaction and 530 * clear the hold bus bit if there are no 531 * further messages to be processed. 532 */ 533 done_flag = 1; 534 } 535 if (!id->send_count && !id->bus_hold_flag) 536 cdns_i2c_clear_bus_hold(id); 537 538 status = IRQ_HANDLED; 539 } 540 541 /* Update the status for errors */ 542 id->err_status |= isr_status & CDNS_I2C_IXR_ERR_INTR_MASK; 543 if (id->err_status) 544 status = IRQ_HANDLED; 545 546 if (done_flag) 547 complete(&id->xfer_done); 548 549 return status; 550 } 551 552 /** 553 * cdns_i2c_isr - Interrupt handler for the I2C device 554 * @irq: irq number for the I2C device 555 * @ptr: void pointer to cdns_i2c structure 556 * 557 * This function passes the control to slave/master based on current role of 558 * i2c controller. 559 * 560 * Return: IRQ_HANDLED always 561 */ 562 static irqreturn_t cdns_i2c_isr(int irq, void *ptr) 563 { 564 #if IS_ENABLED(CONFIG_I2C_SLAVE) 565 struct cdns_i2c *id = ptr; 566 567 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) 568 return cdns_i2c_slave_isr(ptr); 569 #endif 570 return cdns_i2c_master_isr(ptr); 571 } 572 573 /** 574 * cdns_i2c_mrecv - Prepare and start a master receive operation 575 * @id: pointer to the i2c device structure 576 */ 577 static void cdns_i2c_mrecv(struct cdns_i2c *id) 578 { 579 unsigned int ctrl_reg; 580 unsigned int isr_status; 581 unsigned long flags; 582 bool hold_clear = false; 583 bool irq_save = false; 584 585 u32 addr; 586 587 id->p_recv_buf = id->p_msg->buf; 588 id->recv_count = id->p_msg->len; 589 590 /* Put the controller in master receive mode and clear the FIFO */ 591 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 592 ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO; 593 594 if (id->p_msg->flags & I2C_M_RECV_LEN) 595 id->recv_count = I2C_SMBUS_BLOCK_MAX + 1; 596 597 id->curr_recv_count = id->recv_count; 598 599 /* 600 * Check for the message size against FIFO depth and set the 601 * 'hold bus' bit if it is greater than FIFO depth. 602 */ 603 if (id->recv_count > CDNS_I2C_FIFO_DEPTH) 604 ctrl_reg |= CDNS_I2C_CR_HOLD; 605 606 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 607 608 /* Clear the interrupts in interrupt status register */ 609 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 610 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 611 612 /* 613 * The no. of bytes to receive is checked against the limit of 614 * max transfer size. Set transfer size register with no of bytes 615 * receive if it is less than transfer size and transfer size if 616 * it is more. Enable the interrupts. 617 */ 618 if (id->recv_count > CDNS_I2C_TRANSFER_SIZE) { 619 cdns_i2c_writereg(CDNS_I2C_TRANSFER_SIZE, 620 CDNS_I2C_XFER_SIZE_OFFSET); 621 id->curr_recv_count = CDNS_I2C_TRANSFER_SIZE; 622 } else { 623 cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET); 624 } 625 626 /* Determine hold_clear based on number of bytes to receive and hold flag */ 627 if (!id->bus_hold_flag && 628 ((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) && 629 (id->recv_count <= CDNS_I2C_FIFO_DEPTH)) { 630 if (cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & CDNS_I2C_CR_HOLD) { 631 hold_clear = true; 632 if (id->quirks & CDNS_I2C_BROKEN_HOLD_BIT) 633 irq_save = true; 634 } 635 } 636 637 addr = id->p_msg->addr; 638 addr &= CDNS_I2C_ADDR_MASK; 639 640 if (hold_clear) { 641 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET) & ~CDNS_I2C_CR_HOLD; 642 /* 643 * In case of Xilinx Zynq SOC, clear the HOLD bit before transfer size 644 * register reaches '0'. This is an IP bug which causes transfer size 645 * register overflow to 0xFF. To satisfy this timing requirement, 646 * disable the interrupts on current processor core between register 647 * writes to slave address register and control register. 648 */ 649 if (irq_save) 650 local_irq_save(flags); 651 652 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 653 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 654 /* Read it back to avoid bufferring and make sure write happens */ 655 cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 656 657 if (irq_save) 658 local_irq_restore(flags); 659 } else { 660 cdns_i2c_writereg(addr, CDNS_I2C_ADDR_OFFSET); 661 } 662 663 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 664 } 665 666 /** 667 * cdns_i2c_msend - Prepare and start a master send operation 668 * @id: pointer to the i2c device 669 */ 670 static void cdns_i2c_msend(struct cdns_i2c *id) 671 { 672 unsigned int avail_bytes; 673 unsigned int bytes_to_send; 674 unsigned int ctrl_reg; 675 unsigned int isr_status; 676 677 id->p_recv_buf = NULL; 678 id->p_send_buf = id->p_msg->buf; 679 id->send_count = id->p_msg->len; 680 681 /* Set the controller in Master transmit mode and clear the FIFO. */ 682 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 683 ctrl_reg &= ~CDNS_I2C_CR_RW; 684 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; 685 686 /* 687 * Check for the message size against FIFO depth and set the 688 * 'hold bus' bit if it is greater than FIFO depth. 689 */ 690 if (id->send_count > CDNS_I2C_FIFO_DEPTH) 691 ctrl_reg |= CDNS_I2C_CR_HOLD; 692 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 693 694 /* Clear the interrupts in interrupt status register. */ 695 isr_status = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 696 cdns_i2c_writereg(isr_status, CDNS_I2C_ISR_OFFSET); 697 698 /* 699 * Calculate the space available in FIFO. Check the message length 700 * against the space available, and fill the FIFO accordingly. 701 * Enable the interrupts. 702 */ 703 avail_bytes = CDNS_I2C_FIFO_DEPTH - 704 cdns_i2c_readreg(CDNS_I2C_XFER_SIZE_OFFSET); 705 706 if (id->send_count > avail_bytes) 707 bytes_to_send = avail_bytes; 708 else 709 bytes_to_send = id->send_count; 710 711 while (bytes_to_send--) { 712 cdns_i2c_writereg((*(id->p_send_buf)++), CDNS_I2C_DATA_OFFSET); 713 id->send_count--; 714 } 715 716 /* 717 * Clear the bus hold flag if there is no more data 718 * and if it is the last message. 719 */ 720 if (!id->bus_hold_flag && !id->send_count) 721 cdns_i2c_clear_bus_hold(id); 722 /* Set the slave address in address register - triggers operation. */ 723 cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK, 724 CDNS_I2C_ADDR_OFFSET); 725 726 cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET); 727 } 728 729 /** 730 * cdns_i2c_master_reset - Reset the interface 731 * @adap: pointer to the i2c adapter driver instance 732 * 733 * This function cleanup the fifos, clear the hold bit and status 734 * and disable the interrupts. 735 */ 736 static void cdns_i2c_master_reset(struct i2c_adapter *adap) 737 { 738 struct cdns_i2c *id = adap->algo_data; 739 u32 regval; 740 741 /* Disable the interrupts */ 742 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET); 743 /* Clear the hold bit and fifos */ 744 regval = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 745 regval &= ~CDNS_I2C_CR_HOLD; 746 regval |= CDNS_I2C_CR_CLR_FIFO; 747 cdns_i2c_writereg(regval, CDNS_I2C_CR_OFFSET); 748 /* Update the transfercount register to zero */ 749 cdns_i2c_writereg(0, CDNS_I2C_XFER_SIZE_OFFSET); 750 /* Clear the interrupt status register */ 751 regval = cdns_i2c_readreg(CDNS_I2C_ISR_OFFSET); 752 cdns_i2c_writereg(regval, CDNS_I2C_ISR_OFFSET); 753 /* Clear the status register */ 754 regval = cdns_i2c_readreg(CDNS_I2C_SR_OFFSET); 755 cdns_i2c_writereg(regval, CDNS_I2C_SR_OFFSET); 756 } 757 758 static int cdns_i2c_process_msg(struct cdns_i2c *id, struct i2c_msg *msg, 759 struct i2c_adapter *adap) 760 { 761 unsigned long time_left; 762 u32 reg; 763 764 id->p_msg = msg; 765 id->err_status = 0; 766 reinit_completion(&id->xfer_done); 767 768 /* Check for the TEN Bit mode on each msg */ 769 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 770 if (msg->flags & I2C_M_TEN) { 771 if (reg & CDNS_I2C_CR_NEA) 772 cdns_i2c_writereg(reg & ~CDNS_I2C_CR_NEA, 773 CDNS_I2C_CR_OFFSET); 774 } else { 775 if (!(reg & CDNS_I2C_CR_NEA)) 776 cdns_i2c_writereg(reg | CDNS_I2C_CR_NEA, 777 CDNS_I2C_CR_OFFSET); 778 } 779 780 /* Check for the R/W flag on each msg */ 781 if (msg->flags & I2C_M_RD) 782 cdns_i2c_mrecv(id); 783 else 784 cdns_i2c_msend(id); 785 786 /* Wait for the signal of completion */ 787 time_left = wait_for_completion_timeout(&id->xfer_done, adap->timeout); 788 if (time_left == 0) { 789 cdns_i2c_master_reset(adap); 790 dev_err(id->adap.dev.parent, 791 "timeout waiting on completion\n"); 792 return -ETIMEDOUT; 793 } 794 795 cdns_i2c_writereg(CDNS_I2C_IXR_ALL_INTR_MASK, 796 CDNS_I2C_IDR_OFFSET); 797 798 /* If it is bus arbitration error, try again */ 799 if (id->err_status & CDNS_I2C_IXR_ARB_LOST) 800 return -EAGAIN; 801 802 return 0; 803 } 804 805 /** 806 * cdns_i2c_master_xfer - The main i2c transfer function 807 * @adap: pointer to the i2c adapter driver instance 808 * @msgs: pointer to the i2c message structure 809 * @num: the number of messages to transfer 810 * 811 * Initiates the send/recv activity based on the transfer message received. 812 * 813 * Return: number of msgs processed on success, negative error otherwise 814 */ 815 static int cdns_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 816 int num) 817 { 818 int ret, count; 819 u32 reg; 820 struct cdns_i2c *id = adap->algo_data; 821 bool hold_quirk; 822 #if IS_ENABLED(CONFIG_I2C_SLAVE) 823 bool change_role = false; 824 #endif 825 826 ret = pm_runtime_resume_and_get(id->dev); 827 if (ret < 0) 828 return ret; 829 830 #if IS_ENABLED(CONFIG_I2C_SLAVE) 831 /* Check i2c operating mode and switch if possible */ 832 if (id->dev_mode == CDNS_I2C_MODE_SLAVE) { 833 if (id->slave_state != CDNS_I2C_SLAVE_STATE_IDLE) 834 return -EAGAIN; 835 836 /* Set mode to master */ 837 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 838 839 /* Mark flag to change role once xfer is completed */ 840 change_role = true; 841 } 842 #endif 843 844 /* Check if the bus is free */ 845 if (cdns_i2c_readreg(CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_BA) { 846 ret = -EAGAIN; 847 goto out; 848 } 849 850 hold_quirk = !!(id->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 851 /* 852 * Set the flag to one when multiple messages are to be 853 * processed with a repeated start. 854 */ 855 if (num > 1) { 856 /* 857 * This controller does not give completion interrupt after a 858 * master receive message if HOLD bit is set (repeated start), 859 * resulting in SW timeout. Hence, if a receive message is 860 * followed by any other message, an error is returned 861 * indicating that this sequence is not supported. 862 */ 863 for (count = 0; (count < num - 1 && hold_quirk); count++) { 864 if (msgs[count].flags & I2C_M_RD) { 865 dev_warn(adap->dev.parent, 866 "Can't do repeated start after a receive message\n"); 867 ret = -EOPNOTSUPP; 868 goto out; 869 } 870 } 871 id->bus_hold_flag = 1; 872 reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 873 reg |= CDNS_I2C_CR_HOLD; 874 cdns_i2c_writereg(reg, CDNS_I2C_CR_OFFSET); 875 } else { 876 id->bus_hold_flag = 0; 877 } 878 879 /* Process the msg one by one */ 880 for (count = 0; count < num; count++, msgs++) { 881 if (count == (num - 1)) 882 id->bus_hold_flag = 0; 883 884 ret = cdns_i2c_process_msg(id, msgs, adap); 885 if (ret) 886 goto out; 887 888 /* Report the other error interrupts to application */ 889 if (id->err_status) { 890 cdns_i2c_master_reset(adap); 891 892 if (id->err_status & CDNS_I2C_IXR_NACK) { 893 ret = -ENXIO; 894 goto out; 895 } 896 ret = -EIO; 897 goto out; 898 } 899 } 900 901 ret = num; 902 903 out: 904 905 #if IS_ENABLED(CONFIG_I2C_SLAVE) 906 /* Switch i2c mode to slave */ 907 if (change_role) 908 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 909 #endif 910 911 pm_runtime_mark_last_busy(id->dev); 912 pm_runtime_put_autosuspend(id->dev); 913 return ret; 914 } 915 916 /** 917 * cdns_i2c_func - Returns the supported features of the I2C driver 918 * @adap: pointer to the i2c adapter structure 919 * 920 * Return: 32 bit value, each bit corresponding to a feature 921 */ 922 static u32 cdns_i2c_func(struct i2c_adapter *adap) 923 { 924 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 925 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 926 I2C_FUNC_SMBUS_BLOCK_DATA; 927 928 #if IS_ENABLED(CONFIG_I2C_SLAVE) 929 func |= I2C_FUNC_SLAVE; 930 #endif 931 932 return func; 933 } 934 935 #if IS_ENABLED(CONFIG_I2C_SLAVE) 936 static int cdns_reg_slave(struct i2c_client *slave) 937 { 938 int ret; 939 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 940 adap); 941 942 if (id->slave) 943 return -EBUSY; 944 945 if (slave->flags & I2C_CLIENT_TEN) 946 return -EAFNOSUPPORT; 947 948 ret = pm_runtime_resume_and_get(id->dev); 949 if (ret < 0) 950 return ret; 951 952 /* Store slave information */ 953 id->slave = slave; 954 955 /* Enable I2C slave */ 956 cdns_i2c_set_mode(CDNS_I2C_MODE_SLAVE, id); 957 958 return 0; 959 } 960 961 static int cdns_unreg_slave(struct i2c_client *slave) 962 { 963 struct cdns_i2c *id = container_of(slave->adapter, struct cdns_i2c, 964 adap); 965 966 pm_runtime_put(id->dev); 967 968 /* Remove slave information */ 969 id->slave = NULL; 970 971 /* Enable I2C master */ 972 cdns_i2c_set_mode(CDNS_I2C_MODE_MASTER, id); 973 974 return 0; 975 } 976 #endif 977 978 static const struct i2c_algorithm cdns_i2c_algo = { 979 .master_xfer = cdns_i2c_master_xfer, 980 .functionality = cdns_i2c_func, 981 #if IS_ENABLED(CONFIG_I2C_SLAVE) 982 .reg_slave = cdns_reg_slave, 983 .unreg_slave = cdns_unreg_slave, 984 #endif 985 }; 986 987 /** 988 * cdns_i2c_calc_divs - Calculate clock dividers 989 * @f: I2C clock frequency 990 * @input_clk: Input clock frequency 991 * @a: First divider (return value) 992 * @b: Second divider (return value) 993 * 994 * f is used as input and output variable. As input it is used as target I2C 995 * frequency. On function exit f holds the actually resulting I2C frequency. 996 * 997 * Return: 0 on success, negative errno otherwise. 998 */ 999 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 1000 unsigned int *a, unsigned int *b) 1001 { 1002 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 1003 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 1004 unsigned int last_error, current_error; 1005 1006 /* calculate (divisor_a+1) x (divisor_b+1) */ 1007 temp = input_clk / (22 * fscl); 1008 1009 /* 1010 * If the calculated value is negative or 0, the fscl input is out of 1011 * range. Return error. 1012 */ 1013 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 1014 return -EINVAL; 1015 1016 last_error = -1; 1017 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 1018 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 1019 1020 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 1021 continue; 1022 div_b--; 1023 1024 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 1025 1026 if (actual_fscl > fscl) 1027 continue; 1028 1029 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 1030 (fscl - actual_fscl)); 1031 1032 if (last_error > current_error) { 1033 calc_div_a = div_a; 1034 calc_div_b = div_b; 1035 best_fscl = actual_fscl; 1036 last_error = current_error; 1037 } 1038 } 1039 1040 *a = calc_div_a; 1041 *b = calc_div_b; 1042 *f = best_fscl; 1043 1044 return 0; 1045 } 1046 1047 /** 1048 * cdns_i2c_setclk - This function sets the serial clock rate for the I2C device 1049 * @clk_in: I2C clock input frequency in Hz 1050 * @id: Pointer to the I2C device structure 1051 * 1052 * The device must be idle rather than busy transferring data before setting 1053 * these device options. 1054 * The data rate is set by values in the control register. 1055 * The formula for determining the correct register values is 1056 * Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) 1057 * See the hardware data sheet for a full explanation of setting the serial 1058 * clock rate. The clock can not be faster than the input clock divide by 22. 1059 * The two most common clock rates are 100KHz and 400KHz. 1060 * 1061 * Return: 0 on success, negative error otherwise 1062 */ 1063 static int cdns_i2c_setclk(unsigned long clk_in, struct cdns_i2c *id) 1064 { 1065 unsigned int div_a, div_b; 1066 unsigned int ctrl_reg; 1067 int ret = 0; 1068 unsigned long fscl = id->i2c_clk; 1069 1070 ret = cdns_i2c_calc_divs(&fscl, clk_in, &div_a, &div_b); 1071 if (ret) 1072 return ret; 1073 1074 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); 1075 ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK); 1076 ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) | 1077 (div_b << CDNS_I2C_CR_DIVB_SHIFT)); 1078 cdns_i2c_writereg(ctrl_reg, CDNS_I2C_CR_OFFSET); 1079 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1080 id->ctrl_reg_diva_divb = ctrl_reg & (CDNS_I2C_CR_DIVA_MASK | 1081 CDNS_I2C_CR_DIVB_MASK); 1082 #endif 1083 return 0; 1084 } 1085 1086 /** 1087 * cdns_i2c_clk_notifier_cb - Clock rate change callback 1088 * @nb: Pointer to notifier block 1089 * @event: Notification reason 1090 * @data: Pointer to notification data object 1091 * 1092 * This function is called when the cdns_i2c input clock frequency changes. 1093 * The callback checks whether a valid bus frequency can be generated after the 1094 * change. If so, the change is acknowledged, otherwise the change is aborted. 1095 * New dividers are written to the HW in the pre- or post change notification 1096 * depending on the scaling direction. 1097 * 1098 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 1099 * to acknowledge the change, NOTIFY_DONE if the notification is 1100 * considered irrelevant. 1101 */ 1102 static int cdns_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 1103 event, void *data) 1104 { 1105 struct clk_notifier_data *ndata = data; 1106 struct cdns_i2c *id = to_cdns_i2c(nb); 1107 1108 if (pm_runtime_suspended(id->dev)) 1109 return NOTIFY_OK; 1110 1111 switch (event) { 1112 case PRE_RATE_CHANGE: 1113 { 1114 unsigned long input_clk = ndata->new_rate; 1115 unsigned long fscl = id->i2c_clk; 1116 unsigned int div_a, div_b; 1117 int ret; 1118 1119 ret = cdns_i2c_calc_divs(&fscl, input_clk, &div_a, &div_b); 1120 if (ret) { 1121 dev_warn(id->adap.dev.parent, 1122 "clock rate change rejected\n"); 1123 return NOTIFY_STOP; 1124 } 1125 1126 /* scale up */ 1127 if (ndata->new_rate > ndata->old_rate) 1128 cdns_i2c_setclk(ndata->new_rate, id); 1129 1130 return NOTIFY_OK; 1131 } 1132 case POST_RATE_CHANGE: 1133 id->input_clk = ndata->new_rate; 1134 /* scale down */ 1135 if (ndata->new_rate < ndata->old_rate) 1136 cdns_i2c_setclk(ndata->new_rate, id); 1137 return NOTIFY_OK; 1138 case ABORT_RATE_CHANGE: 1139 /* scale up */ 1140 if (ndata->new_rate > ndata->old_rate) 1141 cdns_i2c_setclk(ndata->old_rate, id); 1142 return NOTIFY_OK; 1143 default: 1144 return NOTIFY_DONE; 1145 } 1146 } 1147 1148 /** 1149 * cdns_i2c_runtime_suspend - Runtime suspend method for the driver 1150 * @dev: Address of the platform_device structure 1151 * 1152 * Put the driver into low power mode. 1153 * 1154 * Return: 0 always 1155 */ 1156 static int __maybe_unused cdns_i2c_runtime_suspend(struct device *dev) 1157 { 1158 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1159 1160 clk_disable(xi2c->clk); 1161 1162 return 0; 1163 } 1164 1165 /** 1166 * cdns_i2c_runtime_resume - Runtime resume 1167 * @dev: Address of the platform_device structure 1168 * 1169 * Runtime resume callback. 1170 * 1171 * Return: 0 on success and error value on error 1172 */ 1173 static int __maybe_unused cdns_i2c_runtime_resume(struct device *dev) 1174 { 1175 struct cdns_i2c *xi2c = dev_get_drvdata(dev); 1176 int ret; 1177 1178 ret = clk_enable(xi2c->clk); 1179 if (ret) { 1180 dev_err(dev, "Cannot enable clock.\n"); 1181 return ret; 1182 } 1183 1184 return 0; 1185 } 1186 1187 static const struct dev_pm_ops cdns_i2c_dev_pm_ops = { 1188 SET_RUNTIME_PM_OPS(cdns_i2c_runtime_suspend, 1189 cdns_i2c_runtime_resume, NULL) 1190 }; 1191 1192 static const struct cdns_platform_data r1p10_i2c_def = { 1193 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 1194 }; 1195 1196 static const struct of_device_id cdns_i2c_of_match[] = { 1197 { .compatible = "cdns,i2c-r1p10", .data = &r1p10_i2c_def }, 1198 { .compatible = "cdns,i2c-r1p14",}, 1199 { /* end of table */ } 1200 }; 1201 MODULE_DEVICE_TABLE(of, cdns_i2c_of_match); 1202 1203 /** 1204 * cdns_i2c_probe - Platform registration call 1205 * @pdev: Handle to the platform device structure 1206 * 1207 * This function does all the memory allocation and registration for the i2c 1208 * device. User can modify the address mode to 10 bit address mode using the 1209 * ioctl call with option I2C_TENBIT. 1210 * 1211 * Return: 0 on success, negative error otherwise 1212 */ 1213 static int cdns_i2c_probe(struct platform_device *pdev) 1214 { 1215 struct resource *r_mem; 1216 struct cdns_i2c *id; 1217 int ret; 1218 const struct of_device_id *match; 1219 1220 id = devm_kzalloc(&pdev->dev, sizeof(*id), GFP_KERNEL); 1221 if (!id) 1222 return -ENOMEM; 1223 1224 id->dev = &pdev->dev; 1225 platform_set_drvdata(pdev, id); 1226 1227 match = of_match_node(cdns_i2c_of_match, pdev->dev.of_node); 1228 if (match && match->data) { 1229 const struct cdns_platform_data *data = match->data; 1230 id->quirks = data->quirks; 1231 } 1232 1233 id->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r_mem); 1234 if (IS_ERR(id->membase)) 1235 return PTR_ERR(id->membase); 1236 1237 ret = platform_get_irq(pdev, 0); 1238 if (ret < 0) 1239 return ret; 1240 id->irq = ret; 1241 1242 id->adap.owner = THIS_MODULE; 1243 id->adap.dev.of_node = pdev->dev.of_node; 1244 id->adap.algo = &cdns_i2c_algo; 1245 id->adap.timeout = CDNS_I2C_TIMEOUT; 1246 id->adap.retries = 3; /* Default retry value. */ 1247 id->adap.algo_data = id; 1248 id->adap.dev.parent = &pdev->dev; 1249 init_completion(&id->xfer_done); 1250 snprintf(id->adap.name, sizeof(id->adap.name), 1251 "Cadence I2C at %08lx", (unsigned long)r_mem->start); 1252 1253 id->clk = devm_clk_get(&pdev->dev, NULL); 1254 if (IS_ERR(id->clk)) 1255 return dev_err_probe(&pdev->dev, PTR_ERR(id->clk), 1256 "input clock not found.\n"); 1257 1258 ret = clk_prepare_enable(id->clk); 1259 if (ret) 1260 dev_err(&pdev->dev, "Unable to enable clock.\n"); 1261 1262 pm_runtime_set_autosuspend_delay(id->dev, CNDS_I2C_PM_TIMEOUT); 1263 pm_runtime_use_autosuspend(id->dev); 1264 pm_runtime_set_active(id->dev); 1265 pm_runtime_enable(id->dev); 1266 1267 id->clk_rate_change_nb.notifier_call = cdns_i2c_clk_notifier_cb; 1268 if (clk_notifier_register(id->clk, &id->clk_rate_change_nb)) 1269 dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); 1270 id->input_clk = clk_get_rate(id->clk); 1271 1272 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1273 &id->i2c_clk); 1274 if (ret || (id->i2c_clk > I2C_MAX_FAST_MODE_FREQ)) 1275 id->i2c_clk = I2C_MAX_STANDARD_MODE_FREQ; 1276 1277 #if IS_ENABLED(CONFIG_I2C_SLAVE) 1278 /* Set initial mode to master */ 1279 id->dev_mode = CDNS_I2C_MODE_MASTER; 1280 id->slave_state = CDNS_I2C_SLAVE_STATE_IDLE; 1281 #endif 1282 cdns_i2c_writereg(CDNS_I2C_CR_MASTER_EN_MASK, CDNS_I2C_CR_OFFSET); 1283 1284 ret = cdns_i2c_setclk(id->input_clk, id); 1285 if (ret) { 1286 dev_err(&pdev->dev, "invalid SCL clock: %u Hz\n", id->i2c_clk); 1287 ret = -EINVAL; 1288 goto err_clk_dis; 1289 } 1290 1291 ret = devm_request_irq(&pdev->dev, id->irq, cdns_i2c_isr, 0, 1292 DRIVER_NAME, id); 1293 if (ret) { 1294 dev_err(&pdev->dev, "cannot get irq %d\n", id->irq); 1295 goto err_clk_dis; 1296 } 1297 1298 /* 1299 * Cadence I2C controller has a bug wherein it generates 1300 * invalid read transaction after HW timeout in master receiver mode. 1301 * HW timeout is not used by this driver and the interrupt is disabled. 1302 * But the feature itself cannot be disabled. Hence maximum value 1303 * is written to this register to reduce the chances of error. 1304 */ 1305 cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); 1306 1307 ret = i2c_add_adapter(&id->adap); 1308 if (ret < 0) 1309 goto err_clk_dis; 1310 1311 dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", 1312 id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq); 1313 1314 return 0; 1315 1316 err_clk_dis: 1317 clk_disable_unprepare(id->clk); 1318 pm_runtime_disable(&pdev->dev); 1319 pm_runtime_set_suspended(&pdev->dev); 1320 return ret; 1321 } 1322 1323 /** 1324 * cdns_i2c_remove - Unregister the device after releasing the resources 1325 * @pdev: Handle to the platform device structure 1326 * 1327 * This function frees all the resources allocated to the device. 1328 * 1329 * Return: 0 always 1330 */ 1331 static int cdns_i2c_remove(struct platform_device *pdev) 1332 { 1333 struct cdns_i2c *id = platform_get_drvdata(pdev); 1334 1335 pm_runtime_disable(&pdev->dev); 1336 pm_runtime_set_suspended(&pdev->dev); 1337 pm_runtime_dont_use_autosuspend(&pdev->dev); 1338 1339 i2c_del_adapter(&id->adap); 1340 clk_notifier_unregister(id->clk, &id->clk_rate_change_nb); 1341 clk_disable_unprepare(id->clk); 1342 1343 return 0; 1344 } 1345 1346 static struct platform_driver cdns_i2c_drv = { 1347 .driver = { 1348 .name = DRIVER_NAME, 1349 .of_match_table = cdns_i2c_of_match, 1350 .pm = &cdns_i2c_dev_pm_ops, 1351 }, 1352 .probe = cdns_i2c_probe, 1353 .remove = cdns_i2c_remove, 1354 }; 1355 1356 module_platform_driver(cdns_i2c_drv); 1357 1358 MODULE_AUTHOR("Xilinx Inc."); 1359 MODULE_DESCRIPTION("Cadence I2C bus driver"); 1360 MODULE_LICENSE("GPL"); 1361