1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/i2c.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 26 #define N_DATA_REGS 8 27 28 /* 29 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register 30 * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per 31 * data register whereas STB SoCs use 4 byte per data register transfer, 32 * account for this difference in total count per transaction and mask to 33 * use. 34 */ 35 #define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0)) 36 #define BSC_CNT_REG1_SHIFT 0 37 38 /* BSC CTL register field definitions */ 39 #define BSC_CTL_REG_DTF_MASK 0x00000003 40 #define BSC_CTL_REG_SCL_SEL_MASK 0x00000030 41 #define BSC_CTL_REG_SCL_SEL_SHIFT 4 42 #define BSC_CTL_REG_INT_EN_MASK 0x00000040 43 #define BSC_CTL_REG_INT_EN_SHIFT 6 44 #define BSC_CTL_REG_DIV_CLK_MASK 0x00000080 45 46 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */ 47 #define BSC_IIC_EN_RESTART_MASK 0x00000040 48 #define BSC_IIC_EN_NOSTART_MASK 0x00000020 49 #define BSC_IIC_EN_NOSTOP_MASK 0x00000010 50 #define BSC_IIC_EN_NOACK_MASK 0x00000004 51 #define BSC_IIC_EN_INTRP_MASK 0x00000002 52 #define BSC_IIC_EN_ENABLE_MASK 0x00000001 53 54 /* BSC_CTLHI control register field definitions */ 55 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080 56 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040 57 #define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 58 #define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001 59 60 #define I2C_TIMEOUT 100 /* msecs */ 61 62 /* Condition mask used for non combined transfer */ 63 #define COND_RESTART BSC_IIC_EN_RESTART_MASK 64 #define COND_NOSTART BSC_IIC_EN_NOSTART_MASK 65 #define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK 66 #define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP) 67 68 /* BSC data transfer direction */ 69 #define DTF_WR_MASK 0x00000000 70 #define DTF_RD_MASK 0x00000001 71 /* BSC data transfer direction combined format */ 72 #define DTF_RD_WR_MASK 0x00000002 73 #define DTF_WR_RD_MASK 0x00000003 74 75 #define INT_ENABLE true 76 #define INT_DISABLE false 77 78 /* BSC block register map structure to cache fields to be written */ 79 struct bsc_regs { 80 u32 chip_address; /* slave address */ 81 u32 data_in[N_DATA_REGS]; /* tx data buffer*/ 82 u32 cnt_reg; /* rx/tx data length */ 83 u32 ctl_reg; /* control register */ 84 u32 iic_enable; /* xfer enable and status */ 85 u32 data_out[N_DATA_REGS]; /* rx data buffer */ 86 u32 ctlhi_reg; /* more control fields */ 87 u32 scl_param; /* reserved */ 88 }; 89 90 struct bsc_clk_param { 91 u32 hz; 92 u32 scl_mask; 93 u32 div_mask; 94 }; 95 96 enum bsc_xfer_cmd { 97 CMD_WR, 98 CMD_RD, 99 CMD_WR_NOACK, 100 CMD_RD_NOACK, 101 }; 102 103 static char const *cmd_string[] = { 104 [CMD_WR] = "WR", 105 [CMD_RD] = "RD", 106 [CMD_WR_NOACK] = "WR NOACK", 107 [CMD_RD_NOACK] = "RD NOACK", 108 }; 109 110 enum bus_speeds { 111 SPD_375K, 112 SPD_390K, 113 SPD_187K, 114 SPD_200K, 115 SPD_93K, 116 SPD_97K, 117 SPD_46K, 118 SPD_50K 119 }; 120 121 static const struct bsc_clk_param bsc_clk[] = { 122 [SPD_375K] = { 123 .hz = 375000, 124 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 125 .div_mask = 0 126 }, 127 [SPD_390K] = { 128 .hz = 390000, 129 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 130 .div_mask = 0 131 }, 132 [SPD_187K] = { 133 .hz = 187500, 134 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 135 .div_mask = 0 136 }, 137 [SPD_200K] = { 138 .hz = 200000, 139 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 140 .div_mask = 0 141 }, 142 [SPD_93K] = { 143 .hz = 93750, 144 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 145 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 146 }, 147 [SPD_97K] = { 148 .hz = 97500, 149 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 150 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 151 }, 152 [SPD_46K] = { 153 .hz = 46875, 154 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 155 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 156 }, 157 [SPD_50K] = { 158 .hz = 50000, 159 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 160 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 161 } 162 }; 163 164 struct brcmstb_i2c_dev { 165 struct device *device; 166 void __iomem *base; 167 int irq; 168 struct bsc_regs *bsc_regmap; 169 struct i2c_adapter adapter; 170 struct completion done; 171 u32 clk_freq_hz; 172 int data_regsz; 173 }; 174 175 /* register accessors for both be and le cpu arch */ 176 #ifdef CONFIG_CPU_BIG_ENDIAN 177 #define __bsc_readl(_reg) ioread32be(_reg) 178 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) 179 #else 180 #define __bsc_readl(_reg) ioread32(_reg) 181 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) 182 #endif 183 184 #define bsc_readl(_dev, _reg) \ 185 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) 186 187 #define bsc_writel(_dev, _val, _reg) \ 188 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) 189 190 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev) 191 { 192 return (N_DATA_REGS * dev->data_regsz); 193 } 194 195 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev) 196 { 197 return dev->data_regsz; 198 } 199 200 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev, 201 bool int_en) 202 { 203 204 if (int_en) 205 /* Enable BSC CTL interrupt line */ 206 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK; 207 else 208 /* Disable BSC CTL interrupt line */ 209 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK; 210 211 barrier(); 212 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 213 } 214 215 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid) 216 { 217 struct brcmstb_i2c_dev *dev = devid; 218 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg); 219 u32 status_iic_intrp = bsc_readl(dev, iic_enable); 220 221 dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n", 222 status_bsc_ctl, status_iic_intrp); 223 224 if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK)) 225 return IRQ_NONE; 226 227 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 228 complete(&dev->done); 229 230 dev_dbg(dev->device, "isr handled"); 231 return IRQ_HANDLED; 232 } 233 234 /* Wait for device to be ready */ 235 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev) 236 { 237 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); 238 239 while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) { 240 if (time_after(jiffies, timeout)) 241 return -ETIMEDOUT; 242 cpu_relax(); 243 } 244 return 0; 245 } 246 247 /* i2c xfer completion function, handles both irq and polling mode */ 248 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev) 249 { 250 int ret = 0; 251 unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT); 252 253 if (dev->irq >= 0) { 254 if (!wait_for_completion_timeout(&dev->done, timeout)) 255 ret = -ETIMEDOUT; 256 } else { 257 /* we are in polling mode */ 258 u32 bsc_intrp; 259 unsigned long time_left = jiffies + timeout; 260 261 do { 262 bsc_intrp = bsc_readl(dev, iic_enable) & 263 BSC_IIC_EN_INTRP_MASK; 264 if (time_after(jiffies, time_left)) { 265 ret = -ETIMEDOUT; 266 break; 267 } 268 cpu_relax(); 269 } while (!bsc_intrp); 270 } 271 272 if (dev->irq < 0 || ret == -ETIMEDOUT) 273 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 274 275 return ret; 276 } 277 278 /* Set xfer START/STOP conditions for subsequent transfer */ 279 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev, 280 u32 cond_flag) 281 { 282 u32 regval = dev->bsc_regmap->iic_enable; 283 284 dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag; 285 } 286 287 /* Send I2C request check completion */ 288 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev, 289 enum bsc_xfer_cmd cmd) 290 { 291 int rc = 0; 292 struct bsc_regs *pi2creg = dev->bsc_regmap; 293 294 /* Make sure the hardware is ready */ 295 rc = brcmstb_i2c_wait_if_busy(dev); 296 if (rc < 0) 297 return rc; 298 299 /* only if we are in interrupt mode */ 300 if (dev->irq >= 0) 301 reinit_completion(&dev->done); 302 303 /* enable BSC CTL interrupt line */ 304 brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE); 305 306 /* initiate transfer by setting iic_enable */ 307 pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK; 308 bsc_writel(dev, pi2creg->iic_enable, iic_enable); 309 310 /* Wait for transaction to finish or timeout */ 311 rc = brcmstb_i2c_wait_for_completion(dev); 312 if (rc) { 313 dev_dbg(dev->device, "intr timeout for cmd %s\n", 314 cmd_string[cmd]); 315 goto cmd_out; 316 } 317 318 if ((cmd == CMD_RD || cmd == CMD_WR) && 319 bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) { 320 rc = -EREMOTEIO; 321 dev_dbg(dev->device, "controller received NOACK intr for %s\n", 322 cmd_string[cmd]); 323 } 324 325 cmd_out: 326 bsc_writel(dev, 0, cnt_reg); 327 bsc_writel(dev, 0, iic_enable); 328 329 return rc; 330 } 331 332 /* Actual data transfer through the BSC master */ 333 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, 334 u8 *buf, unsigned int len, 335 struct i2c_msg *pmsg) 336 { 337 int cnt, byte, i, rc; 338 enum bsc_xfer_cmd cmd; 339 u32 ctl_reg; 340 struct bsc_regs *pi2creg = dev->bsc_regmap; 341 int no_ack = pmsg->flags & I2C_M_IGNORE_NAK; 342 int data_regsz = brcmstb_i2c_get_data_regsz(dev); 343 344 /* see if the transaction needs to check NACK conditions */ 345 if (no_ack) { 346 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK 347 : CMD_WR_NOACK; 348 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK; 349 } else { 350 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR; 351 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK; 352 } 353 bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg); 354 355 /* set data transfer direction */ 356 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK; 357 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) 358 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK; 359 else 360 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK; 361 362 /* set the read/write length */ 363 bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) & 364 (len << BSC_CNT_REG1_SHIFT), cnt_reg); 365 366 /* Write data into data_in register */ 367 368 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) { 369 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 370 u32 word = 0; 371 372 for (byte = 0; byte < data_regsz; byte++) { 373 word >>= BITS_PER_BYTE; 374 if ((cnt + byte) < len) 375 word |= buf[cnt + byte] << 376 (BITS_PER_BYTE * (data_regsz - 1)); 377 } 378 bsc_writel(dev, word, data_in[i]); 379 } 380 } 381 382 /* Initiate xfer, the function will return on completion */ 383 rc = brcmstb_send_i2c_cmd(dev, cmd); 384 385 if (rc != 0) { 386 dev_dbg(dev->device, "%s failure", cmd_string[cmd]); 387 return rc; 388 } 389 390 /* Read data from data_out register */ 391 if (cmd == CMD_RD || cmd == CMD_RD_NOACK) { 392 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 393 u32 data = bsc_readl(dev, data_out[i]); 394 395 for (byte = 0; byte < data_regsz && 396 (byte + cnt) < len; byte++) { 397 buf[cnt + byte] = data & 0xff; 398 data >>= BITS_PER_BYTE; 399 } 400 } 401 } 402 403 return 0; 404 } 405 406 /* Write a single byte of data to the i2c bus */ 407 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev, 408 u8 *buf, unsigned int nak_expected) 409 { 410 enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK; 411 412 bsc_writel(dev, 1, cnt_reg); 413 bsc_writel(dev, *buf, data_in); 414 415 return brcmstb_send_i2c_cmd(dev, cmd); 416 } 417 418 /* Send i2c address */ 419 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev, 420 struct i2c_msg *msg) 421 { 422 unsigned char addr; 423 424 if (msg->flags & I2C_M_TEN) { 425 /* First byte is 11110XX0 where XX is upper 2 bits */ 426 addr = 0xF0 | ((msg->addr & 0x300) >> 7); 427 bsc_writel(dev, addr, chip_address); 428 429 /* Second byte is the remaining 8 bits */ 430 addr = msg->addr & 0xFF; 431 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 432 return -EREMOTEIO; 433 434 if (msg->flags & I2C_M_RD) { 435 /* For read, send restart without stop condition */ 436 brcmstb_set_i2c_start_stop(dev, COND_RESTART 437 | COND_NOSTOP); 438 /* Then re-send the first byte with the read bit set */ 439 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; 440 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 441 return -EREMOTEIO; 442 443 } 444 } else { 445 addr = i2c_8bit_addr_from_msg(msg); 446 447 bsc_writel(dev, addr, chip_address); 448 } 449 450 return 0; 451 } 452 453 /* Master transfer function */ 454 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter, 455 struct i2c_msg msgs[], int num) 456 { 457 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter); 458 struct i2c_msg *pmsg; 459 int rc = 0; 460 int i; 461 int bytes_to_xfer; 462 u8 *tmp_buf; 463 int len = 0; 464 int xfersz = brcmstb_i2c_get_xfersz(dev); 465 u32 cond, cond_per_msg; 466 467 /* Loop through all messages */ 468 for (i = 0; i < num; i++) { 469 pmsg = &msgs[i]; 470 len = pmsg->len; 471 tmp_buf = pmsg->buf; 472 473 dev_dbg(dev->device, 474 "msg# %d/%d flg %x buf %x len %d\n", i, 475 num - 1, pmsg->flags, 476 pmsg->buf ? pmsg->buf[0] : '0', pmsg->len); 477 478 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART)) 479 cond = ~COND_START_STOP; 480 else 481 cond = COND_RESTART | COND_NOSTOP; 482 483 brcmstb_set_i2c_start_stop(dev, cond); 484 485 /* Send slave address */ 486 if (!(pmsg->flags & I2C_M_NOSTART)) { 487 rc = brcmstb_i2c_do_addr(dev, pmsg); 488 if (rc < 0) { 489 dev_dbg(dev->device, 490 "NACK for addr %2.2x msg#%d rc = %d\n", 491 pmsg->addr, i, rc); 492 goto out; 493 } 494 } 495 496 cond_per_msg = cond; 497 498 /* Perform data transfer */ 499 while (len) { 500 bytes_to_xfer = min(len, xfersz); 501 502 if (len <= xfersz) { 503 if (i == (num - 1)) 504 cond_per_msg = cond_per_msg & 505 ~(COND_RESTART | COND_NOSTOP); 506 else 507 cond_per_msg = cond; 508 } else { 509 cond_per_msg = (cond_per_msg & ~COND_RESTART) | 510 COND_NOSTOP; 511 } 512 513 brcmstb_set_i2c_start_stop(dev, cond_per_msg); 514 515 rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf, 516 bytes_to_xfer, pmsg); 517 if (rc < 0) 518 goto out; 519 520 len -= bytes_to_xfer; 521 tmp_buf += bytes_to_xfer; 522 523 cond_per_msg = COND_NOSTART | COND_NOSTOP; 524 } 525 } 526 527 rc = num; 528 out: 529 return rc; 530 531 } 532 533 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap) 534 { 535 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR 536 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING; 537 } 538 539 static const struct i2c_algorithm brcmstb_i2c_algo = { 540 .master_xfer = brcmstb_i2c_xfer, 541 .functionality = brcmstb_i2c_functionality, 542 }; 543 544 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev) 545 { 546 int i = 0, num_speeds = ARRAY_SIZE(bsc_clk); 547 u32 clk_freq_hz = dev->clk_freq_hz; 548 549 for (i = 0; i < num_speeds; i++) { 550 if (bsc_clk[i].hz == clk_freq_hz) { 551 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK 552 | BSC_CTL_REG_DIV_CLK_MASK); 553 dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask | 554 bsc_clk[i].div_mask); 555 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 556 break; 557 } 558 } 559 560 /* in case we did not get find a valid speed */ 561 if (i == num_speeds) { 562 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >> 563 BSC_CTL_REG_SCL_SEL_SHIFT; 564 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n", 565 bsc_clk[i].hz); 566 } 567 } 568 569 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev) 570 { 571 if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32)) 572 /* set 4 byte data in/out xfers */ 573 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK; 574 else 575 dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK; 576 577 bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg); 578 /* set bus speed */ 579 brcmstb_i2c_set_bus_speed(dev); 580 } 581 582 #define AUTOI2C_CTRL0 0x26c 583 #define AUTOI2C_CTRL0_RELEASE_BSC BIT(1) 584 585 static int bcm2711_release_bsc(struct brcmstb_i2c_dev *dev) 586 { 587 struct platform_device *pdev = to_platform_device(dev->device); 588 struct resource *iomem; 589 void __iomem *autoi2c; 590 591 /* Map hardware registers */ 592 iomem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "auto-i2c"); 593 autoi2c = devm_ioremap_resource(&pdev->dev, iomem); 594 if (IS_ERR(autoi2c)) 595 return PTR_ERR(autoi2c); 596 597 writel(AUTOI2C_CTRL0_RELEASE_BSC, autoi2c + AUTOI2C_CTRL0); 598 devm_iounmap(&pdev->dev, autoi2c); 599 600 /* We need to reset the controller after the release */ 601 dev->bsc_regmap->iic_enable = 0; 602 bsc_writel(dev, dev->bsc_regmap->iic_enable, iic_enable); 603 604 return 0; 605 } 606 607 static int brcmstb_i2c_probe(struct platform_device *pdev) 608 { 609 int rc = 0; 610 struct brcmstb_i2c_dev *dev; 611 struct i2c_adapter *adap; 612 struct resource *iomem; 613 const char *int_name; 614 615 /* Allocate memory for private data structure */ 616 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 617 if (!dev) 618 return -ENOMEM; 619 620 dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL); 621 if (!dev->bsc_regmap) 622 return -ENOMEM; 623 624 platform_set_drvdata(pdev, dev); 625 dev->device = &pdev->dev; 626 init_completion(&dev->done); 627 628 /* Map hardware registers */ 629 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 630 dev->base = devm_ioremap_resource(dev->device, iomem); 631 if (IS_ERR(dev->base)) { 632 rc = -ENOMEM; 633 goto probe_errorout; 634 } 635 636 if (of_device_is_compatible(dev->device->of_node, 637 "brcm,bcm2711-hdmi-i2c")) { 638 rc = bcm2711_release_bsc(dev); 639 if (rc) 640 goto probe_errorout; 641 } 642 643 rc = of_property_read_string(dev->device->of_node, "interrupt-names", 644 &int_name); 645 if (rc < 0) 646 int_name = NULL; 647 648 /* Get the interrupt number */ 649 dev->irq = platform_get_irq_optional(pdev, 0); 650 651 /* disable the bsc interrupt line */ 652 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 653 654 /* register the ISR handler */ 655 if (dev->irq >= 0) { 656 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr, 657 IRQF_SHARED, 658 int_name ? int_name : pdev->name, 659 dev); 660 661 if (rc) { 662 dev_dbg(dev->device, "falling back to polling mode"); 663 dev->irq = -1; 664 } 665 } 666 667 if (of_property_read_u32(dev->device->of_node, 668 "clock-frequency", &dev->clk_freq_hz)) { 669 dev_warn(dev->device, "setting clock-frequency@%dHz\n", 670 bsc_clk[0].hz); 671 dev->clk_freq_hz = bsc_clk[0].hz; 672 } 673 674 /* set the data in/out register size for compatible SoCs */ 675 if (of_device_is_compatible(dev->device->of_node, 676 "brcm,brcmper-i2c")) 677 dev->data_regsz = sizeof(u8); 678 else 679 dev->data_regsz = sizeof(u32); 680 681 brcmstb_i2c_set_bsc_reg_defaults(dev); 682 683 /* Add the i2c adapter */ 684 adap = &dev->adapter; 685 i2c_set_adapdata(adap, dev); 686 adap->owner = THIS_MODULE; 687 strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name)); 688 if (int_name) 689 strlcat(adap->name, int_name, sizeof(adap->name)); 690 adap->algo = &brcmstb_i2c_algo; 691 adap->dev.parent = &pdev->dev; 692 adap->dev.of_node = pdev->dev.of_node; 693 rc = i2c_add_adapter(adap); 694 if (rc) 695 goto probe_errorout; 696 697 dev_info(dev->device, "%s@%dhz registered in %s mode\n", 698 int_name ? int_name : " ", dev->clk_freq_hz, 699 (dev->irq >= 0) ? "interrupt" : "polling"); 700 701 return 0; 702 703 probe_errorout: 704 return rc; 705 } 706 707 static int brcmstb_i2c_remove(struct platform_device *pdev) 708 { 709 struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev); 710 711 i2c_del_adapter(&dev->adapter); 712 return 0; 713 } 714 715 #ifdef CONFIG_PM_SLEEP 716 static int brcmstb_i2c_suspend(struct device *dev) 717 { 718 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 719 720 i2c_mark_adapter_suspended(&i2c_dev->adapter); 721 return 0; 722 } 723 724 static int brcmstb_i2c_resume(struct device *dev) 725 { 726 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 727 728 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev); 729 i2c_mark_adapter_resumed(&i2c_dev->adapter); 730 731 return 0; 732 } 733 #endif 734 735 static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend, 736 brcmstb_i2c_resume); 737 738 static const struct of_device_id brcmstb_i2c_of_match[] = { 739 {.compatible = "brcm,brcmstb-i2c"}, 740 {.compatible = "brcm,brcmper-i2c"}, 741 {.compatible = "brcm,bcm2711-hdmi-i2c"}, 742 {}, 743 }; 744 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match); 745 746 static struct platform_driver brcmstb_i2c_driver = { 747 .driver = { 748 .name = "brcmstb-i2c", 749 .of_match_table = brcmstb_i2c_of_match, 750 .pm = &brcmstb_i2c_pm, 751 }, 752 .probe = brcmstb_i2c_probe, 753 .remove = brcmstb_i2c_remove, 754 }; 755 module_platform_driver(brcmstb_i2c_driver); 756 757 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>"); 758 MODULE_DESCRIPTION("Broadcom Settop I2C Driver"); 759 MODULE_LICENSE("GPL v2"); 760