1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/i2c.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 #include <linux/version.h> 26 27 #define N_DATA_REGS 8 28 29 /* 30 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register 31 * size. Cable modem and DSL SoCs with Peripheral i2c cores use 1 byte per 32 * data register whereas STB SoCs use 4 byte per data register transfer, 33 * account for this difference in total count per transaction and mask to 34 * use. 35 */ 36 #define BSC_CNT_REG1_MASK(nb) (nb == 1 ? GENMASK(3, 0) : GENMASK(5, 0)) 37 #define BSC_CNT_REG1_SHIFT 0 38 39 /* BSC CTL register field definitions */ 40 #define BSC_CTL_REG_DTF_MASK 0x00000003 41 #define BSC_CTL_REG_SCL_SEL_MASK 0x00000030 42 #define BSC_CTL_REG_SCL_SEL_SHIFT 4 43 #define BSC_CTL_REG_INT_EN_MASK 0x00000040 44 #define BSC_CTL_REG_INT_EN_SHIFT 6 45 #define BSC_CTL_REG_DIV_CLK_MASK 0x00000080 46 47 /* BSC_IIC_ENABLE r/w enable and interrupt field definitions */ 48 #define BSC_IIC_EN_RESTART_MASK 0x00000040 49 #define BSC_IIC_EN_NOSTART_MASK 0x00000020 50 #define BSC_IIC_EN_NOSTOP_MASK 0x00000010 51 #define BSC_IIC_EN_NOACK_MASK 0x00000004 52 #define BSC_IIC_EN_INTRP_MASK 0x00000002 53 #define BSC_IIC_EN_ENABLE_MASK 0x00000001 54 55 /* BSC_CTLHI control register field definitions */ 56 #define BSC_CTLHI_REG_INPUT_SWITCHING_LEVEL_MASK 0x00000080 57 #define BSC_CTLHI_REG_DATAREG_SIZE_MASK 0x00000040 58 #define BSC_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 59 #define BSC_CTLHI_REG_WAIT_DIS_MASK 0x00000001 60 61 #define I2C_TIMEOUT 100 /* msecs */ 62 63 /* Condition mask used for non combined transfer */ 64 #define COND_RESTART BSC_IIC_EN_RESTART_MASK 65 #define COND_NOSTART BSC_IIC_EN_NOSTART_MASK 66 #define COND_NOSTOP BSC_IIC_EN_NOSTOP_MASK 67 #define COND_START_STOP (COND_RESTART | COND_NOSTART | COND_NOSTOP) 68 69 /* BSC data transfer direction */ 70 #define DTF_WR_MASK 0x00000000 71 #define DTF_RD_MASK 0x00000001 72 /* BSC data transfer direction combined format */ 73 #define DTF_RD_WR_MASK 0x00000002 74 #define DTF_WR_RD_MASK 0x00000003 75 76 #define INT_ENABLE true 77 #define INT_DISABLE false 78 79 /* BSC block register map structure to cache fields to be written */ 80 struct bsc_regs { 81 u32 chip_address; /* slave address */ 82 u32 data_in[N_DATA_REGS]; /* tx data buffer*/ 83 u32 cnt_reg; /* rx/tx data length */ 84 u32 ctl_reg; /* control register */ 85 u32 iic_enable; /* xfer enable and status */ 86 u32 data_out[N_DATA_REGS]; /* rx data buffer */ 87 u32 ctlhi_reg; /* more control fields */ 88 u32 scl_param; /* reserved */ 89 }; 90 91 struct bsc_clk_param { 92 u32 hz; 93 u32 scl_mask; 94 u32 div_mask; 95 }; 96 97 enum bsc_xfer_cmd { 98 CMD_WR, 99 CMD_RD, 100 CMD_WR_NOACK, 101 CMD_RD_NOACK, 102 }; 103 104 static char const *cmd_string[] = { 105 [CMD_WR] = "WR", 106 [CMD_RD] = "RD", 107 [CMD_WR_NOACK] = "WR NOACK", 108 [CMD_RD_NOACK] = "RD NOACK", 109 }; 110 111 enum bus_speeds { 112 SPD_375K, 113 SPD_390K, 114 SPD_187K, 115 SPD_200K, 116 SPD_93K, 117 SPD_97K, 118 SPD_46K, 119 SPD_50K 120 }; 121 122 static const struct bsc_clk_param bsc_clk[] = { 123 [SPD_375K] = { 124 .hz = 375000, 125 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 126 .div_mask = 0 127 }, 128 [SPD_390K] = { 129 .hz = 390000, 130 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 131 .div_mask = 0 132 }, 133 [SPD_187K] = { 134 .hz = 187500, 135 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 136 .div_mask = 0 137 }, 138 [SPD_200K] = { 139 .hz = 200000, 140 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 141 .div_mask = 0 142 }, 143 [SPD_93K] = { 144 .hz = 93750, 145 .scl_mask = SPD_375K << BSC_CTL_REG_SCL_SEL_SHIFT, 146 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 147 }, 148 [SPD_97K] = { 149 .hz = 97500, 150 .scl_mask = SPD_390K << BSC_CTL_REG_SCL_SEL_SHIFT, 151 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 152 }, 153 [SPD_46K] = { 154 .hz = 46875, 155 .scl_mask = SPD_187K << BSC_CTL_REG_SCL_SEL_SHIFT, 156 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 157 }, 158 [SPD_50K] = { 159 .hz = 50000, 160 .scl_mask = SPD_200K << BSC_CTL_REG_SCL_SEL_SHIFT, 161 .div_mask = BSC_CTL_REG_DIV_CLK_MASK 162 } 163 }; 164 165 struct brcmstb_i2c_dev { 166 struct device *device; 167 void __iomem *base; 168 void __iomem *irq_base; 169 int irq; 170 struct bsc_regs *bsc_regmap; 171 struct i2c_adapter adapter; 172 struct completion done; 173 u32 clk_freq_hz; 174 int data_regsz; 175 }; 176 177 /* register accessors for both be and le cpu arch */ 178 #ifdef CONFIG_CPU_BIG_ENDIAN 179 #define __bsc_readl(_reg) ioread32be(_reg) 180 #define __bsc_writel(_val, _reg) iowrite32be(_val, _reg) 181 #else 182 #define __bsc_readl(_reg) ioread32(_reg) 183 #define __bsc_writel(_val, _reg) iowrite32(_val, _reg) 184 #endif 185 186 #define bsc_readl(_dev, _reg) \ 187 __bsc_readl(_dev->base + offsetof(struct bsc_regs, _reg)) 188 189 #define bsc_writel(_dev, _val, _reg) \ 190 __bsc_writel(_val, _dev->base + offsetof(struct bsc_regs, _reg)) 191 192 static inline int brcmstb_i2c_get_xfersz(struct brcmstb_i2c_dev *dev) 193 { 194 return (N_DATA_REGS * dev->data_regsz); 195 } 196 197 static inline int brcmstb_i2c_get_data_regsz(struct brcmstb_i2c_dev *dev) 198 { 199 return dev->data_regsz; 200 } 201 202 static void brcmstb_i2c_enable_disable_irq(struct brcmstb_i2c_dev *dev, 203 bool int_en) 204 { 205 206 if (int_en) 207 /* Enable BSC CTL interrupt line */ 208 dev->bsc_regmap->ctl_reg |= BSC_CTL_REG_INT_EN_MASK; 209 else 210 /* Disable BSC CTL interrupt line */ 211 dev->bsc_regmap->ctl_reg &= ~BSC_CTL_REG_INT_EN_MASK; 212 213 barrier(); 214 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 215 } 216 217 static irqreturn_t brcmstb_i2c_isr(int irq, void *devid) 218 { 219 struct brcmstb_i2c_dev *dev = devid; 220 u32 status_bsc_ctl = bsc_readl(dev, ctl_reg); 221 u32 status_iic_intrp = bsc_readl(dev, iic_enable); 222 223 dev_dbg(dev->device, "isr CTL_REG %x IIC_EN %x\n", 224 status_bsc_ctl, status_iic_intrp); 225 226 if (!(status_bsc_ctl & BSC_CTL_REG_INT_EN_MASK)) 227 return IRQ_NONE; 228 229 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 230 complete(&dev->done); 231 232 dev_dbg(dev->device, "isr handled"); 233 return IRQ_HANDLED; 234 } 235 236 /* Wait for device to be ready */ 237 static int brcmstb_i2c_wait_if_busy(struct brcmstb_i2c_dev *dev) 238 { 239 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); 240 241 while ((bsc_readl(dev, iic_enable) & BSC_IIC_EN_INTRP_MASK)) { 242 if (time_after(jiffies, timeout)) 243 return -ETIMEDOUT; 244 cpu_relax(); 245 } 246 return 0; 247 } 248 249 /* i2c xfer completion function, handles both irq and polling mode */ 250 static int brcmstb_i2c_wait_for_completion(struct brcmstb_i2c_dev *dev) 251 { 252 int ret = 0; 253 unsigned long timeout = msecs_to_jiffies(I2C_TIMEOUT); 254 255 if (dev->irq >= 0) { 256 if (!wait_for_completion_timeout(&dev->done, timeout)) 257 ret = -ETIMEDOUT; 258 } else { 259 /* we are in polling mode */ 260 u32 bsc_intrp; 261 unsigned long time_left = jiffies + timeout; 262 263 do { 264 bsc_intrp = bsc_readl(dev, iic_enable) & 265 BSC_IIC_EN_INTRP_MASK; 266 if (time_after(jiffies, time_left)) { 267 ret = -ETIMEDOUT; 268 break; 269 } 270 cpu_relax(); 271 } while (!bsc_intrp); 272 } 273 274 if (dev->irq < 0 || ret == -ETIMEDOUT) 275 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 276 277 return ret; 278 } 279 280 /* Set xfer START/STOP conditions for subsequent transfer */ 281 static void brcmstb_set_i2c_start_stop(struct brcmstb_i2c_dev *dev, 282 u32 cond_flag) 283 { 284 u32 regval = dev->bsc_regmap->iic_enable; 285 286 dev->bsc_regmap->iic_enable = (regval & ~COND_START_STOP) | cond_flag; 287 } 288 289 /* Send I2C request check completion */ 290 static int brcmstb_send_i2c_cmd(struct brcmstb_i2c_dev *dev, 291 enum bsc_xfer_cmd cmd) 292 { 293 int rc = 0; 294 struct bsc_regs *pi2creg = dev->bsc_regmap; 295 296 /* Make sure the hardware is ready */ 297 rc = brcmstb_i2c_wait_if_busy(dev); 298 if (rc < 0) 299 return rc; 300 301 /* only if we are in interrupt mode */ 302 if (dev->irq >= 0) 303 reinit_completion(&dev->done); 304 305 /* enable BSC CTL interrupt line */ 306 brcmstb_i2c_enable_disable_irq(dev, INT_ENABLE); 307 308 /* initiate transfer by setting iic_enable */ 309 pi2creg->iic_enable |= BSC_IIC_EN_ENABLE_MASK; 310 bsc_writel(dev, pi2creg->iic_enable, iic_enable); 311 312 /* Wait for transaction to finish or timeout */ 313 rc = brcmstb_i2c_wait_for_completion(dev); 314 if (rc) { 315 dev_dbg(dev->device, "intr timeout for cmd %s\n", 316 cmd_string[cmd]); 317 goto cmd_out; 318 } 319 320 if ((CMD_RD || CMD_WR) && 321 bsc_readl(dev, iic_enable) & BSC_IIC_EN_NOACK_MASK) { 322 rc = -EREMOTEIO; 323 dev_dbg(dev->device, "controller received NOACK intr for %s\n", 324 cmd_string[cmd]); 325 } 326 327 cmd_out: 328 bsc_writel(dev, 0, cnt_reg); 329 bsc_writel(dev, 0, iic_enable); 330 331 return rc; 332 } 333 334 /* Actual data transfer through the BSC master */ 335 static int brcmstb_i2c_xfer_bsc_data(struct brcmstb_i2c_dev *dev, 336 u8 *buf, unsigned int len, 337 struct i2c_msg *pmsg) 338 { 339 int cnt, byte, i, rc; 340 enum bsc_xfer_cmd cmd; 341 u32 ctl_reg; 342 struct bsc_regs *pi2creg = dev->bsc_regmap; 343 int no_ack = pmsg->flags & I2C_M_IGNORE_NAK; 344 int data_regsz = brcmstb_i2c_get_data_regsz(dev); 345 346 /* see if the transaction needs to check NACK conditions */ 347 if (no_ack) { 348 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD_NOACK 349 : CMD_WR_NOACK; 350 pi2creg->ctlhi_reg |= BSC_CTLHI_REG_IGNORE_ACK_MASK; 351 } else { 352 cmd = (pmsg->flags & I2C_M_RD) ? CMD_RD : CMD_WR; 353 pi2creg->ctlhi_reg &= ~BSC_CTLHI_REG_IGNORE_ACK_MASK; 354 } 355 bsc_writel(dev, pi2creg->ctlhi_reg, ctlhi_reg); 356 357 /* set data transfer direction */ 358 ctl_reg = pi2creg->ctl_reg & ~BSC_CTL_REG_DTF_MASK; 359 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) 360 pi2creg->ctl_reg = ctl_reg | DTF_WR_MASK; 361 else 362 pi2creg->ctl_reg = ctl_reg | DTF_RD_MASK; 363 364 /* set the read/write length */ 365 bsc_writel(dev, BSC_CNT_REG1_MASK(data_regsz) & 366 (len << BSC_CNT_REG1_SHIFT), cnt_reg); 367 368 /* Write data into data_in register */ 369 370 if (cmd == CMD_WR || cmd == CMD_WR_NOACK) { 371 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 372 u32 word = 0; 373 374 for (byte = 0; byte < data_regsz; byte++) { 375 word >>= BITS_PER_BYTE; 376 if ((cnt + byte) < len) 377 word |= buf[cnt + byte] << 378 (BITS_PER_BYTE * (data_regsz - 1)); 379 } 380 bsc_writel(dev, word, data_in[i]); 381 } 382 } 383 384 /* Initiate xfer, the function will return on completion */ 385 rc = brcmstb_send_i2c_cmd(dev, cmd); 386 387 if (rc != 0) { 388 dev_dbg(dev->device, "%s failure", cmd_string[cmd]); 389 return rc; 390 } 391 392 /* Read data from data_out register */ 393 if (cmd == CMD_RD || cmd == CMD_RD_NOACK) { 394 for (cnt = 0, i = 0; cnt < len; cnt += data_regsz, i++) { 395 u32 data = bsc_readl(dev, data_out[i]); 396 397 for (byte = 0; byte < data_regsz && 398 (byte + cnt) < len; byte++) { 399 buf[cnt + byte] = data & 0xff; 400 data >>= BITS_PER_BYTE; 401 } 402 } 403 } 404 405 return 0; 406 } 407 408 /* Write a single byte of data to the i2c bus */ 409 static int brcmstb_i2c_write_data_byte(struct brcmstb_i2c_dev *dev, 410 u8 *buf, unsigned int nak_expected) 411 { 412 enum bsc_xfer_cmd cmd = nak_expected ? CMD_WR : CMD_WR_NOACK; 413 414 bsc_writel(dev, 1, cnt_reg); 415 bsc_writel(dev, *buf, data_in); 416 417 return brcmstb_send_i2c_cmd(dev, cmd); 418 } 419 420 /* Send i2c address */ 421 static int brcmstb_i2c_do_addr(struct brcmstb_i2c_dev *dev, 422 struct i2c_msg *msg) 423 { 424 unsigned char addr; 425 426 if (msg->flags & I2C_M_TEN) { 427 /* First byte is 11110XX0 where XX is upper 2 bits */ 428 addr = 0xF0 | ((msg->addr & 0x300) >> 7); 429 bsc_writel(dev, addr, chip_address); 430 431 /* Second byte is the remaining 8 bits */ 432 addr = msg->addr & 0xFF; 433 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 434 return -EREMOTEIO; 435 436 if (msg->flags & I2C_M_RD) { 437 /* For read, send restart without stop condition */ 438 brcmstb_set_i2c_start_stop(dev, COND_RESTART 439 | COND_NOSTOP); 440 /* Then re-send the first byte with the read bit set */ 441 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; 442 if (brcmstb_i2c_write_data_byte(dev, &addr, 0) < 0) 443 return -EREMOTEIO; 444 445 } 446 } else { 447 addr = i2c_8bit_addr_from_msg(msg); 448 449 bsc_writel(dev, addr, chip_address); 450 } 451 452 return 0; 453 } 454 455 /* Master transfer function */ 456 static int brcmstb_i2c_xfer(struct i2c_adapter *adapter, 457 struct i2c_msg msgs[], int num) 458 { 459 struct brcmstb_i2c_dev *dev = i2c_get_adapdata(adapter); 460 struct i2c_msg *pmsg; 461 int rc = 0; 462 int i; 463 int bytes_to_xfer; 464 u8 *tmp_buf; 465 int len = 0; 466 int xfersz = brcmstb_i2c_get_xfersz(dev); 467 u32 cond, cond_per_msg; 468 469 /* Loop through all messages */ 470 for (i = 0; i < num; i++) { 471 pmsg = &msgs[i]; 472 len = pmsg->len; 473 tmp_buf = pmsg->buf; 474 475 dev_dbg(dev->device, 476 "msg# %d/%d flg %x buf %x len %d\n", i, 477 num - 1, pmsg->flags, 478 pmsg->buf ? pmsg->buf[0] : '0', pmsg->len); 479 480 if (i < (num - 1) && (msgs[i + 1].flags & I2C_M_NOSTART)) 481 cond = ~COND_START_STOP; 482 else 483 cond = COND_RESTART | COND_NOSTOP; 484 485 brcmstb_set_i2c_start_stop(dev, cond); 486 487 /* Send slave address */ 488 if (!(pmsg->flags & I2C_M_NOSTART)) { 489 rc = brcmstb_i2c_do_addr(dev, pmsg); 490 if (rc < 0) { 491 dev_dbg(dev->device, 492 "NACK for addr %2.2x msg#%d rc = %d\n", 493 pmsg->addr, i, rc); 494 goto out; 495 } 496 } 497 498 cond_per_msg = cond; 499 500 /* Perform data transfer */ 501 while (len) { 502 bytes_to_xfer = min(len, xfersz); 503 504 if (len <= xfersz) { 505 if (i == (num - 1)) 506 cond_per_msg = cond_per_msg & 507 ~(COND_RESTART | COND_NOSTOP); 508 else 509 cond_per_msg = cond; 510 } else { 511 cond_per_msg = (cond_per_msg & ~COND_RESTART) | 512 COND_NOSTOP; 513 } 514 515 brcmstb_set_i2c_start_stop(dev, cond_per_msg); 516 517 rc = brcmstb_i2c_xfer_bsc_data(dev, tmp_buf, 518 bytes_to_xfer, pmsg); 519 if (rc < 0) 520 goto out; 521 522 len -= bytes_to_xfer; 523 tmp_buf += bytes_to_xfer; 524 525 cond_per_msg = COND_NOSTART | COND_NOSTOP; 526 } 527 } 528 529 rc = num; 530 out: 531 return rc; 532 533 } 534 535 static u32 brcmstb_i2c_functionality(struct i2c_adapter *adap) 536 { 537 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR 538 | I2C_FUNC_NOSTART | I2C_FUNC_PROTOCOL_MANGLING; 539 } 540 541 static const struct i2c_algorithm brcmstb_i2c_algo = { 542 .master_xfer = brcmstb_i2c_xfer, 543 .functionality = brcmstb_i2c_functionality, 544 }; 545 546 static void brcmstb_i2c_set_bus_speed(struct brcmstb_i2c_dev *dev) 547 { 548 int i = 0, num_speeds = ARRAY_SIZE(bsc_clk); 549 u32 clk_freq_hz = dev->clk_freq_hz; 550 551 for (i = 0; i < num_speeds; i++) { 552 if (bsc_clk[i].hz == clk_freq_hz) { 553 dev->bsc_regmap->ctl_reg &= ~(BSC_CTL_REG_SCL_SEL_MASK 554 | BSC_CTL_REG_DIV_CLK_MASK); 555 dev->bsc_regmap->ctl_reg |= (bsc_clk[i].scl_mask | 556 bsc_clk[i].div_mask); 557 bsc_writel(dev, dev->bsc_regmap->ctl_reg, ctl_reg); 558 break; 559 } 560 } 561 562 /* in case we did not get find a valid speed */ 563 if (i == num_speeds) { 564 i = (bsc_readl(dev, ctl_reg) & BSC_CTL_REG_SCL_SEL_MASK) >> 565 BSC_CTL_REG_SCL_SEL_SHIFT; 566 dev_warn(dev->device, "leaving current clock-frequency @ %dHz\n", 567 bsc_clk[i].hz); 568 } 569 } 570 571 static void brcmstb_i2c_set_bsc_reg_defaults(struct brcmstb_i2c_dev *dev) 572 { 573 if (brcmstb_i2c_get_data_regsz(dev) == sizeof(u32)) 574 /* set 4 byte data in/out xfers */ 575 dev->bsc_regmap->ctlhi_reg = BSC_CTLHI_REG_DATAREG_SIZE_MASK; 576 else 577 dev->bsc_regmap->ctlhi_reg &= ~BSC_CTLHI_REG_DATAREG_SIZE_MASK; 578 579 bsc_writel(dev, dev->bsc_regmap->ctlhi_reg, ctlhi_reg); 580 /* set bus speed */ 581 brcmstb_i2c_set_bus_speed(dev); 582 } 583 584 static int brcmstb_i2c_probe(struct platform_device *pdev) 585 { 586 int rc = 0; 587 struct brcmstb_i2c_dev *dev; 588 struct i2c_adapter *adap; 589 struct resource *iomem; 590 const char *int_name; 591 592 /* Allocate memory for private data structure */ 593 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 594 if (!dev) 595 return -ENOMEM; 596 597 dev->bsc_regmap = devm_kzalloc(&pdev->dev, sizeof(*dev->bsc_regmap), GFP_KERNEL); 598 if (!dev->bsc_regmap) 599 return -ENOMEM; 600 601 platform_set_drvdata(pdev, dev); 602 dev->device = &pdev->dev; 603 init_completion(&dev->done); 604 605 /* Map hardware registers */ 606 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 607 dev->base = devm_ioremap_resource(dev->device, iomem); 608 if (IS_ERR(dev->base)) { 609 rc = -ENOMEM; 610 goto probe_errorout; 611 } 612 613 rc = of_property_read_string(dev->device->of_node, "interrupt-names", 614 &int_name); 615 if (rc < 0) 616 int_name = NULL; 617 618 /* Get the interrupt number */ 619 dev->irq = platform_get_irq(pdev, 0); 620 621 /* disable the bsc interrupt line */ 622 brcmstb_i2c_enable_disable_irq(dev, INT_DISABLE); 623 624 /* register the ISR handler */ 625 rc = devm_request_irq(&pdev->dev, dev->irq, brcmstb_i2c_isr, 626 IRQF_SHARED, 627 int_name ? int_name : pdev->name, 628 dev); 629 630 if (rc) { 631 dev_dbg(dev->device, "falling back to polling mode"); 632 dev->irq = -1; 633 } 634 635 if (of_property_read_u32(dev->device->of_node, 636 "clock-frequency", &dev->clk_freq_hz)) { 637 dev_warn(dev->device, "setting clock-frequency@%dHz\n", 638 bsc_clk[0].hz); 639 dev->clk_freq_hz = bsc_clk[0].hz; 640 } 641 642 /* set the data in/out register size for compatible SoCs */ 643 if (of_device_is_compatible(dev->device->of_node, 644 "brcmstb,brcmper-i2c")) 645 dev->data_regsz = sizeof(u8); 646 else 647 dev->data_regsz = sizeof(u32); 648 649 brcmstb_i2c_set_bsc_reg_defaults(dev); 650 651 /* Add the i2c adapter */ 652 adap = &dev->adapter; 653 i2c_set_adapdata(adap, dev); 654 adap->owner = THIS_MODULE; 655 strlcpy(adap->name, "Broadcom STB : ", sizeof(adap->name)); 656 if (int_name) 657 strlcat(adap->name, int_name, sizeof(adap->name)); 658 adap->algo = &brcmstb_i2c_algo; 659 adap->dev.parent = &pdev->dev; 660 adap->dev.of_node = pdev->dev.of_node; 661 rc = i2c_add_adapter(adap); 662 if (rc) 663 goto probe_errorout; 664 665 dev_info(dev->device, "%s@%dhz registered in %s mode\n", 666 int_name ? int_name : " ", dev->clk_freq_hz, 667 (dev->irq >= 0) ? "interrupt" : "polling"); 668 669 return 0; 670 671 probe_errorout: 672 return rc; 673 } 674 675 static int brcmstb_i2c_remove(struct platform_device *pdev) 676 { 677 struct brcmstb_i2c_dev *dev = platform_get_drvdata(pdev); 678 679 i2c_del_adapter(&dev->adapter); 680 return 0; 681 } 682 683 #ifdef CONFIG_PM_SLEEP 684 static int brcmstb_i2c_suspend(struct device *dev) 685 { 686 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 687 688 i2c_mark_adapter_suspended(&i2c_dev->adapter); 689 return 0; 690 } 691 692 static int brcmstb_i2c_resume(struct device *dev) 693 { 694 struct brcmstb_i2c_dev *i2c_dev = dev_get_drvdata(dev); 695 696 brcmstb_i2c_set_bsc_reg_defaults(i2c_dev); 697 i2c_mark_adapter_resumed(&i2c_dev->adapter); 698 699 return 0; 700 } 701 #endif 702 703 static SIMPLE_DEV_PM_OPS(brcmstb_i2c_pm, brcmstb_i2c_suspend, 704 brcmstb_i2c_resume); 705 706 static const struct of_device_id brcmstb_i2c_of_match[] = { 707 {.compatible = "brcm,brcmstb-i2c"}, 708 {.compatible = "brcm,brcmper-i2c"}, 709 {}, 710 }; 711 MODULE_DEVICE_TABLE(of, brcmstb_i2c_of_match); 712 713 static struct platform_driver brcmstb_i2c_driver = { 714 .driver = { 715 .name = "brcmstb-i2c", 716 .of_match_table = brcmstb_i2c_of_match, 717 .pm = &brcmstb_i2c_pm, 718 }, 719 .probe = brcmstb_i2c_probe, 720 .remove = brcmstb_i2c_remove, 721 }; 722 module_platform_driver(brcmstb_i2c_driver); 723 724 MODULE_AUTHOR("Kamal Dasu <kdasu@broadcom.com>"); 725 MODULE_DESCRIPTION("Broadcom Settop I2C Driver"); 726 MODULE_LICENSE("GPL v2"); 727