1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BCM2835 master mode driver 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clkdev.h> 8 #include <linux/clk-provider.h> 9 #include <linux/completion.h> 10 #include <linux/err.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 18 #define BCM2835_I2C_C 0x0 19 #define BCM2835_I2C_S 0x4 20 #define BCM2835_I2C_DLEN 0x8 21 #define BCM2835_I2C_A 0xc 22 #define BCM2835_I2C_FIFO 0x10 23 #define BCM2835_I2C_DIV 0x14 24 #define BCM2835_I2C_DEL 0x18 25 #define BCM2835_I2C_CLKT 0x1c 26 27 #define BCM2835_I2C_C_READ BIT(0) 28 #define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */ 29 #define BCM2835_I2C_C_ST BIT(7) 30 #define BCM2835_I2C_C_INTD BIT(8) 31 #define BCM2835_I2C_C_INTT BIT(9) 32 #define BCM2835_I2C_C_INTR BIT(10) 33 #define BCM2835_I2C_C_I2CEN BIT(15) 34 35 #define BCM2835_I2C_S_TA BIT(0) 36 #define BCM2835_I2C_S_DONE BIT(1) 37 #define BCM2835_I2C_S_TXW BIT(2) 38 #define BCM2835_I2C_S_RXR BIT(3) 39 #define BCM2835_I2C_S_TXD BIT(4) 40 #define BCM2835_I2C_S_RXD BIT(5) 41 #define BCM2835_I2C_S_TXE BIT(6) 42 #define BCM2835_I2C_S_RXF BIT(7) 43 #define BCM2835_I2C_S_ERR BIT(8) 44 #define BCM2835_I2C_S_CLKT BIT(9) 45 #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */ 46 47 #define BCM2835_I2C_FEDL_SHIFT 16 48 #define BCM2835_I2C_REDL_SHIFT 0 49 50 #define BCM2835_I2C_CDIV_MIN 0x0002 51 #define BCM2835_I2C_CDIV_MAX 0xFFFE 52 53 struct bcm2835_i2c_dev { 54 struct device *dev; 55 void __iomem *regs; 56 int irq; 57 struct i2c_adapter adapter; 58 struct completion completion; 59 struct i2c_msg *curr_msg; 60 int num_msgs; 61 u32 msg_err; 62 u8 *msg_buf; 63 size_t msg_buf_remaining; 64 }; 65 66 static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev, 67 u32 reg, u32 val) 68 { 69 writel(val, i2c_dev->regs + reg); 70 } 71 72 static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg) 73 { 74 return readl(i2c_dev->regs + reg); 75 } 76 77 #define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw) 78 struct clk_bcm2835_i2c { 79 struct clk_hw hw; 80 struct bcm2835_i2c_dev *i2c_dev; 81 }; 82 83 static int clk_bcm2835_i2c_calc_divider(unsigned long rate, 84 unsigned long parent_rate) 85 { 86 u32 divider = DIV_ROUND_UP(parent_rate, rate); 87 88 /* 89 * Per the datasheet, the register is always interpreted as an even 90 * number, by rounding down. In other words, the LSB is ignored. So, 91 * if the LSB is set, increment the divider to avoid any issue. 92 */ 93 if (divider & 1) 94 divider++; 95 if ((divider < BCM2835_I2C_CDIV_MIN) || 96 (divider > BCM2835_I2C_CDIV_MAX)) 97 return -EINVAL; 98 99 return divider; 100 } 101 102 static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate, 103 unsigned long parent_rate) 104 { 105 struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw); 106 u32 redl, fedl; 107 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); 108 109 if (divider == -EINVAL) 110 return -EINVAL; 111 112 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); 113 114 /* 115 * Number of core clocks to wait after falling edge before 116 * outputting the next data bit. Note that both FEDL and REDL 117 * can't be greater than CDIV/2. 118 */ 119 fedl = max(divider / 16, 1u); 120 121 /* 122 * Number of core clocks to wait after rising edge before 123 * sampling the next incoming data bit. 124 */ 125 redl = max(divider / 4, 1u); 126 127 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL, 128 (fedl << BCM2835_I2C_FEDL_SHIFT) | 129 (redl << BCM2835_I2C_REDL_SHIFT)); 130 return 0; 131 } 132 133 static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate, 134 unsigned long *parent_rate) 135 { 136 u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate); 137 138 return DIV_ROUND_UP(*parent_rate, divider); 139 } 140 141 static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw, 142 unsigned long parent_rate) 143 { 144 struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw); 145 u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV); 146 147 return DIV_ROUND_UP(parent_rate, divider); 148 } 149 150 static const struct clk_ops clk_bcm2835_i2c_ops = { 151 .set_rate = clk_bcm2835_i2c_set_rate, 152 .round_rate = clk_bcm2835_i2c_round_rate, 153 .recalc_rate = clk_bcm2835_i2c_recalc_rate, 154 }; 155 156 static struct clk *bcm2835_i2c_register_div(struct device *dev, 157 struct clk *mclk, 158 struct bcm2835_i2c_dev *i2c_dev) 159 { 160 struct clk_init_data init; 161 struct clk_bcm2835_i2c *priv; 162 char name[32]; 163 const char *mclk_name; 164 165 snprintf(name, sizeof(name), "%s_div", dev_name(dev)); 166 167 mclk_name = __clk_get_name(mclk); 168 169 init.ops = &clk_bcm2835_i2c_ops; 170 init.name = name; 171 init.parent_names = (const char* []) { mclk_name }; 172 init.num_parents = 1; 173 init.flags = 0; 174 175 priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL); 176 if (priv == NULL) 177 return ERR_PTR(-ENOMEM); 178 179 priv->hw.init = &init; 180 priv->i2c_dev = i2c_dev; 181 182 clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev)); 183 return devm_clk_register(dev, &priv->hw); 184 } 185 186 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev) 187 { 188 u32 val; 189 190 while (i2c_dev->msg_buf_remaining) { 191 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 192 if (!(val & BCM2835_I2C_S_TXD)) 193 break; 194 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO, 195 *i2c_dev->msg_buf); 196 i2c_dev->msg_buf++; 197 i2c_dev->msg_buf_remaining--; 198 } 199 } 200 201 static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev) 202 { 203 u32 val; 204 205 while (i2c_dev->msg_buf_remaining) { 206 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 207 if (!(val & BCM2835_I2C_S_RXD)) 208 break; 209 *i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev, 210 BCM2835_I2C_FIFO); 211 i2c_dev->msg_buf++; 212 i2c_dev->msg_buf_remaining--; 213 } 214 } 215 216 /* 217 * Repeated Start Condition (Sr) 218 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it 219 * talks about reading from a slave with 10 bit address. This is achieved by 220 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then 221 * issue a read. 222 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the 223 * firmware actually does it using polling and says that it's a workaround for 224 * a problem in the state machine. 225 * It turns out that it is possible to use the TXW interrupt to know when the 226 * transfer is active, provided the FIFO has not been prefilled. 227 */ 228 229 static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev) 230 { 231 u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN; 232 struct i2c_msg *msg = i2c_dev->curr_msg; 233 bool last_msg = (i2c_dev->num_msgs == 1); 234 235 if (!i2c_dev->num_msgs) 236 return; 237 238 i2c_dev->num_msgs--; 239 i2c_dev->msg_buf = msg->buf; 240 i2c_dev->msg_buf_remaining = msg->len; 241 242 if (msg->flags & I2C_M_RD) 243 c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR; 244 else 245 c |= BCM2835_I2C_C_INTT; 246 247 if (last_msg) 248 c |= BCM2835_I2C_C_INTD; 249 250 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr); 251 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len); 252 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c); 253 } 254 255 static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev) 256 { 257 i2c_dev->curr_msg = NULL; 258 i2c_dev->num_msgs = 0; 259 260 i2c_dev->msg_buf = NULL; 261 i2c_dev->msg_buf_remaining = 0; 262 } 263 264 /* 265 * Note about I2C_C_CLEAR on error: 266 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in 267 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through 268 * the state machine to send a NACK and a STOP. Since we're setting CLEAR 269 * without I2CEN, that NACK will be hanging around queued up for next time 270 * we start the engine. 271 */ 272 273 static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data) 274 { 275 struct bcm2835_i2c_dev *i2c_dev = data; 276 u32 val, err; 277 278 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 279 280 err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR); 281 if (err) { 282 i2c_dev->msg_err = err; 283 goto complete; 284 } 285 286 if (val & BCM2835_I2C_S_DONE) { 287 if (!i2c_dev->curr_msg) { 288 dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n"); 289 } else if (i2c_dev->curr_msg->flags & I2C_M_RD) { 290 bcm2835_drain_rxfifo(i2c_dev); 291 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 292 } 293 294 if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining) 295 i2c_dev->msg_err = BCM2835_I2C_S_LEN; 296 else 297 i2c_dev->msg_err = 0; 298 goto complete; 299 } 300 301 if (val & BCM2835_I2C_S_TXW) { 302 if (!i2c_dev->msg_buf_remaining) { 303 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; 304 goto complete; 305 } 306 307 bcm2835_fill_txfifo(i2c_dev); 308 309 if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) { 310 i2c_dev->curr_msg++; 311 bcm2835_i2c_start_transfer(i2c_dev); 312 } 313 314 return IRQ_HANDLED; 315 } 316 317 if (val & BCM2835_I2C_S_RXR) { 318 if (!i2c_dev->msg_buf_remaining) { 319 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; 320 goto complete; 321 } 322 323 bcm2835_drain_rxfifo(i2c_dev); 324 return IRQ_HANDLED; 325 } 326 327 return IRQ_NONE; 328 329 complete: 330 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR); 331 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT | 332 BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE); 333 complete(&i2c_dev->completion); 334 335 return IRQ_HANDLED; 336 } 337 338 static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 339 int num) 340 { 341 struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 342 unsigned long time_left; 343 int i; 344 345 for (i = 0; i < (num - 1); i++) 346 if (msgs[i].flags & I2C_M_RD) { 347 dev_warn_once(i2c_dev->dev, 348 "only one read message supported, has to be last\n"); 349 return -EOPNOTSUPP; 350 } 351 352 i2c_dev->curr_msg = msgs; 353 i2c_dev->num_msgs = num; 354 reinit_completion(&i2c_dev->completion); 355 356 bcm2835_i2c_start_transfer(i2c_dev); 357 358 time_left = wait_for_completion_timeout(&i2c_dev->completion, 359 adap->timeout); 360 361 bcm2835_i2c_finish_transfer(i2c_dev); 362 363 if (!time_left) { 364 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 365 BCM2835_I2C_C_CLEAR); 366 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 367 return -ETIMEDOUT; 368 } 369 370 if (!i2c_dev->msg_err) 371 return num; 372 373 dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err); 374 375 if (i2c_dev->msg_err & BCM2835_I2C_S_ERR) 376 return -EREMOTEIO; 377 378 return -EIO; 379 } 380 381 static u32 bcm2835_i2c_func(struct i2c_adapter *adap) 382 { 383 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 384 } 385 386 static const struct i2c_algorithm bcm2835_i2c_algo = { 387 .master_xfer = bcm2835_i2c_xfer, 388 .functionality = bcm2835_i2c_func, 389 }; 390 391 /* 392 * This HW was reported to have problems with clock stretching: 393 * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html 394 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272 395 */ 396 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = { 397 .flags = I2C_AQ_NO_CLK_STRETCH, 398 }; 399 400 static int bcm2835_i2c_probe(struct platform_device *pdev) 401 { 402 struct bcm2835_i2c_dev *i2c_dev; 403 struct resource *mem, *irq; 404 int ret; 405 struct i2c_adapter *adap; 406 struct clk *bus_clk; 407 struct clk *mclk; 408 u32 bus_clk_rate; 409 410 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 411 if (!i2c_dev) 412 return -ENOMEM; 413 platform_set_drvdata(pdev, i2c_dev); 414 i2c_dev->dev = &pdev->dev; 415 init_completion(&i2c_dev->completion); 416 417 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 418 i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem); 419 if (IS_ERR(i2c_dev->regs)) 420 return PTR_ERR(i2c_dev->regs); 421 422 mclk = devm_clk_get(&pdev->dev, NULL); 423 if (IS_ERR(mclk)) { 424 if (PTR_ERR(mclk) != -EPROBE_DEFER) 425 dev_err(&pdev->dev, "Could not get clock\n"); 426 return PTR_ERR(mclk); 427 } 428 429 bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev); 430 431 if (IS_ERR(bus_clk)) { 432 dev_err(&pdev->dev, "Could not register clock\n"); 433 return PTR_ERR(bus_clk); 434 } 435 436 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 437 &bus_clk_rate); 438 if (ret < 0) { 439 dev_warn(&pdev->dev, 440 "Could not read clock-frequency property\n"); 441 bus_clk_rate = 100000; 442 } 443 444 ret = clk_set_rate_exclusive(bus_clk, bus_clk_rate); 445 if (ret < 0) { 446 dev_err(&pdev->dev, "Could not set clock frequency\n"); 447 return ret; 448 } 449 450 ret = clk_prepare_enable(bus_clk); 451 if (ret) { 452 dev_err(&pdev->dev, "Couldn't prepare clock"); 453 return ret; 454 } 455 456 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 457 if (!irq) { 458 dev_err(&pdev->dev, "No IRQ resource\n"); 459 return -ENODEV; 460 } 461 i2c_dev->irq = irq->start; 462 463 ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED, 464 dev_name(&pdev->dev), i2c_dev); 465 if (ret) { 466 dev_err(&pdev->dev, "Could not request IRQ\n"); 467 return -ENODEV; 468 } 469 470 adap = &i2c_dev->adapter; 471 i2c_set_adapdata(adap, i2c_dev); 472 adap->owner = THIS_MODULE; 473 adap->class = I2C_CLASS_DEPRECATED; 474 strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name)); 475 adap->algo = &bcm2835_i2c_algo; 476 adap->dev.parent = &pdev->dev; 477 adap->dev.of_node = pdev->dev.of_node; 478 adap->quirks = &bcm2835_i2c_quirks; 479 480 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0); 481 482 ret = i2c_add_adapter(adap); 483 if (ret) 484 free_irq(i2c_dev->irq, i2c_dev); 485 486 return ret; 487 } 488 489 static int bcm2835_i2c_remove(struct platform_device *pdev) 490 { 491 struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 492 struct clk *bus_clk = devm_clk_get(i2c_dev->dev, "div"); 493 494 clk_rate_exclusive_put(bus_clk); 495 clk_disable_unprepare(bus_clk); 496 497 free_irq(i2c_dev->irq, i2c_dev); 498 i2c_del_adapter(&i2c_dev->adapter); 499 500 return 0; 501 } 502 503 static const struct of_device_id bcm2835_i2c_of_match[] = { 504 { .compatible = "brcm,bcm2835-i2c" }, 505 {}, 506 }; 507 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match); 508 509 static struct platform_driver bcm2835_i2c_driver = { 510 .probe = bcm2835_i2c_probe, 511 .remove = bcm2835_i2c_remove, 512 .driver = { 513 .name = "i2c-bcm2835", 514 .of_match_table = bcm2835_i2c_of_match, 515 }, 516 }; 517 module_platform_driver(bcm2835_i2c_driver); 518 519 MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>"); 520 MODULE_DESCRIPTION("BCM2835 I2C bus adapter"); 521 MODULE_LICENSE("GPL v2"); 522 MODULE_ALIAS("platform:i2c-bcm2835"); 523