1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * BCM2835 master mode driver 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clkdev.h> 8 #include <linux/clk-provider.h> 9 #include <linux/completion.h> 10 #include <linux/err.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 19 #define BCM2835_I2C_C 0x0 20 #define BCM2835_I2C_S 0x4 21 #define BCM2835_I2C_DLEN 0x8 22 #define BCM2835_I2C_A 0xc 23 #define BCM2835_I2C_FIFO 0x10 24 #define BCM2835_I2C_DIV 0x14 25 #define BCM2835_I2C_DEL 0x18 26 #define BCM2835_I2C_CLKT 0x1c 27 28 #define BCM2835_I2C_C_READ BIT(0) 29 #define BCM2835_I2C_C_CLEAR BIT(4) /* bits 4 and 5 both clear */ 30 #define BCM2835_I2C_C_ST BIT(7) 31 #define BCM2835_I2C_C_INTD BIT(8) 32 #define BCM2835_I2C_C_INTT BIT(9) 33 #define BCM2835_I2C_C_INTR BIT(10) 34 #define BCM2835_I2C_C_I2CEN BIT(15) 35 36 #define BCM2835_I2C_S_TA BIT(0) 37 #define BCM2835_I2C_S_DONE BIT(1) 38 #define BCM2835_I2C_S_TXW BIT(2) 39 #define BCM2835_I2C_S_RXR BIT(3) 40 #define BCM2835_I2C_S_TXD BIT(4) 41 #define BCM2835_I2C_S_RXD BIT(5) 42 #define BCM2835_I2C_S_TXE BIT(6) 43 #define BCM2835_I2C_S_RXF BIT(7) 44 #define BCM2835_I2C_S_ERR BIT(8) 45 #define BCM2835_I2C_S_CLKT BIT(9) 46 #define BCM2835_I2C_S_LEN BIT(10) /* Fake bit for SW error reporting */ 47 48 #define BCM2835_I2C_FEDL_SHIFT 16 49 #define BCM2835_I2C_REDL_SHIFT 0 50 51 #define BCM2835_I2C_CDIV_MIN 0x0002 52 #define BCM2835_I2C_CDIV_MAX 0xFFFE 53 54 struct bcm2835_i2c_dev { 55 struct device *dev; 56 void __iomem *regs; 57 int irq; 58 struct i2c_adapter adapter; 59 struct completion completion; 60 struct i2c_msg *curr_msg; 61 int num_msgs; 62 u32 msg_err; 63 u8 *msg_buf; 64 size_t msg_buf_remaining; 65 }; 66 67 static inline void bcm2835_i2c_writel(struct bcm2835_i2c_dev *i2c_dev, 68 u32 reg, u32 val) 69 { 70 writel(val, i2c_dev->regs + reg); 71 } 72 73 static inline u32 bcm2835_i2c_readl(struct bcm2835_i2c_dev *i2c_dev, u32 reg) 74 { 75 return readl(i2c_dev->regs + reg); 76 } 77 78 #define to_clk_bcm2835_i2c(_hw) container_of(_hw, struct clk_bcm2835_i2c, hw) 79 struct clk_bcm2835_i2c { 80 struct clk_hw hw; 81 struct bcm2835_i2c_dev *i2c_dev; 82 }; 83 84 static int clk_bcm2835_i2c_calc_divider(unsigned long rate, 85 unsigned long parent_rate) 86 { 87 u32 divider = DIV_ROUND_UP(parent_rate, rate); 88 89 /* 90 * Per the datasheet, the register is always interpreted as an even 91 * number, by rounding down. In other words, the LSB is ignored. So, 92 * if the LSB is set, increment the divider to avoid any issue. 93 */ 94 if (divider & 1) 95 divider++; 96 if ((divider < BCM2835_I2C_CDIV_MIN) || 97 (divider > BCM2835_I2C_CDIV_MAX)) 98 return -EINVAL; 99 100 return divider; 101 } 102 103 static int clk_bcm2835_i2c_set_rate(struct clk_hw *hw, unsigned long rate, 104 unsigned long parent_rate) 105 { 106 struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw); 107 u32 redl, fedl; 108 u32 divider = clk_bcm2835_i2c_calc_divider(rate, parent_rate); 109 110 if (divider == -EINVAL) 111 return -EINVAL; 112 113 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DIV, divider); 114 115 /* 116 * Number of core clocks to wait after falling edge before 117 * outputting the next data bit. Note that both FEDL and REDL 118 * can't be greater than CDIV/2. 119 */ 120 fedl = max(divider / 16, 1u); 121 122 /* 123 * Number of core clocks to wait after rising edge before 124 * sampling the next incoming data bit. 125 */ 126 redl = max(divider / 4, 1u); 127 128 bcm2835_i2c_writel(div->i2c_dev, BCM2835_I2C_DEL, 129 (fedl << BCM2835_I2C_FEDL_SHIFT) | 130 (redl << BCM2835_I2C_REDL_SHIFT)); 131 return 0; 132 } 133 134 static long clk_bcm2835_i2c_round_rate(struct clk_hw *hw, unsigned long rate, 135 unsigned long *parent_rate) 136 { 137 u32 divider = clk_bcm2835_i2c_calc_divider(rate, *parent_rate); 138 139 return DIV_ROUND_UP(*parent_rate, divider); 140 } 141 142 static unsigned long clk_bcm2835_i2c_recalc_rate(struct clk_hw *hw, 143 unsigned long parent_rate) 144 { 145 struct clk_bcm2835_i2c *div = to_clk_bcm2835_i2c(hw); 146 u32 divider = bcm2835_i2c_readl(div->i2c_dev, BCM2835_I2C_DIV); 147 148 return DIV_ROUND_UP(parent_rate, divider); 149 } 150 151 static const struct clk_ops clk_bcm2835_i2c_ops = { 152 .set_rate = clk_bcm2835_i2c_set_rate, 153 .round_rate = clk_bcm2835_i2c_round_rate, 154 .recalc_rate = clk_bcm2835_i2c_recalc_rate, 155 }; 156 157 static struct clk *bcm2835_i2c_register_div(struct device *dev, 158 struct clk *mclk, 159 struct bcm2835_i2c_dev *i2c_dev) 160 { 161 struct clk_init_data init; 162 struct clk_bcm2835_i2c *priv; 163 char name[32]; 164 const char *mclk_name; 165 166 snprintf(name, sizeof(name), "%s_div", dev_name(dev)); 167 168 mclk_name = __clk_get_name(mclk); 169 170 init.ops = &clk_bcm2835_i2c_ops; 171 init.name = name; 172 init.parent_names = (const char* []) { mclk_name }; 173 init.num_parents = 1; 174 init.flags = 0; 175 176 priv = devm_kzalloc(dev, sizeof(struct clk_bcm2835_i2c), GFP_KERNEL); 177 if (priv == NULL) 178 return ERR_PTR(-ENOMEM); 179 180 priv->hw.init = &init; 181 priv->i2c_dev = i2c_dev; 182 183 clk_hw_register_clkdev(&priv->hw, "div", dev_name(dev)); 184 return devm_clk_register(dev, &priv->hw); 185 } 186 187 static void bcm2835_fill_txfifo(struct bcm2835_i2c_dev *i2c_dev) 188 { 189 u32 val; 190 191 while (i2c_dev->msg_buf_remaining) { 192 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 193 if (!(val & BCM2835_I2C_S_TXD)) 194 break; 195 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_FIFO, 196 *i2c_dev->msg_buf); 197 i2c_dev->msg_buf++; 198 i2c_dev->msg_buf_remaining--; 199 } 200 } 201 202 static void bcm2835_drain_rxfifo(struct bcm2835_i2c_dev *i2c_dev) 203 { 204 u32 val; 205 206 while (i2c_dev->msg_buf_remaining) { 207 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 208 if (!(val & BCM2835_I2C_S_RXD)) 209 break; 210 *i2c_dev->msg_buf = bcm2835_i2c_readl(i2c_dev, 211 BCM2835_I2C_FIFO); 212 i2c_dev->msg_buf++; 213 i2c_dev->msg_buf_remaining--; 214 } 215 } 216 217 /* 218 * Repeated Start Condition (Sr) 219 * The BCM2835 ARM Peripherals datasheet mentions a way to trigger a Sr when it 220 * talks about reading from a slave with 10 bit address. This is achieved by 221 * issuing a write, poll the I2CS.TA flag and wait for it to be set, and then 222 * issue a read. 223 * A comment in https://github.com/raspberrypi/linux/issues/254 shows how the 224 * firmware actually does it using polling and says that it's a workaround for 225 * a problem in the state machine. 226 * It turns out that it is possible to use the TXW interrupt to know when the 227 * transfer is active, provided the FIFO has not been prefilled. 228 */ 229 230 static void bcm2835_i2c_start_transfer(struct bcm2835_i2c_dev *i2c_dev) 231 { 232 u32 c = BCM2835_I2C_C_ST | BCM2835_I2C_C_I2CEN; 233 struct i2c_msg *msg = i2c_dev->curr_msg; 234 bool last_msg = (i2c_dev->num_msgs == 1); 235 236 if (!i2c_dev->num_msgs) 237 return; 238 239 i2c_dev->num_msgs--; 240 i2c_dev->msg_buf = msg->buf; 241 i2c_dev->msg_buf_remaining = msg->len; 242 243 if (msg->flags & I2C_M_RD) 244 c |= BCM2835_I2C_C_READ | BCM2835_I2C_C_INTR; 245 else 246 c |= BCM2835_I2C_C_INTT; 247 248 if (last_msg) 249 c |= BCM2835_I2C_C_INTD; 250 251 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_A, msg->addr); 252 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_DLEN, msg->len); 253 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, c); 254 } 255 256 static void bcm2835_i2c_finish_transfer(struct bcm2835_i2c_dev *i2c_dev) 257 { 258 i2c_dev->curr_msg = NULL; 259 i2c_dev->num_msgs = 0; 260 261 i2c_dev->msg_buf = NULL; 262 i2c_dev->msg_buf_remaining = 0; 263 } 264 265 /* 266 * Note about I2C_C_CLEAR on error: 267 * The I2C_C_CLEAR on errors will take some time to resolve -- if you were in 268 * non-idle state and I2C_C_READ, it sets an abort_rx flag and runs through 269 * the state machine to send a NACK and a STOP. Since we're setting CLEAR 270 * without I2CEN, that NACK will be hanging around queued up for next time 271 * we start the engine. 272 */ 273 274 static irqreturn_t bcm2835_i2c_isr(int this_irq, void *data) 275 { 276 struct bcm2835_i2c_dev *i2c_dev = data; 277 u32 val, err; 278 279 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 280 281 err = val & (BCM2835_I2C_S_CLKT | BCM2835_I2C_S_ERR); 282 if (err) { 283 i2c_dev->msg_err = err; 284 goto complete; 285 } 286 287 if (val & BCM2835_I2C_S_DONE) { 288 if (!i2c_dev->curr_msg) { 289 dev_err(i2c_dev->dev, "Got unexpected interrupt (from firmware?)\n"); 290 } else if (i2c_dev->curr_msg->flags & I2C_M_RD) { 291 bcm2835_drain_rxfifo(i2c_dev); 292 val = bcm2835_i2c_readl(i2c_dev, BCM2835_I2C_S); 293 } 294 295 if ((val & BCM2835_I2C_S_RXD) || i2c_dev->msg_buf_remaining) 296 i2c_dev->msg_err = BCM2835_I2C_S_LEN; 297 else 298 i2c_dev->msg_err = 0; 299 goto complete; 300 } 301 302 if (val & BCM2835_I2C_S_TXW) { 303 if (!i2c_dev->msg_buf_remaining) { 304 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; 305 goto complete; 306 } 307 308 bcm2835_fill_txfifo(i2c_dev); 309 310 if (i2c_dev->num_msgs && !i2c_dev->msg_buf_remaining) { 311 i2c_dev->curr_msg++; 312 bcm2835_i2c_start_transfer(i2c_dev); 313 } 314 315 return IRQ_HANDLED; 316 } 317 318 if (val & BCM2835_I2C_S_RXR) { 319 if (!i2c_dev->msg_buf_remaining) { 320 i2c_dev->msg_err = val | BCM2835_I2C_S_LEN; 321 goto complete; 322 } 323 324 bcm2835_drain_rxfifo(i2c_dev); 325 return IRQ_HANDLED; 326 } 327 328 return IRQ_NONE; 329 330 complete: 331 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, BCM2835_I2C_C_CLEAR); 332 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_S, BCM2835_I2C_S_CLKT | 333 BCM2835_I2C_S_ERR | BCM2835_I2C_S_DONE); 334 complete(&i2c_dev->completion); 335 336 return IRQ_HANDLED; 337 } 338 339 static int bcm2835_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 340 int num) 341 { 342 struct bcm2835_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 343 unsigned long time_left; 344 int i; 345 346 for (i = 0; i < (num - 1); i++) 347 if (msgs[i].flags & I2C_M_RD) { 348 dev_warn_once(i2c_dev->dev, 349 "only one read message supported, has to be last\n"); 350 return -EOPNOTSUPP; 351 } 352 353 i2c_dev->curr_msg = msgs; 354 i2c_dev->num_msgs = num; 355 reinit_completion(&i2c_dev->completion); 356 357 bcm2835_i2c_start_transfer(i2c_dev); 358 359 time_left = wait_for_completion_timeout(&i2c_dev->completion, 360 adap->timeout); 361 362 bcm2835_i2c_finish_transfer(i2c_dev); 363 364 if (!time_left) { 365 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 366 BCM2835_I2C_C_CLEAR); 367 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 368 return -ETIMEDOUT; 369 } 370 371 if (!i2c_dev->msg_err) 372 return num; 373 374 dev_dbg(i2c_dev->dev, "i2c transfer failed: %x\n", i2c_dev->msg_err); 375 376 if (i2c_dev->msg_err & BCM2835_I2C_S_ERR) 377 return -EREMOTEIO; 378 379 return -EIO; 380 } 381 382 static u32 bcm2835_i2c_func(struct i2c_adapter *adap) 383 { 384 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 385 } 386 387 static const struct i2c_algorithm bcm2835_i2c_algo = { 388 .master_xfer = bcm2835_i2c_xfer, 389 .functionality = bcm2835_i2c_func, 390 }; 391 392 /* 393 * The BCM2835 was reported to have problems with clock stretching: 394 * http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html 395 * https://www.raspberrypi.org/forums/viewtopic.php?p=146272 396 */ 397 static const struct i2c_adapter_quirks bcm2835_i2c_quirks = { 398 .flags = I2C_AQ_NO_CLK_STRETCH, 399 }; 400 401 static int bcm2835_i2c_probe(struct platform_device *pdev) 402 { 403 struct bcm2835_i2c_dev *i2c_dev; 404 struct resource *mem, *irq; 405 int ret; 406 struct i2c_adapter *adap; 407 struct clk *bus_clk; 408 struct clk *mclk; 409 u32 bus_clk_rate; 410 411 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 412 if (!i2c_dev) 413 return -ENOMEM; 414 platform_set_drvdata(pdev, i2c_dev); 415 i2c_dev->dev = &pdev->dev; 416 init_completion(&i2c_dev->completion); 417 418 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 419 i2c_dev->regs = devm_ioremap_resource(&pdev->dev, mem); 420 if (IS_ERR(i2c_dev->regs)) 421 return PTR_ERR(i2c_dev->regs); 422 423 mclk = devm_clk_get(&pdev->dev, NULL); 424 if (IS_ERR(mclk)) { 425 if (PTR_ERR(mclk) != -EPROBE_DEFER) 426 dev_err(&pdev->dev, "Could not get clock\n"); 427 return PTR_ERR(mclk); 428 } 429 430 bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev); 431 432 if (IS_ERR(bus_clk)) { 433 dev_err(&pdev->dev, "Could not register clock\n"); 434 return PTR_ERR(bus_clk); 435 } 436 437 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 438 &bus_clk_rate); 439 if (ret < 0) { 440 dev_warn(&pdev->dev, 441 "Could not read clock-frequency property\n"); 442 bus_clk_rate = 100000; 443 } 444 445 ret = clk_set_rate_exclusive(bus_clk, bus_clk_rate); 446 if (ret < 0) { 447 dev_err(&pdev->dev, "Could not set clock frequency\n"); 448 return ret; 449 } 450 451 ret = clk_prepare_enable(bus_clk); 452 if (ret) { 453 dev_err(&pdev->dev, "Couldn't prepare clock"); 454 return ret; 455 } 456 457 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 458 if (!irq) { 459 dev_err(&pdev->dev, "No IRQ resource\n"); 460 return -ENODEV; 461 } 462 i2c_dev->irq = irq->start; 463 464 ret = request_irq(i2c_dev->irq, bcm2835_i2c_isr, IRQF_SHARED, 465 dev_name(&pdev->dev), i2c_dev); 466 if (ret) { 467 dev_err(&pdev->dev, "Could not request IRQ\n"); 468 return -ENODEV; 469 } 470 471 adap = &i2c_dev->adapter; 472 i2c_set_adapdata(adap, i2c_dev); 473 adap->owner = THIS_MODULE; 474 adap->class = I2C_CLASS_DEPRECATED; 475 snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)", 476 of_node_full_name(pdev->dev.of_node)); 477 adap->algo = &bcm2835_i2c_algo; 478 adap->dev.parent = &pdev->dev; 479 adap->dev.of_node = pdev->dev.of_node; 480 adap->quirks = of_device_get_match_data(&pdev->dev); 481 482 bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0); 483 484 ret = i2c_add_adapter(adap); 485 if (ret) 486 free_irq(i2c_dev->irq, i2c_dev); 487 488 return ret; 489 } 490 491 static int bcm2835_i2c_remove(struct platform_device *pdev) 492 { 493 struct bcm2835_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 494 struct clk *bus_clk = devm_clk_get(i2c_dev->dev, "div"); 495 496 clk_rate_exclusive_put(bus_clk); 497 clk_disable_unprepare(bus_clk); 498 499 free_irq(i2c_dev->irq, i2c_dev); 500 i2c_del_adapter(&i2c_dev->adapter); 501 502 return 0; 503 } 504 505 static const struct of_device_id bcm2835_i2c_of_match[] = { 506 { .compatible = "brcm,bcm2711-i2c" }, 507 { .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks }, 508 {}, 509 }; 510 MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match); 511 512 static struct platform_driver bcm2835_i2c_driver = { 513 .probe = bcm2835_i2c_probe, 514 .remove = bcm2835_i2c_remove, 515 .driver = { 516 .name = "i2c-bcm2835", 517 .of_match_table = bcm2835_i2c_of_match, 518 }, 519 }; 520 module_platform_driver(bcm2835_i2c_driver); 521 522 MODULE_AUTHOR("Stephen Warren <swarren@wwwdotorg.org>"); 523 MODULE_DESCRIPTION("BCM2835 I2C bus adapter"); 524 MODULE_LICENSE("GPL v2"); 525 MODULE_ALIAS("platform:i2c-bcm2835"); 526