1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/i2c.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 24 #define IDM_CTRL_DIRECT_OFFSET 0x00 25 #define CFG_OFFSET 0x00 26 #define CFG_RESET_SHIFT 31 27 #define CFG_EN_SHIFT 30 28 #define CFG_SLAVE_ADDR_0_SHIFT 28 29 #define CFG_M_RETRY_CNT_SHIFT 16 30 #define CFG_M_RETRY_CNT_MASK 0x0f 31 32 #define TIM_CFG_OFFSET 0x04 33 #define TIM_CFG_MODE_400_SHIFT 31 34 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24 35 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f 36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16 37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f 38 39 #define S_CFG_SMBUS_ADDR_OFFSET 0x08 40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31 41 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24 42 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f 43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23 44 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16 45 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f 46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15 47 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8 48 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f 49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7 50 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0 51 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f 52 53 #define M_FIFO_CTRL_OFFSET 0x0c 54 #define M_FIFO_RX_FLUSH_SHIFT 31 55 #define M_FIFO_TX_FLUSH_SHIFT 30 56 #define M_FIFO_RX_CNT_SHIFT 16 57 #define M_FIFO_RX_CNT_MASK 0x7f 58 #define M_FIFO_RX_THLD_SHIFT 8 59 #define M_FIFO_RX_THLD_MASK 0x3f 60 61 #define S_FIFO_CTRL_OFFSET 0x10 62 #define S_FIFO_RX_FLUSH_SHIFT 31 63 #define S_FIFO_TX_FLUSH_SHIFT 30 64 #define S_FIFO_RX_CNT_SHIFT 16 65 #define S_FIFO_RX_CNT_MASK 0x7f 66 #define S_FIFO_RX_THLD_SHIFT 8 67 #define S_FIFO_RX_THLD_MASK 0x3f 68 69 #define M_CMD_OFFSET 0x30 70 #define M_CMD_START_BUSY_SHIFT 31 71 #define M_CMD_STATUS_SHIFT 25 72 #define M_CMD_STATUS_MASK 0x07 73 #define M_CMD_STATUS_SUCCESS 0x0 74 #define M_CMD_STATUS_LOST_ARB 0x1 75 #define M_CMD_STATUS_NACK_ADDR 0x2 76 #define M_CMD_STATUS_NACK_DATA 0x3 77 #define M_CMD_STATUS_TIMEOUT 0x4 78 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5 79 #define M_CMD_STATUS_RX_FIFO_FULL 0x6 80 #define M_CMD_PROTOCOL_SHIFT 9 81 #define M_CMD_PROTOCOL_MASK 0xf 82 #define M_CMD_PROTOCOL_BLK_WR 0x7 83 #define M_CMD_PROTOCOL_BLK_RD 0x8 84 #define M_CMD_PEC_SHIFT 8 85 #define M_CMD_RD_CNT_SHIFT 0 86 #define M_CMD_RD_CNT_MASK 0xff 87 88 #define S_CMD_OFFSET 0x34 89 #define S_CMD_START_BUSY_SHIFT 31 90 #define S_CMD_STATUS_SHIFT 23 91 #define S_CMD_STATUS_MASK 0x07 92 #define S_CMD_STATUS_SUCCESS 0x0 93 #define S_CMD_STATUS_TIMEOUT 0x5 94 95 #define IE_OFFSET 0x38 96 #define IE_M_RX_FIFO_FULL_SHIFT 31 97 #define IE_M_RX_THLD_SHIFT 30 98 #define IE_M_START_BUSY_SHIFT 28 99 #define IE_M_TX_UNDERRUN_SHIFT 27 100 #define IE_S_RX_FIFO_FULL_SHIFT 26 101 #define IE_S_RX_THLD_SHIFT 25 102 #define IE_S_RX_EVENT_SHIFT 24 103 #define IE_S_START_BUSY_SHIFT 23 104 #define IE_S_TX_UNDERRUN_SHIFT 22 105 #define IE_S_RD_EVENT_SHIFT 21 106 107 #define IS_OFFSET 0x3c 108 #define IS_M_RX_FIFO_FULL_SHIFT 31 109 #define IS_M_RX_THLD_SHIFT 30 110 #define IS_M_START_BUSY_SHIFT 28 111 #define IS_M_TX_UNDERRUN_SHIFT 27 112 #define IS_S_RX_FIFO_FULL_SHIFT 26 113 #define IS_S_RX_THLD_SHIFT 25 114 #define IS_S_RX_EVENT_SHIFT 24 115 #define IS_S_START_BUSY_SHIFT 23 116 #define IS_S_TX_UNDERRUN_SHIFT 22 117 #define IS_S_RD_EVENT_SHIFT 21 118 119 #define M_TX_OFFSET 0x40 120 #define M_TX_WR_STATUS_SHIFT 31 121 #define M_TX_DATA_SHIFT 0 122 #define M_TX_DATA_MASK 0xff 123 124 #define M_RX_OFFSET 0x44 125 #define M_RX_STATUS_SHIFT 30 126 #define M_RX_STATUS_MASK 0x03 127 #define M_RX_PEC_ERR_SHIFT 29 128 #define M_RX_DATA_SHIFT 0 129 #define M_RX_DATA_MASK 0xff 130 131 #define S_TX_OFFSET 0x48 132 #define S_TX_WR_STATUS_SHIFT 31 133 #define S_TX_DATA_SHIFT 0 134 #define S_TX_DATA_MASK 0xff 135 136 #define S_RX_OFFSET 0x4c 137 #define S_RX_STATUS_SHIFT 30 138 #define S_RX_STATUS_MASK 0x03 139 #define S_RX_PEC_ERR_SHIFT 29 140 #define S_RX_DATA_SHIFT 0 141 #define S_RX_DATA_MASK 0xff 142 143 #define I2C_TIMEOUT_MSEC 50000 144 #define M_TX_RX_FIFO_SIZE 64 145 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1) 146 147 #define M_RX_MAX_READ_LEN 255 148 #define M_RX_FIFO_THLD_VALUE 50 149 150 #define IE_M_ALL_INTERRUPT_SHIFT 27 151 #define IE_M_ALL_INTERRUPT_MASK 0x1e 152 153 #define SLAVE_READ_WRITE_BIT_MASK 0x1 154 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1 155 #define SLAVE_MAX_SIZE_TRANSACTION 64 156 #define SLAVE_CLOCK_STRETCH_TIME 25 157 158 #define IE_S_ALL_INTERRUPT_SHIFT 21 159 #define IE_S_ALL_INTERRUPT_MASK 0x3f 160 161 enum i2c_slave_read_status { 162 I2C_SLAVE_RX_FIFO_EMPTY = 0, 163 I2C_SLAVE_RX_START, 164 I2C_SLAVE_RX_DATA, 165 I2C_SLAVE_RX_END, 166 }; 167 168 enum bus_speed_index { 169 I2C_SPD_100K = 0, 170 I2C_SPD_400K, 171 }; 172 173 enum bcm_iproc_i2c_type { 174 IPROC_I2C, 175 IPROC_I2C_NIC 176 }; 177 178 struct bcm_iproc_i2c_dev { 179 struct device *device; 180 enum bcm_iproc_i2c_type type; 181 int irq; 182 183 void __iomem *base; 184 void __iomem *idm_base; 185 186 u32 ape_addr_mask; 187 188 /* lock for indirect access through IDM */ 189 spinlock_t idm_lock; 190 191 struct i2c_adapter adapter; 192 unsigned int bus_speed; 193 194 struct completion done; 195 int xfer_is_done; 196 197 struct i2c_msg *msg; 198 199 struct i2c_client *slave; 200 201 /* bytes that have been transferred */ 202 unsigned int tx_bytes; 203 /* bytes that have been read */ 204 unsigned int rx_bytes; 205 unsigned int thld_bytes; 206 }; 207 208 /* 209 * Can be expanded in the future if more interrupt status bits are utilized 210 */ 211 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ 212 | BIT(IS_M_RX_THLD_SHIFT)) 213 214 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\ 215 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\ 216 | BIT(IS_S_TX_UNDERRUN_SHIFT)) 217 218 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave); 219 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); 220 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 221 bool enable); 222 223 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 224 u32 offset) 225 { 226 u32 val; 227 228 if (iproc_i2c->idm_base) { 229 spin_lock(&iproc_i2c->idm_lock); 230 writel(iproc_i2c->ape_addr_mask, 231 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 232 val = readl(iproc_i2c->base + offset); 233 spin_unlock(&iproc_i2c->idm_lock); 234 } else { 235 val = readl(iproc_i2c->base + offset); 236 } 237 238 return val; 239 } 240 241 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 242 u32 offset, u32 val) 243 { 244 if (iproc_i2c->idm_base) { 245 spin_lock(&iproc_i2c->idm_lock); 246 writel(iproc_i2c->ape_addr_mask, 247 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 248 writel(val, iproc_i2c->base + offset); 249 spin_unlock(&iproc_i2c->idm_lock); 250 } else { 251 writel(val, iproc_i2c->base + offset); 252 } 253 } 254 255 static void bcm_iproc_i2c_slave_init( 256 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) 257 { 258 u32 val; 259 260 if (need_reset) { 261 /* put controller in reset */ 262 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 263 val |= BIT(CFG_RESET_SHIFT); 264 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 265 266 /* wait 100 usec per spec */ 267 udelay(100); 268 269 /* bring controller out of reset */ 270 val &= ~(BIT(CFG_RESET_SHIFT)); 271 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 272 } 273 274 /* flush TX/RX FIFOs */ 275 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); 276 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); 277 278 /* Maximum slave stretch time */ 279 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 280 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); 281 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); 282 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 283 284 /* Configure the slave address */ 285 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 286 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 287 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); 288 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); 289 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val); 290 291 /* clear all pending slave interrupts */ 292 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); 293 294 /* Enable interrupt register to indicate a valid byte in receive fifo */ 295 val = BIT(IE_S_RX_EVENT_SHIFT); 296 /* Enable interrupt register for the Slave BUSY command */ 297 val |= BIT(IE_S_START_BUSY_SHIFT); 298 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 299 } 300 301 static void bcm_iproc_i2c_check_slave_status( 302 struct bcm_iproc_i2c_dev *iproc_i2c) 303 { 304 u32 val; 305 306 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET); 307 /* status is valid only when START_BUSY is cleared after it was set */ 308 if (val & BIT(S_CMD_START_BUSY_SHIFT)) 309 return; 310 311 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; 312 if (val == S_CMD_STATUS_TIMEOUT) { 313 dev_err(iproc_i2c->device, "slave random stretch time timeout\n"); 314 315 /* re-initialize i2c for recovery */ 316 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 317 bcm_iproc_i2c_slave_init(iproc_i2c, true); 318 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 319 } 320 } 321 322 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, 323 u32 status) 324 { 325 u32 val; 326 u8 value, rx_status; 327 328 /* Slave RX byte receive */ 329 if (status & BIT(IS_S_RX_EVENT_SHIFT)) { 330 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); 331 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; 332 if (rx_status == I2C_SLAVE_RX_START) { 333 /* Start of SMBUS for Master write */ 334 i2c_slave_event(iproc_i2c->slave, 335 I2C_SLAVE_WRITE_REQUESTED, &value); 336 337 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); 338 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); 339 i2c_slave_event(iproc_i2c->slave, 340 I2C_SLAVE_WRITE_RECEIVED, &value); 341 } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) { 342 /* Start of SMBUS for Master Read */ 343 i2c_slave_event(iproc_i2c->slave, 344 I2C_SLAVE_READ_REQUESTED, &value); 345 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value); 346 347 val = BIT(S_CMD_START_BUSY_SHIFT); 348 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); 349 350 /* 351 * Enable interrupt for TX FIFO becomes empty and 352 * less than PKT_LENGTH bytes were output on the SMBUS 353 */ 354 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 355 val |= BIT(IE_S_TX_UNDERRUN_SHIFT); 356 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 357 } else { 358 /* Master write other than start */ 359 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); 360 i2c_slave_event(iproc_i2c->slave, 361 I2C_SLAVE_WRITE_RECEIVED, &value); 362 } 363 } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) { 364 /* Master read other than start */ 365 i2c_slave_event(iproc_i2c->slave, 366 I2C_SLAVE_READ_PROCESSED, &value); 367 368 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value); 369 val = BIT(S_CMD_START_BUSY_SHIFT); 370 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); 371 } 372 373 /* Stop */ 374 if (status & BIT(IS_S_START_BUSY_SHIFT)) { 375 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value); 376 /* 377 * Enable interrupt for TX FIFO becomes empty and 378 * less than PKT_LENGTH bytes were output on the SMBUS 379 */ 380 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 381 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT); 382 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 383 } 384 385 /* clear interrupt status */ 386 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 387 388 bcm_iproc_i2c_check_slave_status(iproc_i2c); 389 return true; 390 } 391 392 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) 393 { 394 struct i2c_msg *msg = iproc_i2c->msg; 395 396 /* Read valid data from RX FIFO */ 397 while (iproc_i2c->rx_bytes < msg->len) { 398 if (!((iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET) >> M_FIFO_RX_CNT_SHIFT) 399 & M_FIFO_RX_CNT_MASK)) 400 break; 401 402 msg->buf[iproc_i2c->rx_bytes] = 403 (iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET) >> 404 M_RX_DATA_SHIFT) & M_RX_DATA_MASK; 405 iproc_i2c->rx_bytes++; 406 } 407 } 408 409 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) 410 { 411 struct i2c_msg *msg = iproc_i2c->msg; 412 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; 413 unsigned int i; 414 u32 val; 415 416 /* can only fill up to the FIFO size */ 417 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); 418 for (i = 0; i < tx_bytes; i++) { 419 /* start from where we left over */ 420 unsigned int idx = iproc_i2c->tx_bytes + i; 421 422 val = msg->buf[idx]; 423 424 /* mark the last byte */ 425 if (idx == msg->len - 1) { 426 val |= BIT(M_TX_WR_STATUS_SHIFT); 427 428 if (iproc_i2c->irq) { 429 u32 tmp; 430 431 /* 432 * Since this is the last byte, we should now 433 * disable TX FIFO underrun interrupt 434 */ 435 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 436 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); 437 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 438 tmp); 439 } 440 } 441 442 /* load data into TX FIFO */ 443 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 444 } 445 446 /* update number of transferred bytes */ 447 iproc_i2c->tx_bytes += tx_bytes; 448 } 449 450 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) 451 { 452 struct i2c_msg *msg = iproc_i2c->msg; 453 u32 bytes_left, val; 454 455 bcm_iproc_i2c_read_valid_bytes(iproc_i2c); 456 bytes_left = msg->len - iproc_i2c->rx_bytes; 457 if (bytes_left == 0) { 458 if (iproc_i2c->irq) { 459 /* finished reading all data, disable rx thld event */ 460 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 461 val &= ~BIT(IS_M_RX_THLD_SHIFT); 462 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 463 } 464 } else if (bytes_left < iproc_i2c->thld_bytes) { 465 /* set bytes left as threshold */ 466 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 467 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 468 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); 469 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 470 iproc_i2c->thld_bytes = bytes_left; 471 } 472 /* 473 * bytes_left >= iproc_i2c->thld_bytes, 474 * hence no need to change the THRESHOLD SET. 475 * It will remain as iproc_i2c->thld_bytes itself 476 */ 477 } 478 479 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, 480 u32 status) 481 { 482 /* TX FIFO is empty and we have more data to send */ 483 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) 484 bcm_iproc_i2c_send(iproc_i2c); 485 486 /* RX FIFO threshold is reached and data needs to be read out */ 487 if (status & BIT(IS_M_RX_THLD_SHIFT)) 488 bcm_iproc_i2c_read(iproc_i2c); 489 490 /* transfer is done */ 491 if (status & BIT(IS_M_START_BUSY_SHIFT)) { 492 iproc_i2c->xfer_is_done = 1; 493 if (iproc_i2c->irq) 494 complete(&iproc_i2c->done); 495 } 496 } 497 498 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) 499 { 500 struct bcm_iproc_i2c_dev *iproc_i2c = data; 501 u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET); 502 bool ret; 503 u32 sl_status = status & ISR_MASK_SLAVE; 504 505 if (sl_status) { 506 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status); 507 if (ret) 508 return IRQ_HANDLED; 509 else 510 return IRQ_NONE; 511 } 512 513 status &= ISR_MASK; 514 if (!status) 515 return IRQ_NONE; 516 517 /* process all master based events */ 518 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 519 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 520 521 return IRQ_HANDLED; 522 } 523 524 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) 525 { 526 u32 val; 527 528 /* put controller in reset */ 529 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 530 val |= BIT(CFG_RESET_SHIFT); 531 val &= ~(BIT(CFG_EN_SHIFT)); 532 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 533 534 /* wait 100 usec per spec */ 535 udelay(100); 536 537 /* bring controller out of reset */ 538 val &= ~(BIT(CFG_RESET_SHIFT)); 539 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 540 541 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ 542 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); 543 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 544 /* disable all interrupts */ 545 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 546 val &= ~(IE_M_ALL_INTERRUPT_MASK << 547 IE_M_ALL_INTERRUPT_SHIFT); 548 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 549 550 /* clear all pending interrupts */ 551 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff); 552 553 return 0; 554 } 555 556 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 557 bool enable) 558 { 559 u32 val; 560 561 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 562 if (enable) 563 val |= BIT(CFG_EN_SHIFT); 564 else 565 val &= ~BIT(CFG_EN_SHIFT); 566 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 567 } 568 569 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, 570 struct i2c_msg *msg) 571 { 572 u32 val; 573 574 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET); 575 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; 576 577 switch (val) { 578 case M_CMD_STATUS_SUCCESS: 579 return 0; 580 581 case M_CMD_STATUS_LOST_ARB: 582 dev_dbg(iproc_i2c->device, "lost bus arbitration\n"); 583 return -EAGAIN; 584 585 case M_CMD_STATUS_NACK_ADDR: 586 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr); 587 return -ENXIO; 588 589 case M_CMD_STATUS_NACK_DATA: 590 dev_dbg(iproc_i2c->device, "NAK data\n"); 591 return -ENXIO; 592 593 case M_CMD_STATUS_TIMEOUT: 594 dev_dbg(iproc_i2c->device, "bus timeout\n"); 595 return -ETIMEDOUT; 596 597 case M_CMD_STATUS_FIFO_UNDERRUN: 598 dev_dbg(iproc_i2c->device, "FIFO under-run\n"); 599 return -ENXIO; 600 601 case M_CMD_STATUS_RX_FIFO_FULL: 602 dev_dbg(iproc_i2c->device, "RX FIFO full\n"); 603 return -ETIMEDOUT; 604 605 default: 606 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); 607 608 /* re-initialize i2c for recovery */ 609 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 610 bcm_iproc_i2c_init(iproc_i2c); 611 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 612 613 return -EIO; 614 } 615 } 616 617 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, 618 struct i2c_msg *msg, 619 u32 cmd) 620 { 621 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); 622 u32 val, status; 623 int ret; 624 625 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd); 626 627 if (iproc_i2c->irq) { 628 time_left = wait_for_completion_timeout(&iproc_i2c->done, 629 time_left); 630 /* disable all interrupts */ 631 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 632 /* read it back to flush the write */ 633 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 634 /* make sure the interrupt handler isn't running */ 635 synchronize_irq(iproc_i2c->irq); 636 637 } else { /* polling mode */ 638 unsigned long timeout = jiffies + time_left; 639 640 do { 641 status = iproc_i2c_rd_reg(iproc_i2c, 642 IS_OFFSET) & ISR_MASK; 643 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 644 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 645 646 if (time_after(jiffies, timeout)) { 647 time_left = 0; 648 break; 649 } 650 651 cpu_relax(); 652 cond_resched(); 653 } while (!iproc_i2c->xfer_is_done); 654 } 655 656 if (!time_left && !iproc_i2c->xfer_is_done) { 657 dev_err(iproc_i2c->device, "transaction timed out\n"); 658 659 /* flush both TX/RX FIFOs */ 660 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 661 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 662 return -ETIMEDOUT; 663 } 664 665 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); 666 if (ret) { 667 /* flush both TX/RX FIFOs */ 668 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 669 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 670 return ret; 671 } 672 673 return 0; 674 } 675 676 static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, 677 struct i2c_msg *msg) 678 { 679 int i; 680 u8 addr; 681 u32 val, tmp, val_intr_en; 682 unsigned int tx_bytes; 683 684 /* check if bus is busy */ 685 if (!!(iproc_i2c_rd_reg(iproc_i2c, 686 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) { 687 dev_warn(iproc_i2c->device, "bus is busy\n"); 688 return -EBUSY; 689 } 690 691 iproc_i2c->msg = msg; 692 693 /* format and load slave address into the TX FIFO */ 694 addr = i2c_8bit_addr_from_msg(msg); 695 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr); 696 697 /* 698 * For a write transaction, load data into the TX FIFO. Only allow 699 * loading up to TX FIFO size - 1 bytes of data since the first byte 700 * has been used up by the slave address 701 */ 702 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1); 703 if (!(msg->flags & I2C_M_RD)) { 704 for (i = 0; i < tx_bytes; i++) { 705 val = msg->buf[i]; 706 707 /* mark the last byte */ 708 if (i == msg->len - 1) 709 val |= BIT(M_TX_WR_STATUS_SHIFT); 710 711 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 712 } 713 iproc_i2c->tx_bytes = tx_bytes; 714 } 715 716 /* mark as incomplete before starting the transaction */ 717 if (iproc_i2c->irq) 718 reinit_completion(&iproc_i2c->done); 719 720 iproc_i2c->xfer_is_done = 0; 721 722 /* 723 * Enable the "start busy" interrupt, which will be triggered after the 724 * transaction is done, i.e., the internal start_busy bit, transitions 725 * from 1 to 0. 726 */ 727 val_intr_en = BIT(IE_M_START_BUSY_SHIFT); 728 729 /* 730 * If TX data size is larger than the TX FIFO, need to enable TX 731 * underrun interrupt, which will be triggerred when the TX FIFO is 732 * empty. When that happens we can then pump more data into the FIFO 733 */ 734 if (!(msg->flags & I2C_M_RD) && 735 msg->len > iproc_i2c->tx_bytes) 736 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); 737 738 /* 739 * Now we can activate the transfer. For a read operation, specify the 740 * number of bytes to read 741 */ 742 val = BIT(M_CMD_START_BUSY_SHIFT); 743 if (msg->flags & I2C_M_RD) { 744 iproc_i2c->rx_bytes = 0; 745 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) 746 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE; 747 else 748 iproc_i2c->thld_bytes = msg->len; 749 750 /* set threshold value */ 751 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 752 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 753 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT; 754 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp); 755 756 /* enable the RX threshold interrupt */ 757 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); 758 759 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) | 760 (msg->len << M_CMD_RD_CNT_SHIFT); 761 } else { 762 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); 763 } 764 765 if (iproc_i2c->irq) 766 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en); 767 768 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val); 769 } 770 771 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, 772 struct i2c_msg msgs[], int num) 773 { 774 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter); 775 int ret, i; 776 777 /* go through all messages */ 778 for (i = 0; i < num; i++) { 779 ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]); 780 if (ret) { 781 dev_dbg(iproc_i2c->device, "xfer failed\n"); 782 return ret; 783 } 784 } 785 786 return num; 787 } 788 789 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) 790 { 791 u32 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 792 793 if (adap->algo->reg_slave) 794 val |= I2C_FUNC_SLAVE; 795 796 return val; 797 } 798 799 static struct i2c_algorithm bcm_iproc_algo = { 800 .master_xfer = bcm_iproc_i2c_xfer, 801 .functionality = bcm_iproc_i2c_functionality, 802 .reg_slave = bcm_iproc_i2c_reg_slave, 803 .unreg_slave = bcm_iproc_i2c_unreg_slave, 804 }; 805 806 static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { 807 .max_read_len = M_RX_MAX_READ_LEN, 808 }; 809 810 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) 811 { 812 unsigned int bus_speed; 813 u32 val; 814 int ret = of_property_read_u32(iproc_i2c->device->of_node, 815 "clock-frequency", &bus_speed); 816 if (ret < 0) { 817 dev_info(iproc_i2c->device, 818 "unable to interpret clock-frequency DT property\n"); 819 bus_speed = 100000; 820 } 821 822 if (bus_speed < 100000) { 823 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n", 824 bus_speed); 825 dev_err(iproc_i2c->device, 826 "valid speeds are 100khz and 400khz\n"); 827 return -EINVAL; 828 } else if (bus_speed < 400000) { 829 bus_speed = 100000; 830 } else { 831 bus_speed = 400000; 832 } 833 834 iproc_i2c->bus_speed = bus_speed; 835 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 836 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 837 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 838 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 839 840 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed); 841 842 return 0; 843 } 844 845 static int bcm_iproc_i2c_probe(struct platform_device *pdev) 846 { 847 int irq, ret = 0; 848 struct bcm_iproc_i2c_dev *iproc_i2c; 849 struct i2c_adapter *adap; 850 struct resource *res; 851 852 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c), 853 GFP_KERNEL); 854 if (!iproc_i2c) 855 return -ENOMEM; 856 857 platform_set_drvdata(pdev, iproc_i2c); 858 iproc_i2c->device = &pdev->dev; 859 iproc_i2c->type = 860 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev); 861 init_completion(&iproc_i2c->done); 862 863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 864 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res); 865 if (IS_ERR(iproc_i2c->base)) 866 return PTR_ERR(iproc_i2c->base); 867 868 if (iproc_i2c->type == IPROC_I2C_NIC) { 869 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 870 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device, 871 res); 872 if (IS_ERR(iproc_i2c->idm_base)) 873 return PTR_ERR(iproc_i2c->idm_base); 874 875 ret = of_property_read_u32(iproc_i2c->device->of_node, 876 "brcm,ape-hsls-addr-mask", 877 &iproc_i2c->ape_addr_mask); 878 if (ret < 0) { 879 dev_err(iproc_i2c->device, 880 "'brcm,ape-hsls-addr-mask' missing\n"); 881 return -EINVAL; 882 } 883 884 spin_lock_init(&iproc_i2c->idm_lock); 885 886 /* no slave support */ 887 bcm_iproc_algo.reg_slave = NULL; 888 bcm_iproc_algo.unreg_slave = NULL; 889 } 890 891 ret = bcm_iproc_i2c_init(iproc_i2c); 892 if (ret) 893 return ret; 894 895 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c); 896 if (ret) 897 return ret; 898 899 irq = platform_get_irq(pdev, 0); 900 if (irq > 0) { 901 ret = devm_request_irq(iproc_i2c->device, irq, 902 bcm_iproc_i2c_isr, 0, pdev->name, 903 iproc_i2c); 904 if (ret < 0) { 905 dev_err(iproc_i2c->device, 906 "unable to request irq %i\n", irq); 907 return ret; 908 } 909 910 iproc_i2c->irq = irq; 911 } else { 912 dev_warn(iproc_i2c->device, 913 "no irq resource, falling back to poll mode\n"); 914 } 915 916 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 917 918 adap = &iproc_i2c->adapter; 919 i2c_set_adapdata(adap, iproc_i2c); 920 strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name)); 921 adap->algo = &bcm_iproc_algo; 922 adap->quirks = &bcm_iproc_i2c_quirks; 923 adap->dev.parent = &pdev->dev; 924 adap->dev.of_node = pdev->dev.of_node; 925 926 return i2c_add_adapter(adap); 927 } 928 929 static int bcm_iproc_i2c_remove(struct platform_device *pdev) 930 { 931 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 932 933 if (iproc_i2c->irq) { 934 /* 935 * Make sure there's no pending interrupt when we remove the 936 * adapter 937 */ 938 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 939 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 940 synchronize_irq(iproc_i2c->irq); 941 } 942 943 i2c_del_adapter(&iproc_i2c->adapter); 944 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 945 946 return 0; 947 } 948 949 #ifdef CONFIG_PM_SLEEP 950 951 static int bcm_iproc_i2c_suspend(struct device *dev) 952 { 953 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 954 955 if (iproc_i2c->irq) { 956 /* 957 * Make sure there's no pending interrupt when we go into 958 * suspend 959 */ 960 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 961 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 962 synchronize_irq(iproc_i2c->irq); 963 } 964 965 /* now disable the controller */ 966 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 967 968 return 0; 969 } 970 971 static int bcm_iproc_i2c_resume(struct device *dev) 972 { 973 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 974 int ret; 975 u32 val; 976 977 /* 978 * Power domain could have been shut off completely in system deep 979 * sleep, so re-initialize the block here 980 */ 981 ret = bcm_iproc_i2c_init(iproc_i2c); 982 if (ret) 983 return ret; 984 985 /* configure to the desired bus speed */ 986 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 987 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 988 val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 989 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 990 991 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 992 993 return 0; 994 } 995 996 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = { 997 .suspend_late = &bcm_iproc_i2c_suspend, 998 .resume_early = &bcm_iproc_i2c_resume 999 }; 1000 1001 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops) 1002 #else 1003 #define BCM_IPROC_I2C_PM_OPS NULL 1004 #endif /* CONFIG_PM_SLEEP */ 1005 1006 1007 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) 1008 { 1009 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1010 1011 if (iproc_i2c->slave) 1012 return -EBUSY; 1013 1014 if (slave->flags & I2C_CLIENT_TEN) 1015 return -EAFNOSUPPORT; 1016 1017 iproc_i2c->slave = slave; 1018 bcm_iproc_i2c_slave_init(iproc_i2c, false); 1019 return 0; 1020 } 1021 1022 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) 1023 { 1024 u32 tmp; 1025 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1026 1027 if (!iproc_i2c->slave) 1028 return -EINVAL; 1029 1030 iproc_i2c->slave = NULL; 1031 1032 /* disable all slave interrupts */ 1033 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 1034 tmp &= ~(IE_S_ALL_INTERRUPT_MASK << 1035 IE_S_ALL_INTERRUPT_SHIFT); 1036 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp); 1037 1038 /* Erase the slave address programmed */ 1039 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 1040 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 1041 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp); 1042 1043 return 0; 1044 } 1045 1046 static const struct of_device_id bcm_iproc_i2c_of_match[] = { 1047 { 1048 .compatible = "brcm,iproc-i2c", 1049 .data = (int *)IPROC_I2C, 1050 }, { 1051 .compatible = "brcm,iproc-nic-i2c", 1052 .data = (int *)IPROC_I2C_NIC, 1053 }, 1054 { /* sentinel */ } 1055 }; 1056 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); 1057 1058 static struct platform_driver bcm_iproc_i2c_driver = { 1059 .driver = { 1060 .name = "bcm-iproc-i2c", 1061 .of_match_table = bcm_iproc_i2c_of_match, 1062 .pm = BCM_IPROC_I2C_PM_OPS, 1063 }, 1064 .probe = bcm_iproc_i2c_probe, 1065 .remove = bcm_iproc_i2c_remove, 1066 }; 1067 module_platform_driver(bcm_iproc_i2c_driver); 1068 1069 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); 1070 MODULE_DESCRIPTION("Broadcom iProc I2C Driver"); 1071 MODULE_LICENSE("GPL v2"); 1072