1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/i2c.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 24 #define IDM_CTRL_DIRECT_OFFSET 0x00 25 #define CFG_OFFSET 0x00 26 #define CFG_RESET_SHIFT 31 27 #define CFG_EN_SHIFT 30 28 #define CFG_SLAVE_ADDR_0_SHIFT 28 29 #define CFG_M_RETRY_CNT_SHIFT 16 30 #define CFG_M_RETRY_CNT_MASK 0x0f 31 32 #define TIM_CFG_OFFSET 0x04 33 #define TIM_CFG_MODE_400_SHIFT 31 34 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24 35 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f 36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16 37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f 38 39 #define S_CFG_SMBUS_ADDR_OFFSET 0x08 40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31 41 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24 42 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f 43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23 44 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16 45 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f 46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15 47 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8 48 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f 49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7 50 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0 51 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f 52 53 #define M_FIFO_CTRL_OFFSET 0x0c 54 #define M_FIFO_RX_FLUSH_SHIFT 31 55 #define M_FIFO_TX_FLUSH_SHIFT 30 56 #define M_FIFO_RX_CNT_SHIFT 16 57 #define M_FIFO_RX_CNT_MASK 0x7f 58 #define M_FIFO_RX_THLD_SHIFT 8 59 #define M_FIFO_RX_THLD_MASK 0x3f 60 61 #define S_FIFO_CTRL_OFFSET 0x10 62 #define S_FIFO_RX_FLUSH_SHIFT 31 63 #define S_FIFO_TX_FLUSH_SHIFT 30 64 #define S_FIFO_RX_CNT_SHIFT 16 65 #define S_FIFO_RX_CNT_MASK 0x7f 66 #define S_FIFO_RX_THLD_SHIFT 8 67 #define S_FIFO_RX_THLD_MASK 0x3f 68 69 #define M_CMD_OFFSET 0x30 70 #define M_CMD_START_BUSY_SHIFT 31 71 #define M_CMD_STATUS_SHIFT 25 72 #define M_CMD_STATUS_MASK 0x07 73 #define M_CMD_STATUS_SUCCESS 0x0 74 #define M_CMD_STATUS_LOST_ARB 0x1 75 #define M_CMD_STATUS_NACK_ADDR 0x2 76 #define M_CMD_STATUS_NACK_DATA 0x3 77 #define M_CMD_STATUS_TIMEOUT 0x4 78 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5 79 #define M_CMD_STATUS_RX_FIFO_FULL 0x6 80 #define M_CMD_PROTOCOL_SHIFT 9 81 #define M_CMD_PROTOCOL_MASK 0xf 82 #define M_CMD_PROTOCOL_BLK_WR 0x7 83 #define M_CMD_PROTOCOL_BLK_RD 0x8 84 #define M_CMD_PROTOCOL_PROCESS 0xa 85 #define M_CMD_PEC_SHIFT 8 86 #define M_CMD_RD_CNT_SHIFT 0 87 #define M_CMD_RD_CNT_MASK 0xff 88 89 #define S_CMD_OFFSET 0x34 90 #define S_CMD_START_BUSY_SHIFT 31 91 #define S_CMD_STATUS_SHIFT 23 92 #define S_CMD_STATUS_MASK 0x07 93 #define S_CMD_STATUS_SUCCESS 0x0 94 #define S_CMD_STATUS_TIMEOUT 0x5 95 96 #define IE_OFFSET 0x38 97 #define IE_M_RX_FIFO_FULL_SHIFT 31 98 #define IE_M_RX_THLD_SHIFT 30 99 #define IE_M_START_BUSY_SHIFT 28 100 #define IE_M_TX_UNDERRUN_SHIFT 27 101 #define IE_S_RX_FIFO_FULL_SHIFT 26 102 #define IE_S_RX_THLD_SHIFT 25 103 #define IE_S_RX_EVENT_SHIFT 24 104 #define IE_S_START_BUSY_SHIFT 23 105 #define IE_S_TX_UNDERRUN_SHIFT 22 106 #define IE_S_RD_EVENT_SHIFT 21 107 108 #define IS_OFFSET 0x3c 109 #define IS_M_RX_FIFO_FULL_SHIFT 31 110 #define IS_M_RX_THLD_SHIFT 30 111 #define IS_M_START_BUSY_SHIFT 28 112 #define IS_M_TX_UNDERRUN_SHIFT 27 113 #define IS_S_RX_FIFO_FULL_SHIFT 26 114 #define IS_S_RX_THLD_SHIFT 25 115 #define IS_S_RX_EVENT_SHIFT 24 116 #define IS_S_START_BUSY_SHIFT 23 117 #define IS_S_TX_UNDERRUN_SHIFT 22 118 #define IS_S_RD_EVENT_SHIFT 21 119 120 #define M_TX_OFFSET 0x40 121 #define M_TX_WR_STATUS_SHIFT 31 122 #define M_TX_DATA_SHIFT 0 123 #define M_TX_DATA_MASK 0xff 124 125 #define M_RX_OFFSET 0x44 126 #define M_RX_STATUS_SHIFT 30 127 #define M_RX_STATUS_MASK 0x03 128 #define M_RX_PEC_ERR_SHIFT 29 129 #define M_RX_DATA_SHIFT 0 130 #define M_RX_DATA_MASK 0xff 131 132 #define S_TX_OFFSET 0x48 133 #define S_TX_WR_STATUS_SHIFT 31 134 #define S_TX_DATA_SHIFT 0 135 #define S_TX_DATA_MASK 0xff 136 137 #define S_RX_OFFSET 0x4c 138 #define S_RX_STATUS_SHIFT 30 139 #define S_RX_STATUS_MASK 0x03 140 #define S_RX_PEC_ERR_SHIFT 29 141 #define S_RX_DATA_SHIFT 0 142 #define S_RX_DATA_MASK 0xff 143 144 #define I2C_TIMEOUT_MSEC 50000 145 #define M_TX_RX_FIFO_SIZE 64 146 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1) 147 148 #define M_RX_MAX_READ_LEN 255 149 #define M_RX_FIFO_THLD_VALUE 50 150 151 #define IE_M_ALL_INTERRUPT_SHIFT 27 152 #define IE_M_ALL_INTERRUPT_MASK 0x1e 153 154 #define SLAVE_READ_WRITE_BIT_MASK 0x1 155 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1 156 #define SLAVE_MAX_SIZE_TRANSACTION 64 157 #define SLAVE_CLOCK_STRETCH_TIME 25 158 159 #define IE_S_ALL_INTERRUPT_SHIFT 21 160 #define IE_S_ALL_INTERRUPT_MASK 0x3f 161 162 enum i2c_slave_read_status { 163 I2C_SLAVE_RX_FIFO_EMPTY = 0, 164 I2C_SLAVE_RX_START, 165 I2C_SLAVE_RX_DATA, 166 I2C_SLAVE_RX_END, 167 }; 168 169 enum bus_speed_index { 170 I2C_SPD_100K = 0, 171 I2C_SPD_400K, 172 }; 173 174 enum bcm_iproc_i2c_type { 175 IPROC_I2C, 176 IPROC_I2C_NIC 177 }; 178 179 struct bcm_iproc_i2c_dev { 180 struct device *device; 181 enum bcm_iproc_i2c_type type; 182 int irq; 183 184 void __iomem *base; 185 void __iomem *idm_base; 186 187 u32 ape_addr_mask; 188 189 /* lock for indirect access through IDM */ 190 spinlock_t idm_lock; 191 192 struct i2c_adapter adapter; 193 unsigned int bus_speed; 194 195 struct completion done; 196 int xfer_is_done; 197 198 struct i2c_msg *msg; 199 200 struct i2c_client *slave; 201 202 /* bytes that have been transferred */ 203 unsigned int tx_bytes; 204 /* bytes that have been read */ 205 unsigned int rx_bytes; 206 unsigned int thld_bytes; 207 }; 208 209 /* 210 * Can be expanded in the future if more interrupt status bits are utilized 211 */ 212 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ 213 | BIT(IS_M_RX_THLD_SHIFT)) 214 215 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\ 216 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\ 217 | BIT(IS_S_TX_UNDERRUN_SHIFT)) 218 219 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave); 220 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); 221 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 222 bool enable); 223 224 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 225 u32 offset) 226 { 227 u32 val; 228 229 if (iproc_i2c->idm_base) { 230 spin_lock(&iproc_i2c->idm_lock); 231 writel(iproc_i2c->ape_addr_mask, 232 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 233 val = readl(iproc_i2c->base + offset); 234 spin_unlock(&iproc_i2c->idm_lock); 235 } else { 236 val = readl(iproc_i2c->base + offset); 237 } 238 239 return val; 240 } 241 242 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 243 u32 offset, u32 val) 244 { 245 if (iproc_i2c->idm_base) { 246 spin_lock(&iproc_i2c->idm_lock); 247 writel(iproc_i2c->ape_addr_mask, 248 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 249 writel(val, iproc_i2c->base + offset); 250 spin_unlock(&iproc_i2c->idm_lock); 251 } else { 252 writel(val, iproc_i2c->base + offset); 253 } 254 } 255 256 static void bcm_iproc_i2c_slave_init( 257 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) 258 { 259 u32 val; 260 261 if (need_reset) { 262 /* put controller in reset */ 263 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 264 val |= BIT(CFG_RESET_SHIFT); 265 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 266 267 /* wait 100 usec per spec */ 268 udelay(100); 269 270 /* bring controller out of reset */ 271 val &= ~(BIT(CFG_RESET_SHIFT)); 272 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 273 } 274 275 /* flush TX/RX FIFOs */ 276 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); 277 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); 278 279 /* Maximum slave stretch time */ 280 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 281 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); 282 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); 283 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 284 285 /* Configure the slave address */ 286 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 287 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 288 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); 289 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); 290 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val); 291 292 /* clear all pending slave interrupts */ 293 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); 294 295 /* Enable interrupt register to indicate a valid byte in receive fifo */ 296 val = BIT(IE_S_RX_EVENT_SHIFT); 297 /* Enable interrupt register for the Slave BUSY command */ 298 val |= BIT(IE_S_START_BUSY_SHIFT); 299 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 300 } 301 302 static void bcm_iproc_i2c_check_slave_status( 303 struct bcm_iproc_i2c_dev *iproc_i2c) 304 { 305 u32 val; 306 307 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET); 308 /* status is valid only when START_BUSY is cleared after it was set */ 309 if (val & BIT(S_CMD_START_BUSY_SHIFT)) 310 return; 311 312 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; 313 if (val == S_CMD_STATUS_TIMEOUT) { 314 dev_err(iproc_i2c->device, "slave random stretch time timeout\n"); 315 316 /* re-initialize i2c for recovery */ 317 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 318 bcm_iproc_i2c_slave_init(iproc_i2c, true); 319 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 320 } 321 } 322 323 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, 324 u32 status) 325 { 326 u32 val; 327 u8 value, rx_status; 328 329 /* Slave RX byte receive */ 330 if (status & BIT(IS_S_RX_EVENT_SHIFT)) { 331 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); 332 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; 333 if (rx_status == I2C_SLAVE_RX_START) { 334 /* Start of SMBUS for Master write */ 335 i2c_slave_event(iproc_i2c->slave, 336 I2C_SLAVE_WRITE_REQUESTED, &value); 337 338 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); 339 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); 340 i2c_slave_event(iproc_i2c->slave, 341 I2C_SLAVE_WRITE_RECEIVED, &value); 342 } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) { 343 /* Start of SMBUS for Master Read */ 344 i2c_slave_event(iproc_i2c->slave, 345 I2C_SLAVE_READ_REQUESTED, &value); 346 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value); 347 348 val = BIT(S_CMD_START_BUSY_SHIFT); 349 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); 350 351 /* 352 * Enable interrupt for TX FIFO becomes empty and 353 * less than PKT_LENGTH bytes were output on the SMBUS 354 */ 355 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 356 val |= BIT(IE_S_TX_UNDERRUN_SHIFT); 357 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 358 } else { 359 /* Master write other than start */ 360 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); 361 i2c_slave_event(iproc_i2c->slave, 362 I2C_SLAVE_WRITE_RECEIVED, &value); 363 if (rx_status == I2C_SLAVE_RX_END) 364 i2c_slave_event(iproc_i2c->slave, 365 I2C_SLAVE_STOP, &value); 366 } 367 } else if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) { 368 /* Master read other than start */ 369 i2c_slave_event(iproc_i2c->slave, 370 I2C_SLAVE_READ_PROCESSED, &value); 371 372 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value); 373 val = BIT(S_CMD_START_BUSY_SHIFT); 374 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); 375 } 376 377 /* Stop */ 378 if (status & BIT(IS_S_START_BUSY_SHIFT)) { 379 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value); 380 /* 381 * Enable interrupt for TX FIFO becomes empty and 382 * less than PKT_LENGTH bytes were output on the SMBUS 383 */ 384 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 385 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT); 386 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 387 } 388 389 /* clear interrupt status */ 390 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 391 392 bcm_iproc_i2c_check_slave_status(iproc_i2c); 393 return true; 394 } 395 396 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) 397 { 398 struct i2c_msg *msg = iproc_i2c->msg; 399 uint32_t val; 400 401 /* Read valid data from RX FIFO */ 402 while (iproc_i2c->rx_bytes < msg->len) { 403 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET); 404 405 /* rx fifo empty */ 406 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK)) 407 break; 408 409 msg->buf[iproc_i2c->rx_bytes] = 410 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK; 411 iproc_i2c->rx_bytes++; 412 } 413 } 414 415 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) 416 { 417 struct i2c_msg *msg = iproc_i2c->msg; 418 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; 419 unsigned int i; 420 u32 val; 421 422 /* can only fill up to the FIFO size */ 423 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); 424 for (i = 0; i < tx_bytes; i++) { 425 /* start from where we left over */ 426 unsigned int idx = iproc_i2c->tx_bytes + i; 427 428 val = msg->buf[idx]; 429 430 /* mark the last byte */ 431 if (idx == msg->len - 1) { 432 val |= BIT(M_TX_WR_STATUS_SHIFT); 433 434 if (iproc_i2c->irq) { 435 u32 tmp; 436 437 /* 438 * Since this is the last byte, we should now 439 * disable TX FIFO underrun interrupt 440 */ 441 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 442 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); 443 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 444 tmp); 445 } 446 } 447 448 /* load data into TX FIFO */ 449 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 450 } 451 452 /* update number of transferred bytes */ 453 iproc_i2c->tx_bytes += tx_bytes; 454 } 455 456 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) 457 { 458 struct i2c_msg *msg = iproc_i2c->msg; 459 u32 bytes_left, val; 460 461 bcm_iproc_i2c_read_valid_bytes(iproc_i2c); 462 bytes_left = msg->len - iproc_i2c->rx_bytes; 463 if (bytes_left == 0) { 464 if (iproc_i2c->irq) { 465 /* finished reading all data, disable rx thld event */ 466 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 467 val &= ~BIT(IS_M_RX_THLD_SHIFT); 468 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 469 } 470 } else if (bytes_left < iproc_i2c->thld_bytes) { 471 /* set bytes left as threshold */ 472 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 473 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 474 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); 475 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 476 iproc_i2c->thld_bytes = bytes_left; 477 } 478 /* 479 * bytes_left >= iproc_i2c->thld_bytes, 480 * hence no need to change the THRESHOLD SET. 481 * It will remain as iproc_i2c->thld_bytes itself 482 */ 483 } 484 485 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, 486 u32 status) 487 { 488 /* TX FIFO is empty and we have more data to send */ 489 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) 490 bcm_iproc_i2c_send(iproc_i2c); 491 492 /* RX FIFO threshold is reached and data needs to be read out */ 493 if (status & BIT(IS_M_RX_THLD_SHIFT)) 494 bcm_iproc_i2c_read(iproc_i2c); 495 496 /* transfer is done */ 497 if (status & BIT(IS_M_START_BUSY_SHIFT)) { 498 iproc_i2c->xfer_is_done = 1; 499 if (iproc_i2c->irq) 500 complete(&iproc_i2c->done); 501 } 502 } 503 504 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) 505 { 506 struct bcm_iproc_i2c_dev *iproc_i2c = data; 507 u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET); 508 bool ret; 509 u32 sl_status = status & ISR_MASK_SLAVE; 510 511 if (sl_status) { 512 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status); 513 if (ret) 514 return IRQ_HANDLED; 515 else 516 return IRQ_NONE; 517 } 518 519 status &= ISR_MASK; 520 if (!status) 521 return IRQ_NONE; 522 523 /* process all master based events */ 524 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 525 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 526 527 return IRQ_HANDLED; 528 } 529 530 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) 531 { 532 u32 val; 533 534 /* put controller in reset */ 535 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 536 val |= BIT(CFG_RESET_SHIFT); 537 val &= ~(BIT(CFG_EN_SHIFT)); 538 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 539 540 /* wait 100 usec per spec */ 541 udelay(100); 542 543 /* bring controller out of reset */ 544 val &= ~(BIT(CFG_RESET_SHIFT)); 545 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 546 547 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ 548 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); 549 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 550 /* disable all interrupts */ 551 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 552 val &= ~(IE_M_ALL_INTERRUPT_MASK << 553 IE_M_ALL_INTERRUPT_SHIFT); 554 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 555 556 /* clear all pending interrupts */ 557 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff); 558 559 return 0; 560 } 561 562 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 563 bool enable) 564 { 565 u32 val; 566 567 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 568 if (enable) 569 val |= BIT(CFG_EN_SHIFT); 570 else 571 val &= ~BIT(CFG_EN_SHIFT); 572 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 573 } 574 575 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, 576 struct i2c_msg *msg) 577 { 578 u32 val; 579 580 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET); 581 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; 582 583 switch (val) { 584 case M_CMD_STATUS_SUCCESS: 585 return 0; 586 587 case M_CMD_STATUS_LOST_ARB: 588 dev_dbg(iproc_i2c->device, "lost bus arbitration\n"); 589 return -EAGAIN; 590 591 case M_CMD_STATUS_NACK_ADDR: 592 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr); 593 return -ENXIO; 594 595 case M_CMD_STATUS_NACK_DATA: 596 dev_dbg(iproc_i2c->device, "NAK data\n"); 597 return -ENXIO; 598 599 case M_CMD_STATUS_TIMEOUT: 600 dev_dbg(iproc_i2c->device, "bus timeout\n"); 601 return -ETIMEDOUT; 602 603 case M_CMD_STATUS_FIFO_UNDERRUN: 604 dev_dbg(iproc_i2c->device, "FIFO under-run\n"); 605 return -ENXIO; 606 607 case M_CMD_STATUS_RX_FIFO_FULL: 608 dev_dbg(iproc_i2c->device, "RX FIFO full\n"); 609 return -ETIMEDOUT; 610 611 default: 612 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); 613 614 /* re-initialize i2c for recovery */ 615 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 616 bcm_iproc_i2c_init(iproc_i2c); 617 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 618 619 return -EIO; 620 } 621 } 622 623 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, 624 struct i2c_msg *msg, 625 u32 cmd) 626 { 627 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); 628 u32 val, status; 629 int ret; 630 631 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd); 632 633 if (iproc_i2c->irq) { 634 time_left = wait_for_completion_timeout(&iproc_i2c->done, 635 time_left); 636 /* disable all interrupts */ 637 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 638 /* read it back to flush the write */ 639 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 640 /* make sure the interrupt handler isn't running */ 641 synchronize_irq(iproc_i2c->irq); 642 643 } else { /* polling mode */ 644 unsigned long timeout = jiffies + time_left; 645 646 do { 647 status = iproc_i2c_rd_reg(iproc_i2c, 648 IS_OFFSET) & ISR_MASK; 649 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 650 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 651 652 if (time_after(jiffies, timeout)) { 653 time_left = 0; 654 break; 655 } 656 657 cpu_relax(); 658 cond_resched(); 659 } while (!iproc_i2c->xfer_is_done); 660 } 661 662 if (!time_left && !iproc_i2c->xfer_is_done) { 663 dev_err(iproc_i2c->device, "transaction timed out\n"); 664 665 /* flush both TX/RX FIFOs */ 666 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 667 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 668 return -ETIMEDOUT; 669 } 670 671 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); 672 if (ret) { 673 /* flush both TX/RX FIFOs */ 674 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 675 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 676 return ret; 677 } 678 679 return 0; 680 } 681 682 /* 683 * If 'process_call' is true, then this is a multi-msg transfer that requires 684 * a repeated start between the messages. 685 * More specifically, it must be a write (reg) followed by a read (data). 686 * The i2c quirks are set to enforce this rule. 687 */ 688 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c, 689 struct i2c_msg *msgs, bool process_call) 690 { 691 int i; 692 u8 addr; 693 u32 val, tmp, val_intr_en; 694 unsigned int tx_bytes; 695 struct i2c_msg *msg = &msgs[0]; 696 697 /* check if bus is busy */ 698 if (!!(iproc_i2c_rd_reg(iproc_i2c, 699 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) { 700 dev_warn(iproc_i2c->device, "bus is busy\n"); 701 return -EBUSY; 702 } 703 704 iproc_i2c->msg = msg; 705 706 /* format and load slave address into the TX FIFO */ 707 addr = i2c_8bit_addr_from_msg(msg); 708 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr); 709 710 /* 711 * For a write transaction, load data into the TX FIFO. Only allow 712 * loading up to TX FIFO size - 1 bytes of data since the first byte 713 * has been used up by the slave address 714 */ 715 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1); 716 if (!(msg->flags & I2C_M_RD)) { 717 for (i = 0; i < tx_bytes; i++) { 718 val = msg->buf[i]; 719 720 /* mark the last byte */ 721 if (!process_call && (i == msg->len - 1)) 722 val |= 1 << M_TX_WR_STATUS_SHIFT; 723 724 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 725 } 726 iproc_i2c->tx_bytes = tx_bytes; 727 } 728 729 /* Process the read message if this is process call */ 730 if (process_call) { 731 msg++; 732 iproc_i2c->msg = msg; /* point to second msg */ 733 734 /* 735 * The last byte to be sent out should be a slave 736 * address with read operation 737 */ 738 addr = i2c_8bit_addr_from_msg(msg); 739 /* mark it the last byte out */ 740 val = addr | (1 << M_TX_WR_STATUS_SHIFT); 741 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 742 } 743 744 /* mark as incomplete before starting the transaction */ 745 if (iproc_i2c->irq) 746 reinit_completion(&iproc_i2c->done); 747 748 iproc_i2c->xfer_is_done = 0; 749 750 /* 751 * Enable the "start busy" interrupt, which will be triggered after the 752 * transaction is done, i.e., the internal start_busy bit, transitions 753 * from 1 to 0. 754 */ 755 val_intr_en = BIT(IE_M_START_BUSY_SHIFT); 756 757 /* 758 * If TX data size is larger than the TX FIFO, need to enable TX 759 * underrun interrupt, which will be triggerred when the TX FIFO is 760 * empty. When that happens we can then pump more data into the FIFO 761 */ 762 if (!process_call && !(msg->flags & I2C_M_RD) && 763 msg->len > iproc_i2c->tx_bytes) 764 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); 765 766 /* 767 * Now we can activate the transfer. For a read operation, specify the 768 * number of bytes to read 769 */ 770 val = BIT(M_CMD_START_BUSY_SHIFT); 771 if (msg->flags & I2C_M_RD) { 772 u32 protocol; 773 774 iproc_i2c->rx_bytes = 0; 775 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) 776 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE; 777 else 778 iproc_i2c->thld_bytes = msg->len; 779 780 /* set threshold value */ 781 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 782 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 783 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT; 784 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp); 785 786 /* enable the RX threshold interrupt */ 787 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); 788 789 protocol = process_call ? 790 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD; 791 792 val |= (protocol << M_CMD_PROTOCOL_SHIFT) | 793 (msg->len << M_CMD_RD_CNT_SHIFT); 794 } else { 795 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); 796 } 797 798 if (iproc_i2c->irq) 799 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en); 800 801 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val); 802 } 803 804 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, 805 struct i2c_msg msgs[], int num) 806 { 807 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter); 808 bool process_call = false; 809 int ret; 810 811 if (num == 2) { 812 /* Repeated start, use process call */ 813 process_call = true; 814 if (msgs[1].flags & I2C_M_NOSTART) { 815 dev_err(iproc_i2c->device, "Invalid repeated start\n"); 816 return -EOPNOTSUPP; 817 } 818 } 819 820 ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call); 821 if (ret) { 822 dev_dbg(iproc_i2c->device, "xfer failed\n"); 823 return ret; 824 } 825 826 return num; 827 } 828 829 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) 830 { 831 u32 val; 832 833 /* We do not support the SMBUS Quick command */ 834 val = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 835 836 if (adap->algo->reg_slave) 837 val |= I2C_FUNC_SLAVE; 838 839 return val; 840 } 841 842 static struct i2c_algorithm bcm_iproc_algo = { 843 .master_xfer = bcm_iproc_i2c_xfer, 844 .functionality = bcm_iproc_i2c_functionality, 845 .reg_slave = bcm_iproc_i2c_reg_slave, 846 .unreg_slave = bcm_iproc_i2c_unreg_slave, 847 }; 848 849 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { 850 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 851 .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE, 852 .max_read_len = M_RX_MAX_READ_LEN, 853 }; 854 855 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) 856 { 857 unsigned int bus_speed; 858 u32 val; 859 int ret = of_property_read_u32(iproc_i2c->device->of_node, 860 "clock-frequency", &bus_speed); 861 if (ret < 0) { 862 dev_info(iproc_i2c->device, 863 "unable to interpret clock-frequency DT property\n"); 864 bus_speed = I2C_MAX_STANDARD_MODE_FREQ; 865 } 866 867 if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) { 868 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n", 869 bus_speed); 870 dev_err(iproc_i2c->device, 871 "valid speeds are 100khz and 400khz\n"); 872 return -EINVAL; 873 } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) { 874 bus_speed = I2C_MAX_STANDARD_MODE_FREQ; 875 } else { 876 bus_speed = I2C_MAX_FAST_MODE_FREQ; 877 } 878 879 iproc_i2c->bus_speed = bus_speed; 880 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 881 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 882 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT; 883 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 884 885 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed); 886 887 return 0; 888 } 889 890 static int bcm_iproc_i2c_probe(struct platform_device *pdev) 891 { 892 int irq, ret = 0; 893 struct bcm_iproc_i2c_dev *iproc_i2c; 894 struct i2c_adapter *adap; 895 struct resource *res; 896 897 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c), 898 GFP_KERNEL); 899 if (!iproc_i2c) 900 return -ENOMEM; 901 902 platform_set_drvdata(pdev, iproc_i2c); 903 iproc_i2c->device = &pdev->dev; 904 iproc_i2c->type = 905 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev); 906 init_completion(&iproc_i2c->done); 907 908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 909 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res); 910 if (IS_ERR(iproc_i2c->base)) 911 return PTR_ERR(iproc_i2c->base); 912 913 if (iproc_i2c->type == IPROC_I2C_NIC) { 914 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 915 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device, 916 res); 917 if (IS_ERR(iproc_i2c->idm_base)) 918 return PTR_ERR(iproc_i2c->idm_base); 919 920 ret = of_property_read_u32(iproc_i2c->device->of_node, 921 "brcm,ape-hsls-addr-mask", 922 &iproc_i2c->ape_addr_mask); 923 if (ret < 0) { 924 dev_err(iproc_i2c->device, 925 "'brcm,ape-hsls-addr-mask' missing\n"); 926 return -EINVAL; 927 } 928 929 spin_lock_init(&iproc_i2c->idm_lock); 930 931 /* no slave support */ 932 bcm_iproc_algo.reg_slave = NULL; 933 bcm_iproc_algo.unreg_slave = NULL; 934 } 935 936 ret = bcm_iproc_i2c_init(iproc_i2c); 937 if (ret) 938 return ret; 939 940 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c); 941 if (ret) 942 return ret; 943 944 irq = platform_get_irq(pdev, 0); 945 if (irq > 0) { 946 ret = devm_request_irq(iproc_i2c->device, irq, 947 bcm_iproc_i2c_isr, 0, pdev->name, 948 iproc_i2c); 949 if (ret < 0) { 950 dev_err(iproc_i2c->device, 951 "unable to request irq %i\n", irq); 952 return ret; 953 } 954 955 iproc_i2c->irq = irq; 956 } else { 957 dev_warn(iproc_i2c->device, 958 "no irq resource, falling back to poll mode\n"); 959 } 960 961 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 962 963 adap = &iproc_i2c->adapter; 964 i2c_set_adapdata(adap, iproc_i2c); 965 snprintf(adap->name, sizeof(adap->name), 966 "Broadcom iProc (%s)", 967 of_node_full_name(iproc_i2c->device->of_node)); 968 adap->algo = &bcm_iproc_algo; 969 adap->quirks = &bcm_iproc_i2c_quirks; 970 adap->dev.parent = &pdev->dev; 971 adap->dev.of_node = pdev->dev.of_node; 972 973 return i2c_add_adapter(adap); 974 } 975 976 static int bcm_iproc_i2c_remove(struct platform_device *pdev) 977 { 978 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 979 980 if (iproc_i2c->irq) { 981 /* 982 * Make sure there's no pending interrupt when we remove the 983 * adapter 984 */ 985 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 986 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 987 synchronize_irq(iproc_i2c->irq); 988 } 989 990 i2c_del_adapter(&iproc_i2c->adapter); 991 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 992 993 return 0; 994 } 995 996 #ifdef CONFIG_PM_SLEEP 997 998 static int bcm_iproc_i2c_suspend(struct device *dev) 999 { 1000 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 1001 1002 if (iproc_i2c->irq) { 1003 /* 1004 * Make sure there's no pending interrupt when we go into 1005 * suspend 1006 */ 1007 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 1008 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 1009 synchronize_irq(iproc_i2c->irq); 1010 } 1011 1012 /* now disable the controller */ 1013 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 1014 1015 return 0; 1016 } 1017 1018 static int bcm_iproc_i2c_resume(struct device *dev) 1019 { 1020 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 1021 int ret; 1022 u32 val; 1023 1024 /* 1025 * Power domain could have been shut off completely in system deep 1026 * sleep, so re-initialize the block here 1027 */ 1028 ret = bcm_iproc_i2c_init(iproc_i2c); 1029 if (ret) 1030 return ret; 1031 1032 /* configure to the desired bus speed */ 1033 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 1034 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 1035 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT; 1036 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 1037 1038 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 1039 1040 return 0; 1041 } 1042 1043 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = { 1044 .suspend_late = &bcm_iproc_i2c_suspend, 1045 .resume_early = &bcm_iproc_i2c_resume 1046 }; 1047 1048 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops) 1049 #else 1050 #define BCM_IPROC_I2C_PM_OPS NULL 1051 #endif /* CONFIG_PM_SLEEP */ 1052 1053 1054 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) 1055 { 1056 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1057 1058 if (iproc_i2c->slave) 1059 return -EBUSY; 1060 1061 if (slave->flags & I2C_CLIENT_TEN) 1062 return -EAFNOSUPPORT; 1063 1064 iproc_i2c->slave = slave; 1065 bcm_iproc_i2c_slave_init(iproc_i2c, false); 1066 return 0; 1067 } 1068 1069 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) 1070 { 1071 u32 tmp; 1072 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1073 1074 if (!iproc_i2c->slave) 1075 return -EINVAL; 1076 1077 iproc_i2c->slave = NULL; 1078 1079 /* disable all slave interrupts */ 1080 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 1081 tmp &= ~(IE_S_ALL_INTERRUPT_MASK << 1082 IE_S_ALL_INTERRUPT_SHIFT); 1083 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp); 1084 1085 /* Erase the slave address programmed */ 1086 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 1087 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 1088 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp); 1089 1090 return 0; 1091 } 1092 1093 static const struct of_device_id bcm_iproc_i2c_of_match[] = { 1094 { 1095 .compatible = "brcm,iproc-i2c", 1096 .data = (int *)IPROC_I2C, 1097 }, { 1098 .compatible = "brcm,iproc-nic-i2c", 1099 .data = (int *)IPROC_I2C_NIC, 1100 }, 1101 { /* sentinel */ } 1102 }; 1103 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); 1104 1105 static struct platform_driver bcm_iproc_i2c_driver = { 1106 .driver = { 1107 .name = "bcm-iproc-i2c", 1108 .of_match_table = bcm_iproc_i2c_of_match, 1109 .pm = BCM_IPROC_I2C_PM_OPS, 1110 }, 1111 .probe = bcm_iproc_i2c_probe, 1112 .remove = bcm_iproc_i2c_remove, 1113 }; 1114 module_platform_driver(bcm_iproc_i2c_driver); 1115 1116 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); 1117 MODULE_DESCRIPTION("Broadcom iProc I2C Driver"); 1118 MODULE_LICENSE("GPL v2"); 1119