1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/i2c.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/of_device.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 24 #define IDM_CTRL_DIRECT_OFFSET 0x00 25 #define CFG_OFFSET 0x00 26 #define CFG_RESET_SHIFT 31 27 #define CFG_EN_SHIFT 30 28 #define CFG_SLAVE_ADDR_0_SHIFT 28 29 #define CFG_M_RETRY_CNT_SHIFT 16 30 #define CFG_M_RETRY_CNT_MASK 0x0f 31 32 #define TIM_CFG_OFFSET 0x04 33 #define TIM_CFG_MODE_400_SHIFT 31 34 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24 35 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f 36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16 37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f 38 39 #define S_CFG_SMBUS_ADDR_OFFSET 0x08 40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31 41 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24 42 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f 43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23 44 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16 45 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f 46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15 47 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8 48 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f 49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7 50 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0 51 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f 52 53 #define M_FIFO_CTRL_OFFSET 0x0c 54 #define M_FIFO_RX_FLUSH_SHIFT 31 55 #define M_FIFO_TX_FLUSH_SHIFT 30 56 #define M_FIFO_RX_CNT_SHIFT 16 57 #define M_FIFO_RX_CNT_MASK 0x7f 58 #define M_FIFO_RX_THLD_SHIFT 8 59 #define M_FIFO_RX_THLD_MASK 0x3f 60 61 #define S_FIFO_CTRL_OFFSET 0x10 62 #define S_FIFO_RX_FLUSH_SHIFT 31 63 #define S_FIFO_TX_FLUSH_SHIFT 30 64 #define S_FIFO_RX_CNT_SHIFT 16 65 #define S_FIFO_RX_CNT_MASK 0x7f 66 #define S_FIFO_RX_THLD_SHIFT 8 67 #define S_FIFO_RX_THLD_MASK 0x3f 68 69 #define M_CMD_OFFSET 0x30 70 #define M_CMD_START_BUSY_SHIFT 31 71 #define M_CMD_STATUS_SHIFT 25 72 #define M_CMD_STATUS_MASK 0x07 73 #define M_CMD_STATUS_SUCCESS 0x0 74 #define M_CMD_STATUS_LOST_ARB 0x1 75 #define M_CMD_STATUS_NACK_ADDR 0x2 76 #define M_CMD_STATUS_NACK_DATA 0x3 77 #define M_CMD_STATUS_TIMEOUT 0x4 78 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5 79 #define M_CMD_STATUS_RX_FIFO_FULL 0x6 80 #define M_CMD_PROTOCOL_SHIFT 9 81 #define M_CMD_PROTOCOL_MASK 0xf 82 #define M_CMD_PROTOCOL_BLK_WR 0x7 83 #define M_CMD_PROTOCOL_BLK_RD 0x8 84 #define M_CMD_PEC_SHIFT 8 85 #define M_CMD_RD_CNT_SHIFT 0 86 #define M_CMD_RD_CNT_MASK 0xff 87 88 #define S_CMD_OFFSET 0x34 89 #define S_CMD_START_BUSY_SHIFT 31 90 #define S_CMD_STATUS_SHIFT 23 91 #define S_CMD_STATUS_MASK 0x07 92 #define S_CMD_STATUS_SUCCESS 0x0 93 #define S_CMD_STATUS_TIMEOUT 0x5 94 95 #define IE_OFFSET 0x38 96 #define IE_M_RX_FIFO_FULL_SHIFT 31 97 #define IE_M_RX_THLD_SHIFT 30 98 #define IE_M_START_BUSY_SHIFT 28 99 #define IE_M_TX_UNDERRUN_SHIFT 27 100 #define IE_S_RX_FIFO_FULL_SHIFT 26 101 #define IE_S_RX_THLD_SHIFT 25 102 #define IE_S_RX_EVENT_SHIFT 24 103 #define IE_S_START_BUSY_SHIFT 23 104 #define IE_S_TX_UNDERRUN_SHIFT 22 105 #define IE_S_RD_EVENT_SHIFT 21 106 107 #define IS_OFFSET 0x3c 108 #define IS_M_RX_FIFO_FULL_SHIFT 31 109 #define IS_M_RX_THLD_SHIFT 30 110 #define IS_M_START_BUSY_SHIFT 28 111 #define IS_M_TX_UNDERRUN_SHIFT 27 112 #define IS_S_RX_FIFO_FULL_SHIFT 26 113 #define IS_S_RX_THLD_SHIFT 25 114 #define IS_S_RX_EVENT_SHIFT 24 115 #define IS_S_START_BUSY_SHIFT 23 116 #define IS_S_TX_UNDERRUN_SHIFT 22 117 #define IS_S_RD_EVENT_SHIFT 21 118 119 #define M_TX_OFFSET 0x40 120 #define M_TX_WR_STATUS_SHIFT 31 121 #define M_TX_DATA_SHIFT 0 122 #define M_TX_DATA_MASK 0xff 123 124 #define M_RX_OFFSET 0x44 125 #define M_RX_STATUS_SHIFT 30 126 #define M_RX_STATUS_MASK 0x03 127 #define M_RX_PEC_ERR_SHIFT 29 128 #define M_RX_DATA_SHIFT 0 129 #define M_RX_DATA_MASK 0xff 130 131 #define S_TX_OFFSET 0x48 132 #define S_TX_WR_STATUS_SHIFT 31 133 #define S_TX_DATA_SHIFT 0 134 #define S_TX_DATA_MASK 0xff 135 136 #define S_RX_OFFSET 0x4c 137 #define S_RX_STATUS_SHIFT 30 138 #define S_RX_STATUS_MASK 0x03 139 #define S_RX_PEC_ERR_SHIFT 29 140 #define S_RX_DATA_SHIFT 0 141 #define S_RX_DATA_MASK 0xff 142 143 #define I2C_TIMEOUT_MSEC 50000 144 #define M_TX_RX_FIFO_SIZE 64 145 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1) 146 147 #define M_RX_MAX_READ_LEN 255 148 #define M_RX_FIFO_THLD_VALUE 50 149 150 #define IE_M_ALL_INTERRUPT_SHIFT 27 151 #define IE_M_ALL_INTERRUPT_MASK 0x1e 152 153 #define SLAVE_READ_WRITE_BIT_MASK 0x1 154 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1 155 #define SLAVE_MAX_SIZE_TRANSACTION 64 156 #define SLAVE_CLOCK_STRETCH_TIME 25 157 158 #define IE_S_ALL_INTERRUPT_SHIFT 21 159 #define IE_S_ALL_INTERRUPT_MASK 0x3f 160 161 enum i2c_slave_read_status { 162 I2C_SLAVE_RX_FIFO_EMPTY = 0, 163 I2C_SLAVE_RX_START, 164 I2C_SLAVE_RX_DATA, 165 I2C_SLAVE_RX_END, 166 }; 167 168 enum i2c_slave_xfer_dir { 169 I2C_SLAVE_DIR_READ = 0, 170 I2C_SLAVE_DIR_WRITE, 171 I2C_SLAVE_DIR_NONE, 172 }; 173 174 enum bus_speed_index { 175 I2C_SPD_100K = 0, 176 I2C_SPD_400K, 177 }; 178 179 enum bcm_iproc_i2c_type { 180 IPROC_I2C, 181 IPROC_I2C_NIC 182 }; 183 184 struct bcm_iproc_i2c_dev { 185 struct device *device; 186 enum bcm_iproc_i2c_type type; 187 int irq; 188 189 void __iomem *base; 190 void __iomem *idm_base; 191 192 u32 ape_addr_mask; 193 194 /* lock for indirect access through IDM */ 195 spinlock_t idm_lock; 196 197 struct i2c_adapter adapter; 198 unsigned int bus_speed; 199 200 struct completion done; 201 int xfer_is_done; 202 203 struct i2c_msg *msg; 204 205 struct i2c_client *slave; 206 enum i2c_slave_xfer_dir xfer_dir; 207 208 /* bytes that have been transferred */ 209 unsigned int tx_bytes; 210 /* bytes that have been read */ 211 unsigned int rx_bytes; 212 unsigned int thld_bytes; 213 }; 214 215 /* 216 * Can be expanded in the future if more interrupt status bits are utilized 217 */ 218 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\ 219 | BIT(IS_M_RX_THLD_SHIFT)) 220 221 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\ 222 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)) 223 224 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave); 225 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave); 226 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 227 bool enable); 228 229 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 230 u32 offset) 231 { 232 u32 val; 233 234 if (iproc_i2c->idm_base) { 235 spin_lock(&iproc_i2c->idm_lock); 236 writel(iproc_i2c->ape_addr_mask, 237 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 238 val = readl(iproc_i2c->base + offset); 239 spin_unlock(&iproc_i2c->idm_lock); 240 } else { 241 val = readl(iproc_i2c->base + offset); 242 } 243 244 return val; 245 } 246 247 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c, 248 u32 offset, u32 val) 249 { 250 if (iproc_i2c->idm_base) { 251 spin_lock(&iproc_i2c->idm_lock); 252 writel(iproc_i2c->ape_addr_mask, 253 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET); 254 writel(val, iproc_i2c->base + offset); 255 spin_unlock(&iproc_i2c->idm_lock); 256 } else { 257 writel(val, iproc_i2c->base + offset); 258 } 259 } 260 261 static void bcm_iproc_i2c_slave_init( 262 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) 263 { 264 u32 val; 265 266 if (need_reset) { 267 /* put controller in reset */ 268 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 269 val |= BIT(CFG_RESET_SHIFT); 270 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 271 272 /* wait 100 usec per spec */ 273 udelay(100); 274 275 /* bring controller out of reset */ 276 val &= ~(BIT(CFG_RESET_SHIFT)); 277 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 278 } 279 280 /* flush TX/RX FIFOs */ 281 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); 282 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val); 283 284 /* Maximum slave stretch time */ 285 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 286 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT); 287 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT); 288 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 289 290 /* Configure the slave address */ 291 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 292 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 293 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT); 294 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT); 295 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val); 296 297 /* clear all pending slave interrupts */ 298 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE); 299 300 /* Enable interrupt register for any READ event */ 301 val = BIT(IE_S_RD_EVENT_SHIFT); 302 /* Enable interrupt register to indicate a valid byte in receive fifo */ 303 val |= BIT(IE_S_RX_EVENT_SHIFT); 304 /* Enable interrupt register for the Slave BUSY command */ 305 val |= BIT(IE_S_START_BUSY_SHIFT); 306 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 307 308 iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE; 309 } 310 311 static void bcm_iproc_i2c_check_slave_status( 312 struct bcm_iproc_i2c_dev *iproc_i2c) 313 { 314 u32 val; 315 316 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET); 317 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK; 318 319 if (val == S_CMD_STATUS_TIMEOUT) { 320 dev_err(iproc_i2c->device, "slave random stretch time timeout\n"); 321 322 /* re-initialize i2c for recovery */ 323 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 324 bcm_iproc_i2c_slave_init(iproc_i2c, true); 325 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 326 } 327 } 328 329 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c, 330 u32 status) 331 { 332 u8 value; 333 u32 val; 334 u32 rd_status; 335 u32 tmp; 336 337 /* Start of transaction. check address and populate the direction */ 338 if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) { 339 tmp = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); 340 rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; 341 /* This condition checks whether the request is a new request */ 342 if (((rd_status == I2C_SLAVE_RX_START) && 343 (status & BIT(IS_S_RX_EVENT_SHIFT))) || 344 ((rd_status == I2C_SLAVE_RX_END) && 345 (status & BIT(IS_S_RD_EVENT_SHIFT)))) { 346 347 /* Last bit is W/R bit. 348 * If 1 then its a read request(by master). 349 */ 350 iproc_i2c->xfer_dir = tmp & SLAVE_READ_WRITE_BIT_MASK; 351 if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE) 352 i2c_slave_event(iproc_i2c->slave, 353 I2C_SLAVE_READ_REQUESTED, &value); 354 else 355 i2c_slave_event(iproc_i2c->slave, 356 I2C_SLAVE_WRITE_REQUESTED, &value); 357 } 358 } 359 360 /* read request from master */ 361 if ((status & BIT(IS_S_RD_EVENT_SHIFT)) && 362 (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) { 363 i2c_slave_event(iproc_i2c->slave, 364 I2C_SLAVE_READ_PROCESSED, &value); 365 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value); 366 367 val = BIT(S_CMD_START_BUSY_SHIFT); 368 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val); 369 } 370 371 /* write request from master */ 372 if ((status & BIT(IS_S_RX_EVENT_SHIFT)) && 373 (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) { 374 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET); 375 /* Its a write request by Master to Slave. 376 * We read data present in receive FIFO 377 */ 378 value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK); 379 i2c_slave_event(iproc_i2c->slave, 380 I2C_SLAVE_WRITE_RECEIVED, &value); 381 382 /* check the status for the last byte of the transaction */ 383 rd_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK; 384 if (rd_status == I2C_SLAVE_RX_END) 385 iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE; 386 387 dev_dbg(iproc_i2c->device, "\nread value = 0x%x\n", value); 388 } 389 390 /* Stop */ 391 if (status & BIT(IS_S_START_BUSY_SHIFT)) { 392 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value); 393 iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE; 394 } 395 396 /* clear interrupt status */ 397 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 398 399 bcm_iproc_i2c_check_slave_status(iproc_i2c); 400 return true; 401 } 402 403 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c) 404 { 405 struct i2c_msg *msg = iproc_i2c->msg; 406 407 /* Read valid data from RX FIFO */ 408 while (iproc_i2c->rx_bytes < msg->len) { 409 if (!((iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET) >> M_FIFO_RX_CNT_SHIFT) 410 & M_FIFO_RX_CNT_MASK)) 411 break; 412 413 msg->buf[iproc_i2c->rx_bytes] = 414 (iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET) >> 415 M_RX_DATA_SHIFT) & M_RX_DATA_MASK; 416 iproc_i2c->rx_bytes++; 417 } 418 } 419 420 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c) 421 { 422 struct i2c_msg *msg = iproc_i2c->msg; 423 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes; 424 unsigned int i; 425 u32 val; 426 427 /* can only fill up to the FIFO size */ 428 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE); 429 for (i = 0; i < tx_bytes; i++) { 430 /* start from where we left over */ 431 unsigned int idx = iproc_i2c->tx_bytes + i; 432 433 val = msg->buf[idx]; 434 435 /* mark the last byte */ 436 if (idx == msg->len - 1) { 437 val |= BIT(M_TX_WR_STATUS_SHIFT); 438 439 if (iproc_i2c->irq) { 440 u32 tmp; 441 442 /* 443 * Since this is the last byte, we should now 444 * disable TX FIFO underrun interrupt 445 */ 446 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 447 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT); 448 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 449 tmp); 450 } 451 } 452 453 /* load data into TX FIFO */ 454 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 455 } 456 457 /* update number of transferred bytes */ 458 iproc_i2c->tx_bytes += tx_bytes; 459 } 460 461 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c) 462 { 463 struct i2c_msg *msg = iproc_i2c->msg; 464 u32 bytes_left, val; 465 466 bcm_iproc_i2c_read_valid_bytes(iproc_i2c); 467 bytes_left = msg->len - iproc_i2c->rx_bytes; 468 if (bytes_left == 0) { 469 if (iproc_i2c->irq) { 470 /* finished reading all data, disable rx thld event */ 471 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 472 val &= ~BIT(IS_M_RX_THLD_SHIFT); 473 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 474 } 475 } else if (bytes_left < iproc_i2c->thld_bytes) { 476 /* set bytes left as threshold */ 477 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 478 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 479 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT); 480 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 481 iproc_i2c->thld_bytes = bytes_left; 482 } 483 /* 484 * bytes_left >= iproc_i2c->thld_bytes, 485 * hence no need to change the THRESHOLD SET. 486 * It will remain as iproc_i2c->thld_bytes itself 487 */ 488 } 489 490 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c, 491 u32 status) 492 { 493 /* TX FIFO is empty and we have more data to send */ 494 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT)) 495 bcm_iproc_i2c_send(iproc_i2c); 496 497 /* RX FIFO threshold is reached and data needs to be read out */ 498 if (status & BIT(IS_M_RX_THLD_SHIFT)) 499 bcm_iproc_i2c_read(iproc_i2c); 500 501 /* transfer is done */ 502 if (status & BIT(IS_M_START_BUSY_SHIFT)) { 503 iproc_i2c->xfer_is_done = 1; 504 if (iproc_i2c->irq) 505 complete(&iproc_i2c->done); 506 } 507 } 508 509 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data) 510 { 511 struct bcm_iproc_i2c_dev *iproc_i2c = data; 512 u32 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET); 513 bool ret; 514 u32 sl_status = status & ISR_MASK_SLAVE; 515 516 if (sl_status) { 517 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status); 518 if (ret) 519 return IRQ_HANDLED; 520 else 521 return IRQ_NONE; 522 } 523 524 status &= ISR_MASK; 525 if (!status) 526 return IRQ_NONE; 527 528 /* process all master based events */ 529 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 530 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 531 532 return IRQ_HANDLED; 533 } 534 535 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) 536 { 537 u32 val; 538 539 /* put controller in reset */ 540 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 541 val |= BIT(CFG_RESET_SHIFT); 542 val &= ~(BIT(CFG_EN_SHIFT)); 543 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 544 545 /* wait 100 usec per spec */ 546 udelay(100); 547 548 /* bring controller out of reset */ 549 val &= ~(BIT(CFG_RESET_SHIFT)); 550 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 551 552 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ 553 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); 554 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 555 /* disable all interrupts */ 556 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 557 val &= ~(IE_M_ALL_INTERRUPT_MASK << 558 IE_M_ALL_INTERRUPT_SHIFT); 559 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val); 560 561 /* clear all pending interrupts */ 562 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff); 563 564 return 0; 565 } 566 567 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c, 568 bool enable) 569 { 570 u32 val; 571 572 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET); 573 if (enable) 574 val |= BIT(CFG_EN_SHIFT); 575 else 576 val &= ~BIT(CFG_EN_SHIFT); 577 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val); 578 } 579 580 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c, 581 struct i2c_msg *msg) 582 { 583 u32 val; 584 585 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET); 586 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK; 587 588 switch (val) { 589 case M_CMD_STATUS_SUCCESS: 590 return 0; 591 592 case M_CMD_STATUS_LOST_ARB: 593 dev_dbg(iproc_i2c->device, "lost bus arbitration\n"); 594 return -EAGAIN; 595 596 case M_CMD_STATUS_NACK_ADDR: 597 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr); 598 return -ENXIO; 599 600 case M_CMD_STATUS_NACK_DATA: 601 dev_dbg(iproc_i2c->device, "NAK data\n"); 602 return -ENXIO; 603 604 case M_CMD_STATUS_TIMEOUT: 605 dev_dbg(iproc_i2c->device, "bus timeout\n"); 606 return -ETIMEDOUT; 607 608 case M_CMD_STATUS_FIFO_UNDERRUN: 609 dev_dbg(iproc_i2c->device, "FIFO under-run\n"); 610 return -ENXIO; 611 612 case M_CMD_STATUS_RX_FIFO_FULL: 613 dev_dbg(iproc_i2c->device, "RX FIFO full\n"); 614 return -ETIMEDOUT; 615 616 default: 617 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val); 618 619 /* re-initialize i2c for recovery */ 620 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 621 bcm_iproc_i2c_init(iproc_i2c); 622 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 623 624 return -EIO; 625 } 626 } 627 628 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, 629 struct i2c_msg *msg, 630 u32 cmd) 631 { 632 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC); 633 u32 val, status; 634 int ret; 635 636 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd); 637 638 if (iproc_i2c->irq) { 639 time_left = wait_for_completion_timeout(&iproc_i2c->done, 640 time_left); 641 /* disable all interrupts */ 642 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 643 /* read it back to flush the write */ 644 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 645 /* make sure the interrupt handler isn't running */ 646 synchronize_irq(iproc_i2c->irq); 647 648 } else { /* polling mode */ 649 unsigned long timeout = jiffies + time_left; 650 651 do { 652 status = iproc_i2c_rd_reg(iproc_i2c, 653 IS_OFFSET) & ISR_MASK; 654 bcm_iproc_i2c_process_m_event(iproc_i2c, status); 655 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status); 656 657 if (time_after(jiffies, timeout)) { 658 time_left = 0; 659 break; 660 } 661 662 cpu_relax(); 663 cond_resched(); 664 } while (!iproc_i2c->xfer_is_done); 665 } 666 667 if (!time_left && !iproc_i2c->xfer_is_done) { 668 dev_err(iproc_i2c->device, "transaction timed out\n"); 669 670 /* flush both TX/RX FIFOs */ 671 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 672 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 673 return -ETIMEDOUT; 674 } 675 676 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg); 677 if (ret) { 678 /* flush both TX/RX FIFOs */ 679 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT); 680 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val); 681 return ret; 682 } 683 684 return 0; 685 } 686 687 static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, 688 struct i2c_msg *msg) 689 { 690 int i; 691 u8 addr; 692 u32 val, tmp, val_intr_en; 693 unsigned int tx_bytes; 694 695 /* check if bus is busy */ 696 if (!!(iproc_i2c_rd_reg(iproc_i2c, 697 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) { 698 dev_warn(iproc_i2c->device, "bus is busy\n"); 699 return -EBUSY; 700 } 701 702 iproc_i2c->msg = msg; 703 704 /* format and load slave address into the TX FIFO */ 705 addr = i2c_8bit_addr_from_msg(msg); 706 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr); 707 708 /* 709 * For a write transaction, load data into the TX FIFO. Only allow 710 * loading up to TX FIFO size - 1 bytes of data since the first byte 711 * has been used up by the slave address 712 */ 713 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1); 714 if (!(msg->flags & I2C_M_RD)) { 715 for (i = 0; i < tx_bytes; i++) { 716 val = msg->buf[i]; 717 718 /* mark the last byte */ 719 if (i == msg->len - 1) 720 val |= BIT(M_TX_WR_STATUS_SHIFT); 721 722 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); 723 } 724 iproc_i2c->tx_bytes = tx_bytes; 725 } 726 727 /* mark as incomplete before starting the transaction */ 728 if (iproc_i2c->irq) 729 reinit_completion(&iproc_i2c->done); 730 731 iproc_i2c->xfer_is_done = 0; 732 733 /* 734 * Enable the "start busy" interrupt, which will be triggered after the 735 * transaction is done, i.e., the internal start_busy bit, transitions 736 * from 1 to 0. 737 */ 738 val_intr_en = BIT(IE_M_START_BUSY_SHIFT); 739 740 /* 741 * If TX data size is larger than the TX FIFO, need to enable TX 742 * underrun interrupt, which will be triggerred when the TX FIFO is 743 * empty. When that happens we can then pump more data into the FIFO 744 */ 745 if (!(msg->flags & I2C_M_RD) && 746 msg->len > iproc_i2c->tx_bytes) 747 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); 748 749 /* 750 * Now we can activate the transfer. For a read operation, specify the 751 * number of bytes to read 752 */ 753 val = BIT(M_CMD_START_BUSY_SHIFT); 754 if (msg->flags & I2C_M_RD) { 755 iproc_i2c->rx_bytes = 0; 756 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) 757 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE; 758 else 759 iproc_i2c->thld_bytes = msg->len; 760 761 /* set threshold value */ 762 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET); 763 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT); 764 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT; 765 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp); 766 767 /* enable the RX threshold interrupt */ 768 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); 769 770 val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) | 771 (msg->len << M_CMD_RD_CNT_SHIFT); 772 } else { 773 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); 774 } 775 776 if (iproc_i2c->irq) 777 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en); 778 779 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val); 780 } 781 782 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, 783 struct i2c_msg msgs[], int num) 784 { 785 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter); 786 int ret, i; 787 788 /* go through all messages */ 789 for (i = 0; i < num; i++) { 790 ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]); 791 if (ret) { 792 dev_dbg(iproc_i2c->device, "xfer failed\n"); 793 return ret; 794 } 795 } 796 797 return num; 798 } 799 800 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) 801 { 802 u32 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 803 804 if (adap->algo->reg_slave) 805 val |= I2C_FUNC_SLAVE; 806 807 return val; 808 } 809 810 static struct i2c_algorithm bcm_iproc_algo = { 811 .master_xfer = bcm_iproc_i2c_xfer, 812 .functionality = bcm_iproc_i2c_functionality, 813 .reg_slave = bcm_iproc_i2c_reg_slave, 814 .unreg_slave = bcm_iproc_i2c_unreg_slave, 815 }; 816 817 static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { 818 .max_read_len = M_RX_MAX_READ_LEN, 819 }; 820 821 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c) 822 { 823 unsigned int bus_speed; 824 u32 val; 825 int ret = of_property_read_u32(iproc_i2c->device->of_node, 826 "clock-frequency", &bus_speed); 827 if (ret < 0) { 828 dev_info(iproc_i2c->device, 829 "unable to interpret clock-frequency DT property\n"); 830 bus_speed = 100000; 831 } 832 833 if (bus_speed < 100000) { 834 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n", 835 bus_speed); 836 dev_err(iproc_i2c->device, 837 "valid speeds are 100khz and 400khz\n"); 838 return -EINVAL; 839 } else if (bus_speed < 400000) { 840 bus_speed = 100000; 841 } else { 842 bus_speed = 400000; 843 } 844 845 iproc_i2c->bus_speed = bus_speed; 846 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 847 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 848 val |= (bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 849 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 850 851 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed); 852 853 return 0; 854 } 855 856 static int bcm_iproc_i2c_probe(struct platform_device *pdev) 857 { 858 int irq, ret = 0; 859 struct bcm_iproc_i2c_dev *iproc_i2c; 860 struct i2c_adapter *adap; 861 struct resource *res; 862 863 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c), 864 GFP_KERNEL); 865 if (!iproc_i2c) 866 return -ENOMEM; 867 868 platform_set_drvdata(pdev, iproc_i2c); 869 iproc_i2c->device = &pdev->dev; 870 iproc_i2c->type = 871 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev); 872 init_completion(&iproc_i2c->done); 873 874 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 875 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res); 876 if (IS_ERR(iproc_i2c->base)) 877 return PTR_ERR(iproc_i2c->base); 878 879 if (iproc_i2c->type == IPROC_I2C_NIC) { 880 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 881 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device, 882 res); 883 if (IS_ERR(iproc_i2c->idm_base)) 884 return PTR_ERR(iproc_i2c->idm_base); 885 886 ret = of_property_read_u32(iproc_i2c->device->of_node, 887 "brcm,ape-hsls-addr-mask", 888 &iproc_i2c->ape_addr_mask); 889 if (ret < 0) { 890 dev_err(iproc_i2c->device, 891 "'brcm,ape-hsls-addr-mask' missing\n"); 892 return -EINVAL; 893 } 894 895 spin_lock_init(&iproc_i2c->idm_lock); 896 897 /* no slave support */ 898 bcm_iproc_algo.reg_slave = NULL; 899 bcm_iproc_algo.unreg_slave = NULL; 900 } 901 902 ret = bcm_iproc_i2c_init(iproc_i2c); 903 if (ret) 904 return ret; 905 906 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c); 907 if (ret) 908 return ret; 909 910 irq = platform_get_irq(pdev, 0); 911 if (irq > 0) { 912 ret = devm_request_irq(iproc_i2c->device, irq, 913 bcm_iproc_i2c_isr, 0, pdev->name, 914 iproc_i2c); 915 if (ret < 0) { 916 dev_err(iproc_i2c->device, 917 "unable to request irq %i\n", irq); 918 return ret; 919 } 920 921 iproc_i2c->irq = irq; 922 } else { 923 dev_warn(iproc_i2c->device, 924 "no irq resource, falling back to poll mode\n"); 925 } 926 927 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 928 929 adap = &iproc_i2c->adapter; 930 i2c_set_adapdata(adap, iproc_i2c); 931 strlcpy(adap->name, "Broadcom iProc I2C adapter", sizeof(adap->name)); 932 adap->algo = &bcm_iproc_algo; 933 adap->quirks = &bcm_iproc_i2c_quirks; 934 adap->dev.parent = &pdev->dev; 935 adap->dev.of_node = pdev->dev.of_node; 936 937 return i2c_add_adapter(adap); 938 } 939 940 static int bcm_iproc_i2c_remove(struct platform_device *pdev) 941 { 942 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev); 943 944 if (iproc_i2c->irq) { 945 /* 946 * Make sure there's no pending interrupt when we remove the 947 * adapter 948 */ 949 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 950 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 951 synchronize_irq(iproc_i2c->irq); 952 } 953 954 i2c_del_adapter(&iproc_i2c->adapter); 955 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 956 957 return 0; 958 } 959 960 #ifdef CONFIG_PM_SLEEP 961 962 static int bcm_iproc_i2c_suspend(struct device *dev) 963 { 964 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 965 966 if (iproc_i2c->irq) { 967 /* 968 * Make sure there's no pending interrupt when we go into 969 * suspend 970 */ 971 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0); 972 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 973 synchronize_irq(iproc_i2c->irq); 974 } 975 976 /* now disable the controller */ 977 bcm_iproc_i2c_enable_disable(iproc_i2c, false); 978 979 return 0; 980 } 981 982 static int bcm_iproc_i2c_resume(struct device *dev) 983 { 984 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev); 985 int ret; 986 u32 val; 987 988 /* 989 * Power domain could have been shut off completely in system deep 990 * sleep, so re-initialize the block here 991 */ 992 ret = bcm_iproc_i2c_init(iproc_i2c); 993 if (ret) 994 return ret; 995 996 /* configure to the desired bus speed */ 997 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET); 998 val &= ~BIT(TIM_CFG_MODE_400_SHIFT); 999 val |= (iproc_i2c->bus_speed == 400000) << TIM_CFG_MODE_400_SHIFT; 1000 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val); 1001 1002 bcm_iproc_i2c_enable_disable(iproc_i2c, true); 1003 1004 return 0; 1005 } 1006 1007 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = { 1008 .suspend_late = &bcm_iproc_i2c_suspend, 1009 .resume_early = &bcm_iproc_i2c_resume 1010 }; 1011 1012 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops) 1013 #else 1014 #define BCM_IPROC_I2C_PM_OPS NULL 1015 #endif /* CONFIG_PM_SLEEP */ 1016 1017 1018 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave) 1019 { 1020 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1021 1022 if (iproc_i2c->slave) 1023 return -EBUSY; 1024 1025 if (slave->flags & I2C_CLIENT_TEN) 1026 return -EAFNOSUPPORT; 1027 1028 iproc_i2c->slave = slave; 1029 bcm_iproc_i2c_slave_init(iproc_i2c, false); 1030 return 0; 1031 } 1032 1033 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave) 1034 { 1035 u32 tmp; 1036 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter); 1037 1038 if (!iproc_i2c->slave) 1039 return -EINVAL; 1040 1041 iproc_i2c->slave = NULL; 1042 1043 /* disable all slave interrupts */ 1044 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET); 1045 tmp &= ~(IE_S_ALL_INTERRUPT_MASK << 1046 IE_S_ALL_INTERRUPT_SHIFT); 1047 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp); 1048 1049 /* Erase the slave address programmed */ 1050 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET); 1051 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT); 1052 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp); 1053 1054 return 0; 1055 } 1056 1057 static const struct of_device_id bcm_iproc_i2c_of_match[] = { 1058 { 1059 .compatible = "brcm,iproc-i2c", 1060 .data = (int *)IPROC_I2C, 1061 }, { 1062 .compatible = "brcm,iproc-nic-i2c", 1063 .data = (int *)IPROC_I2C_NIC, 1064 }, 1065 { /* sentinel */ } 1066 }; 1067 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match); 1068 1069 static struct platform_driver bcm_iproc_i2c_driver = { 1070 .driver = { 1071 .name = "bcm-iproc-i2c", 1072 .of_match_table = bcm_iproc_i2c_of_match, 1073 .pm = BCM_IPROC_I2C_PM_OPS, 1074 }, 1075 .probe = bcm_iproc_i2c_probe, 1076 .remove = bcm_iproc_i2c_remove, 1077 }; 1078 module_platform_driver(bcm_iproc_i2c_driver); 1079 1080 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); 1081 MODULE_DESCRIPTION("Broadcom iProc I2C Driver"); 1082 MODULE_LICENSE("GPL v2"); 1083