1 /* 2 * This driver implements I2C master functionality using the LSI API2C 3 * controller. 4 * 5 * NOTE: The controller has a limitation in that it can only do transfers of 6 * maximum 255 bytes at a time. If a larger transfer is attempted, error code 7 * (-EINVAL) is returned. 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 */ 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/module.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/platform_device.h> 24 25 #define SCL_WAIT_TIMEOUT_NS 25000000 26 #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) 27 #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100)) 28 #define FIFO_SIZE 8 29 #define SEQ_LEN 2 30 31 #define GLOBAL_CONTROL 0x00 32 #define GLOBAL_MST_EN BIT(0) 33 #define GLOBAL_SLV_EN BIT(1) 34 #define GLOBAL_IBML_EN BIT(2) 35 #define INTERRUPT_STATUS 0x04 36 #define INTERRUPT_ENABLE 0x08 37 #define INT_SLV BIT(1) 38 #define INT_MST BIT(0) 39 #define WAIT_TIMER_CONTROL 0x0c 40 #define WT_EN BIT(15) 41 #define WT_VALUE(_x) ((_x) & 0x7fff) 42 #define IBML_TIMEOUT 0x10 43 #define IBML_LOW_MEXT 0x14 44 #define IBML_LOW_SEXT 0x18 45 #define TIMER_CLOCK_DIV 0x1c 46 #define I2C_BUS_MONITOR 0x20 47 #define BM_SDAC BIT(3) 48 #define BM_SCLC BIT(2) 49 #define BM_SDAS BIT(1) 50 #define BM_SCLS BIT(0) 51 #define SOFT_RESET 0x24 52 #define MST_COMMAND 0x28 53 #define CMD_BUSY (1<<3) 54 #define CMD_MANUAL (0x00 | CMD_BUSY) 55 #define CMD_AUTO (0x01 | CMD_BUSY) 56 #define CMD_SEQUENCE (0x02 | CMD_BUSY) 57 #define MST_RX_XFER 0x2c 58 #define MST_TX_XFER 0x30 59 #define MST_ADDR_1 0x34 60 #define MST_ADDR_2 0x38 61 #define MST_DATA 0x3c 62 #define MST_TX_FIFO 0x40 63 #define MST_RX_FIFO 0x44 64 #define MST_INT_ENABLE 0x48 65 #define MST_INT_STATUS 0x4c 66 #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */ 67 #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */ 68 #define MST_STATUS_SNS (1 << 11) /* Manual mode done */ 69 #define MST_STATUS_SS (1 << 10) /* Automatic mode done */ 70 #define MST_STATUS_SCC (1 << 9) /* Stop complete */ 71 #define MST_STATUS_IP (1 << 8) /* Invalid parameter */ 72 #define MST_STATUS_TSS (1 << 7) /* Timeout */ 73 #define MST_STATUS_AL (1 << 6) /* Arbitration lost */ 74 #define MST_STATUS_ND (1 << 5) /* NAK on data phase */ 75 #define MST_STATUS_NA (1 << 4) /* NAK on address phase */ 76 #define MST_STATUS_NAK (MST_STATUS_NA | \ 77 MST_STATUS_ND) 78 #define MST_STATUS_ERR (MST_STATUS_NAK | \ 79 MST_STATUS_AL | \ 80 MST_STATUS_IP) 81 #define MST_TX_BYTES_XFRD 0x50 82 #define MST_RX_BYTES_XFRD 0x54 83 #define SCL_HIGH_PERIOD 0x80 84 #define SCL_LOW_PERIOD 0x84 85 #define SPIKE_FLTR_LEN 0x88 86 #define SDA_SETUP_TIME 0x8c 87 #define SDA_HOLD_TIME 0x90 88 89 /** 90 * axxia_i2c_dev - I2C device context 91 * @base: pointer to register struct 92 * @msg: pointer to current message 93 * @msg_r: pointer to current read message (sequence transfer) 94 * @msg_xfrd: number of bytes transferred in tx_fifo 95 * @msg_xfrd_r: number of bytes transferred in rx_fifo 96 * @msg_err: error code for completed message 97 * @msg_complete: xfer completion object 98 * @dev: device reference 99 * @adapter: core i2c abstraction 100 * @i2c_clk: clock reference for i2c input clock 101 * @bus_clk_rate: current i2c bus clock rate 102 */ 103 struct axxia_i2c_dev { 104 void __iomem *base; 105 struct i2c_msg *msg; 106 struct i2c_msg *msg_r; 107 size_t msg_xfrd; 108 size_t msg_xfrd_r; 109 int msg_err; 110 struct completion msg_complete; 111 struct device *dev; 112 struct i2c_adapter adapter; 113 struct clk *i2c_clk; 114 u32 bus_clk_rate; 115 }; 116 117 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) 118 { 119 u32 int_en; 120 121 int_en = readl(idev->base + MST_INT_ENABLE); 122 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); 123 } 124 125 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) 126 { 127 u32 int_en; 128 129 int_en = readl(idev->base + MST_INT_ENABLE); 130 writel(int_en | mask, idev->base + MST_INT_ENABLE); 131 } 132 133 /** 134 * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency. 135 */ 136 static u32 ns_to_clk(u64 ns, u32 clk_mhz) 137 { 138 return div_u64(ns * clk_mhz, 1000); 139 } 140 141 static int axxia_i2c_init(struct axxia_i2c_dev *idev) 142 { 143 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; 144 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; 145 u32 t_setup; 146 u32 t_high, t_low; 147 u32 tmo_clk; 148 u32 prescale; 149 unsigned long timeout; 150 151 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", 152 idev->bus_clk_rate, clk_mhz, divisor); 153 154 /* Reset controller */ 155 writel(0x01, idev->base + SOFT_RESET); 156 timeout = jiffies + msecs_to_jiffies(100); 157 while (readl(idev->base + SOFT_RESET) & 1) { 158 if (time_after(jiffies, timeout)) { 159 dev_warn(idev->dev, "Soft reset failed\n"); 160 break; 161 } 162 } 163 164 /* Enable Master Mode */ 165 writel(0x1, idev->base + GLOBAL_CONTROL); 166 167 if (idev->bus_clk_rate <= 100000) { 168 /* Standard mode SCL 50/50, tSU:DAT = 250 ns */ 169 t_high = divisor * 1 / 2; 170 t_low = divisor * 1 / 2; 171 t_setup = ns_to_clk(250, clk_mhz); 172 } else { 173 /* Fast mode SCL 33/66, tSU:DAT = 100 ns */ 174 t_high = divisor * 1 / 3; 175 t_low = divisor * 2 / 3; 176 t_setup = ns_to_clk(100, clk_mhz); 177 } 178 179 /* SCL High Time */ 180 writel(t_high, idev->base + SCL_HIGH_PERIOD); 181 /* SCL Low Time */ 182 writel(t_low, idev->base + SCL_LOW_PERIOD); 183 /* SDA Setup Time */ 184 writel(t_setup, idev->base + SDA_SETUP_TIME); 185 /* SDA Hold Time, 300ns */ 186 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); 187 /* Filter <50ns spikes */ 188 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); 189 190 /* Configure Time-Out Registers */ 191 tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz); 192 193 /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */ 194 for (prescale = 0; prescale < 15; ++prescale) { 195 if (tmo_clk <= 0x7fff) 196 break; 197 tmo_clk >>= 1; 198 } 199 if (tmo_clk > 0x7fff) 200 tmo_clk = 0x7fff; 201 202 /* Prescale divider (log2) */ 203 writel(prescale, idev->base + TIMER_CLOCK_DIV); 204 /* Timeout in divided clocks */ 205 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); 206 207 /* Mask all master interrupt bits */ 208 i2c_int_disable(idev, ~0); 209 210 /* Interrupt enable */ 211 writel(0x01, idev->base + INTERRUPT_ENABLE); 212 213 return 0; 214 } 215 216 static int i2c_m_rd(const struct i2c_msg *msg) 217 { 218 return (msg->flags & I2C_M_RD) != 0; 219 } 220 221 static int i2c_m_ten(const struct i2c_msg *msg) 222 { 223 return (msg->flags & I2C_M_TEN) != 0; 224 } 225 226 static int i2c_m_recv_len(const struct i2c_msg *msg) 227 { 228 return (msg->flags & I2C_M_RECV_LEN) != 0; 229 } 230 231 /** 232 * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block 233 * transfer length if this is the first byte of such a transfer. 234 */ 235 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) 236 { 237 struct i2c_msg *msg = idev->msg_r; 238 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); 239 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r); 240 241 while (bytes_to_transfer-- > 0) { 242 int c = readl(idev->base + MST_DATA); 243 244 if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) { 245 /* 246 * Check length byte for SMBus block read 247 */ 248 if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { 249 idev->msg_err = -EPROTO; 250 i2c_int_disable(idev, ~MST_STATUS_TSS); 251 complete(&idev->msg_complete); 252 break; 253 } 254 msg->len = 1 + c; 255 writel(msg->len, idev->base + MST_RX_XFER); 256 } 257 msg->buf[idev->msg_xfrd_r++] = c; 258 } 259 260 return 0; 261 } 262 263 /** 264 * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. 265 * @return: Number of bytes left to transfer. 266 */ 267 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev) 268 { 269 struct i2c_msg *msg = idev->msg; 270 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); 271 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd); 272 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer; 273 274 while (bytes_to_transfer-- > 0) 275 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); 276 277 return ret; 278 } 279 280 static irqreturn_t axxia_i2c_isr(int irq, void *_dev) 281 { 282 struct axxia_i2c_dev *idev = _dev; 283 u32 status; 284 285 if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST)) 286 return IRQ_NONE; 287 288 /* Read interrupt status bits */ 289 status = readl(idev->base + MST_INT_STATUS); 290 291 if (!idev->msg) { 292 dev_warn(idev->dev, "unexpected interrupt\n"); 293 goto out; 294 } 295 296 /* RX FIFO needs service? */ 297 if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL)) 298 axxia_i2c_empty_rx_fifo(idev); 299 300 /* TX FIFO needs service? */ 301 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) { 302 if (axxia_i2c_fill_tx_fifo(idev) == 0) 303 i2c_int_disable(idev, MST_STATUS_TFL); 304 } 305 306 if (unlikely(status & MST_STATUS_ERR)) { 307 /* Transfer error */ 308 i2c_int_disable(idev, ~0); 309 if (status & MST_STATUS_AL) 310 idev->msg_err = -EAGAIN; 311 else if (status & MST_STATUS_NAK) 312 idev->msg_err = -ENXIO; 313 else 314 idev->msg_err = -EIO; 315 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n", 316 status, 317 idev->msg->addr, 318 readl(idev->base + MST_RX_BYTES_XFRD), 319 readl(idev->base + MST_RX_XFER), 320 readl(idev->base + MST_TX_BYTES_XFRD), 321 readl(idev->base + MST_TX_XFER)); 322 complete(&idev->msg_complete); 323 } else if (status & MST_STATUS_SCC) { 324 /* Stop completed */ 325 i2c_int_disable(idev, ~MST_STATUS_TSS); 326 complete(&idev->msg_complete); 327 } else if (status & MST_STATUS_SNS) { 328 /* Transfer done */ 329 i2c_int_disable(idev, ~MST_STATUS_TSS); 330 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len) 331 axxia_i2c_empty_rx_fifo(idev); 332 complete(&idev->msg_complete); 333 } else if (status & MST_STATUS_SS) { 334 /* Auto/Sequence transfer done */ 335 complete(&idev->msg_complete); 336 } else if (status & MST_STATUS_TSS) { 337 /* Transfer timeout */ 338 idev->msg_err = -ETIMEDOUT; 339 i2c_int_disable(idev, ~MST_STATUS_TSS); 340 complete(&idev->msg_complete); 341 } 342 343 out: 344 /* Clear interrupt */ 345 writel(INT_MST, idev->base + INTERRUPT_STATUS); 346 347 return IRQ_HANDLED; 348 } 349 350 static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg) 351 { 352 u32 addr_1, addr_2; 353 354 if (i2c_m_ten(msg)) { 355 /* 10-bit address 356 * addr_1: 5'b11110 | addr[9:8] | (R/nW) 357 * addr_2: addr[7:0] 358 */ 359 addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06); 360 if (i2c_m_rd(msg)) 361 addr_1 |= 1; /* Set the R/nW bit of the address */ 362 addr_2 = msg->addr & 0xFF; 363 } else { 364 /* 7-bit address 365 * addr_1: addr[6:0] | (R/nW) 366 * addr_2: dont care 367 */ 368 addr_1 = i2c_8bit_addr_from_msg(msg); 369 addr_2 = 0; 370 } 371 372 writel(addr_1, idev->base + MST_ADDR_1); 373 writel(addr_2, idev->base + MST_ADDR_2); 374 } 375 376 /* The NAK interrupt will be sent _before_ issuing STOP command 377 * so the controller might still be busy processing it. No 378 * interrupt will be sent at the end so we have to poll for it 379 */ 380 static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev) 381 { 382 unsigned long timeout = jiffies + I2C_XFER_TIMEOUT; 383 384 do { 385 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0) 386 return 0; 387 usleep_range(1, 100); 388 } while (time_before(jiffies, timeout)); 389 390 return -ETIMEDOUT; 391 } 392 393 static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[]) 394 { 395 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL; 396 u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len; 397 unsigned long time_left; 398 399 axxia_i2c_set_addr(idev, &msgs[0]); 400 401 writel(msgs[0].len, idev->base + MST_TX_XFER); 402 writel(rlen, idev->base + MST_RX_XFER); 403 404 idev->msg = &msgs[0]; 405 idev->msg_r = &msgs[1]; 406 idev->msg_xfrd = 0; 407 idev->msg_xfrd_r = 0; 408 axxia_i2c_fill_tx_fifo(idev); 409 410 writel(CMD_SEQUENCE, idev->base + MST_COMMAND); 411 412 reinit_completion(&idev->msg_complete); 413 i2c_int_enable(idev, int_mask); 414 415 time_left = wait_for_completion_timeout(&idev->msg_complete, 416 I2C_XFER_TIMEOUT); 417 418 i2c_int_disable(idev, int_mask); 419 420 axxia_i2c_empty_rx_fifo(idev); 421 422 if (idev->msg_err == -ENXIO) { 423 if (axxia_i2c_handle_seq_nak(idev)) 424 axxia_i2c_init(idev); 425 } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) { 426 dev_warn(idev->dev, "busy after xfer\n"); 427 } 428 429 if (time_left == 0) { 430 idev->msg_err = -ETIMEDOUT; 431 i2c_recover_bus(&idev->adapter); 432 axxia_i2c_init(idev); 433 } 434 435 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) 436 axxia_i2c_init(idev); 437 438 return idev->msg_err; 439 } 440 441 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) 442 { 443 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS; 444 u32 rx_xfer, tx_xfer; 445 unsigned long time_left; 446 unsigned int wt_value; 447 448 idev->msg = msg; 449 idev->msg_r = msg; 450 idev->msg_xfrd = 0; 451 idev->msg_xfrd_r = 0; 452 reinit_completion(&idev->msg_complete); 453 454 axxia_i2c_set_addr(idev, msg); 455 456 if (i2c_m_rd(msg)) { 457 /* I2C read transfer */ 458 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len; 459 tx_xfer = 0; 460 } else { 461 /* I2C write transfer */ 462 rx_xfer = 0; 463 tx_xfer = msg->len; 464 } 465 466 writel(rx_xfer, idev->base + MST_RX_XFER); 467 writel(tx_xfer, idev->base + MST_TX_XFER); 468 469 if (i2c_m_rd(msg)) 470 int_mask |= MST_STATUS_RFL; 471 else if (axxia_i2c_fill_tx_fifo(idev) != 0) 472 int_mask |= MST_STATUS_TFL; 473 474 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL)); 475 /* Disable wait timer temporarly */ 476 writel(wt_value, idev->base + WAIT_TIMER_CONTROL); 477 /* Check if timeout error happened */ 478 if (idev->msg_err) 479 goto out; 480 481 /* Start manual mode */ 482 writel(CMD_MANUAL, idev->base + MST_COMMAND); 483 484 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL); 485 486 i2c_int_enable(idev, int_mask); 487 488 time_left = wait_for_completion_timeout(&idev->msg_complete, 489 I2C_XFER_TIMEOUT); 490 491 i2c_int_disable(idev, int_mask); 492 493 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 494 dev_warn(idev->dev, "busy after xfer\n"); 495 496 if (time_left == 0) { 497 idev->msg_err = -ETIMEDOUT; 498 i2c_recover_bus(&idev->adapter); 499 axxia_i2c_init(idev); 500 } 501 502 out: 503 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO && 504 idev->msg_err != -ETIMEDOUT) 505 axxia_i2c_init(idev); 506 507 return idev->msg_err; 508 } 509 510 static int axxia_i2c_stop(struct axxia_i2c_dev *idev) 511 { 512 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC | MST_STATUS_TSS; 513 unsigned long time_left; 514 515 reinit_completion(&idev->msg_complete); 516 517 /* Issue stop */ 518 writel(0xb, idev->base + MST_COMMAND); 519 i2c_int_enable(idev, int_mask); 520 time_left = wait_for_completion_timeout(&idev->msg_complete, 521 I2C_STOP_TIMEOUT); 522 i2c_int_disable(idev, int_mask); 523 if (time_left == 0) 524 return -ETIMEDOUT; 525 526 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 527 dev_warn(idev->dev, "busy after stop\n"); 528 529 return 0; 530 } 531 532 /* This function checks if the msgs[] array contains messages compatible with 533 * Sequence mode of operation. This mode assumes there will be exactly one 534 * write of non-zero length followed by exactly one read of non-zero length, 535 * both targeted at the same client device. 536 */ 537 static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num) 538 { 539 return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) && 540 msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE && 541 msgs[1].len > 0 && msgs[0].addr == msgs[1].addr; 542 } 543 544 static int 545 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 546 { 547 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 548 int i; 549 int ret = 0; 550 551 idev->msg_err = 0; 552 553 if (axxia_i2c_sequence_ok(msgs, num)) { 554 ret = axxia_i2c_xfer_seq(idev, msgs); 555 return ret ? : SEQ_LEN; 556 } 557 558 i2c_int_enable(idev, MST_STATUS_TSS); 559 560 for (i = 0; ret == 0 && i < num; ++i) 561 ret = axxia_i2c_xfer_msg(idev, &msgs[i]); 562 563 axxia_i2c_stop(idev); 564 565 return ret ? : i; 566 } 567 568 static int axxia_i2c_get_scl(struct i2c_adapter *adap) 569 { 570 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 571 572 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS); 573 } 574 575 static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val) 576 { 577 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 578 u32 tmp; 579 580 /* Preserve SDA Control */ 581 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC; 582 if (!val) 583 tmp |= BM_SCLC; 584 writel(tmp, idev->base + I2C_BUS_MONITOR); 585 } 586 587 static int axxia_i2c_get_sda(struct i2c_adapter *adap) 588 { 589 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 590 591 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS); 592 } 593 594 static struct i2c_bus_recovery_info axxia_i2c_recovery_info = { 595 .recover_bus = i2c_generic_scl_recovery, 596 .get_scl = axxia_i2c_get_scl, 597 .set_scl = axxia_i2c_set_scl, 598 .get_sda = axxia_i2c_get_sda, 599 }; 600 601 static u32 axxia_i2c_func(struct i2c_adapter *adap) 602 { 603 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 604 I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA); 605 return caps; 606 } 607 608 static const struct i2c_algorithm axxia_i2c_algo = { 609 .master_xfer = axxia_i2c_xfer, 610 .functionality = axxia_i2c_func, 611 }; 612 613 static const struct i2c_adapter_quirks axxia_i2c_quirks = { 614 .max_read_len = 255, 615 .max_write_len = 255, 616 }; 617 618 static int axxia_i2c_probe(struct platform_device *pdev) 619 { 620 struct device_node *np = pdev->dev.of_node; 621 struct axxia_i2c_dev *idev = NULL; 622 struct resource *res; 623 void __iomem *base; 624 int irq; 625 int ret = 0; 626 627 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); 628 if (!idev) 629 return -ENOMEM; 630 631 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 632 base = devm_ioremap_resource(&pdev->dev, res); 633 if (IS_ERR(base)) 634 return PTR_ERR(base); 635 636 irq = platform_get_irq(pdev, 0); 637 if (irq < 0) { 638 dev_err(&pdev->dev, "missing interrupt resource\n"); 639 return irq; 640 } 641 642 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c"); 643 if (IS_ERR(idev->i2c_clk)) { 644 dev_err(&pdev->dev, "missing clock\n"); 645 return PTR_ERR(idev->i2c_clk); 646 } 647 648 idev->base = base; 649 idev->dev = &pdev->dev; 650 init_completion(&idev->msg_complete); 651 652 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate); 653 if (idev->bus_clk_rate == 0) 654 idev->bus_clk_rate = 100000; /* default clock rate */ 655 656 ret = clk_prepare_enable(idev->i2c_clk); 657 if (ret) { 658 dev_err(&pdev->dev, "failed to enable clock\n"); 659 return ret; 660 } 661 662 ret = axxia_i2c_init(idev); 663 if (ret) { 664 dev_err(&pdev->dev, "failed to initialize\n"); 665 goto error_disable_clk; 666 } 667 668 ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0, 669 pdev->name, idev); 670 if (ret) { 671 dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq); 672 goto error_disable_clk; 673 } 674 675 i2c_set_adapdata(&idev->adapter, idev); 676 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 677 idev->adapter.owner = THIS_MODULE; 678 idev->adapter.algo = &axxia_i2c_algo; 679 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; 680 idev->adapter.quirks = &axxia_i2c_quirks; 681 idev->adapter.dev.parent = &pdev->dev; 682 idev->adapter.dev.of_node = pdev->dev.of_node; 683 684 platform_set_drvdata(pdev, idev); 685 686 ret = i2c_add_adapter(&idev->adapter); 687 if (ret) 688 goto error_disable_clk; 689 690 return 0; 691 692 error_disable_clk: 693 clk_disable_unprepare(idev->i2c_clk); 694 return ret; 695 } 696 697 static int axxia_i2c_remove(struct platform_device *pdev) 698 { 699 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev); 700 701 clk_disable_unprepare(idev->i2c_clk); 702 i2c_del_adapter(&idev->adapter); 703 704 return 0; 705 } 706 707 /* Match table for of_platform binding */ 708 static const struct of_device_id axxia_i2c_of_match[] = { 709 { .compatible = "lsi,api2c", }, 710 {}, 711 }; 712 713 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match); 714 715 static struct platform_driver axxia_i2c_driver = { 716 .probe = axxia_i2c_probe, 717 .remove = axxia_i2c_remove, 718 .driver = { 719 .name = "axxia-i2c", 720 .of_match_table = axxia_i2c_of_match, 721 }, 722 }; 723 724 module_platform_driver(axxia_i2c_driver); 725 726 MODULE_DESCRIPTION("Axxia I2C Bus driver"); 727 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>"); 728 MODULE_LICENSE("GPL v2"); 729