1 /* 2 * This driver implements I2C master functionality using the LSI API2C 3 * controller. 4 * 5 * NOTE: The controller has a limitation in that it can only do transfers of 6 * maximum 255 bytes at a time. If a larger transfer is attempted, error code 7 * (-EINVAL) is returned. 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 */ 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/err.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/platform_device.h> 23 24 #define SCL_WAIT_TIMEOUT_NS 25000000 25 #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) 26 #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100)) 27 #define FIFO_SIZE 8 28 29 #define GLOBAL_CONTROL 0x00 30 #define GLOBAL_MST_EN BIT(0) 31 #define GLOBAL_SLV_EN BIT(1) 32 #define GLOBAL_IBML_EN BIT(2) 33 #define INTERRUPT_STATUS 0x04 34 #define INTERRUPT_ENABLE 0x08 35 #define INT_SLV BIT(1) 36 #define INT_MST BIT(0) 37 #define WAIT_TIMER_CONTROL 0x0c 38 #define WT_EN BIT(15) 39 #define WT_VALUE(_x) ((_x) & 0x7fff) 40 #define IBML_TIMEOUT 0x10 41 #define IBML_LOW_MEXT 0x14 42 #define IBML_LOW_SEXT 0x18 43 #define TIMER_CLOCK_DIV 0x1c 44 #define I2C_BUS_MONITOR 0x20 45 #define SOFT_RESET 0x24 46 #define MST_COMMAND 0x28 47 #define CMD_BUSY (1<<3) 48 #define CMD_MANUAL (0x00 | CMD_BUSY) 49 #define CMD_AUTO (0x01 | CMD_BUSY) 50 #define MST_RX_XFER 0x2c 51 #define MST_TX_XFER 0x30 52 #define MST_ADDR_1 0x34 53 #define MST_ADDR_2 0x38 54 #define MST_DATA 0x3c 55 #define MST_TX_FIFO 0x40 56 #define MST_RX_FIFO 0x44 57 #define MST_INT_ENABLE 0x48 58 #define MST_INT_STATUS 0x4c 59 #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */ 60 #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */ 61 #define MST_STATUS_SNS (1 << 11) /* Manual mode done */ 62 #define MST_STATUS_SS (1 << 10) /* Automatic mode done */ 63 #define MST_STATUS_SCC (1 << 9) /* Stop complete */ 64 #define MST_STATUS_IP (1 << 8) /* Invalid parameter */ 65 #define MST_STATUS_TSS (1 << 7) /* Timeout */ 66 #define MST_STATUS_AL (1 << 6) /* Arbitration lost */ 67 #define MST_STATUS_ND (1 << 5) /* NAK on data phase */ 68 #define MST_STATUS_NA (1 << 4) /* NAK on address phase */ 69 #define MST_STATUS_NAK (MST_STATUS_NA | \ 70 MST_STATUS_ND) 71 #define MST_STATUS_ERR (MST_STATUS_NAK | \ 72 MST_STATUS_AL | \ 73 MST_STATUS_IP | \ 74 MST_STATUS_TSS) 75 #define MST_TX_BYTES_XFRD 0x50 76 #define MST_RX_BYTES_XFRD 0x54 77 #define SCL_HIGH_PERIOD 0x80 78 #define SCL_LOW_PERIOD 0x84 79 #define SPIKE_FLTR_LEN 0x88 80 #define SDA_SETUP_TIME 0x8c 81 #define SDA_HOLD_TIME 0x90 82 83 /** 84 * axxia_i2c_dev - I2C device context 85 * @base: pointer to register struct 86 * @msg: pointer to current message 87 * @msg_xfrd: number of bytes transferred in msg 88 * @msg_err: error code for completed message 89 * @msg_complete: xfer completion object 90 * @dev: device reference 91 * @adapter: core i2c abstraction 92 * @i2c_clk: clock reference for i2c input clock 93 * @bus_clk_rate: current i2c bus clock rate 94 */ 95 struct axxia_i2c_dev { 96 void __iomem *base; 97 struct i2c_msg *msg; 98 size_t msg_xfrd; 99 int msg_err; 100 struct completion msg_complete; 101 struct device *dev; 102 struct i2c_adapter adapter; 103 struct clk *i2c_clk; 104 u32 bus_clk_rate; 105 }; 106 107 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) 108 { 109 u32 int_en; 110 111 int_en = readl(idev->base + MST_INT_ENABLE); 112 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); 113 } 114 115 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) 116 { 117 u32 int_en; 118 119 int_en = readl(idev->base + MST_INT_ENABLE); 120 writel(int_en | mask, idev->base + MST_INT_ENABLE); 121 } 122 123 /** 124 * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency. 125 */ 126 static u32 ns_to_clk(u64 ns, u32 clk_mhz) 127 { 128 return div_u64(ns * clk_mhz, 1000); 129 } 130 131 static int axxia_i2c_init(struct axxia_i2c_dev *idev) 132 { 133 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; 134 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; 135 u32 t_setup; 136 u32 t_high, t_low; 137 u32 tmo_clk; 138 u32 prescale; 139 unsigned long timeout; 140 141 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", 142 idev->bus_clk_rate, clk_mhz, divisor); 143 144 /* Reset controller */ 145 writel(0x01, idev->base + SOFT_RESET); 146 timeout = jiffies + msecs_to_jiffies(100); 147 while (readl(idev->base + SOFT_RESET) & 1) { 148 if (time_after(jiffies, timeout)) { 149 dev_warn(idev->dev, "Soft reset failed\n"); 150 break; 151 } 152 } 153 154 /* Enable Master Mode */ 155 writel(0x1, idev->base + GLOBAL_CONTROL); 156 157 if (idev->bus_clk_rate <= 100000) { 158 /* Standard mode SCL 50/50, tSU:DAT = 250 ns */ 159 t_high = divisor * 1 / 2; 160 t_low = divisor * 1 / 2; 161 t_setup = ns_to_clk(250, clk_mhz); 162 } else { 163 /* Fast mode SCL 33/66, tSU:DAT = 100 ns */ 164 t_high = divisor * 1 / 3; 165 t_low = divisor * 2 / 3; 166 t_setup = ns_to_clk(100, clk_mhz); 167 } 168 169 /* SCL High Time */ 170 writel(t_high, idev->base + SCL_HIGH_PERIOD); 171 /* SCL Low Time */ 172 writel(t_low, idev->base + SCL_LOW_PERIOD); 173 /* SDA Setup Time */ 174 writel(t_setup, idev->base + SDA_SETUP_TIME); 175 /* SDA Hold Time, 300ns */ 176 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); 177 /* Filter <50ns spikes */ 178 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); 179 180 /* Configure Time-Out Registers */ 181 tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz); 182 183 /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */ 184 for (prescale = 0; prescale < 15; ++prescale) { 185 if (tmo_clk <= 0x7fff) 186 break; 187 tmo_clk >>= 1; 188 } 189 if (tmo_clk > 0x7fff) 190 tmo_clk = 0x7fff; 191 192 /* Prescale divider (log2) */ 193 writel(prescale, idev->base + TIMER_CLOCK_DIV); 194 /* Timeout in divided clocks */ 195 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); 196 197 /* Mask all master interrupt bits */ 198 i2c_int_disable(idev, ~0); 199 200 /* Interrupt enable */ 201 writel(0x01, idev->base + INTERRUPT_ENABLE); 202 203 return 0; 204 } 205 206 static int i2c_m_rd(const struct i2c_msg *msg) 207 { 208 return (msg->flags & I2C_M_RD) != 0; 209 } 210 211 static int i2c_m_ten(const struct i2c_msg *msg) 212 { 213 return (msg->flags & I2C_M_TEN) != 0; 214 } 215 216 static int i2c_m_recv_len(const struct i2c_msg *msg) 217 { 218 return (msg->flags & I2C_M_RECV_LEN) != 0; 219 } 220 221 /** 222 * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block 223 * transfer length if this is the first byte of such a transfer. 224 */ 225 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) 226 { 227 struct i2c_msg *msg = idev->msg; 228 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); 229 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd); 230 231 while (bytes_to_transfer-- > 0) { 232 int c = readl(idev->base + MST_DATA); 233 234 if (idev->msg_xfrd == 0 && i2c_m_recv_len(msg)) { 235 /* 236 * Check length byte for SMBus block read 237 */ 238 if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { 239 idev->msg_err = -EPROTO; 240 i2c_int_disable(idev, ~0); 241 complete(&idev->msg_complete); 242 break; 243 } 244 msg->len = 1 + c; 245 writel(msg->len, idev->base + MST_RX_XFER); 246 } 247 msg->buf[idev->msg_xfrd++] = c; 248 } 249 250 return 0; 251 } 252 253 /** 254 * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. 255 * @return: Number of bytes left to transfer. 256 */ 257 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev) 258 { 259 struct i2c_msg *msg = idev->msg; 260 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); 261 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd); 262 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer; 263 264 while (bytes_to_transfer-- > 0) 265 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); 266 267 return ret; 268 } 269 270 static irqreturn_t axxia_i2c_isr(int irq, void *_dev) 271 { 272 struct axxia_i2c_dev *idev = _dev; 273 u32 status; 274 275 if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST)) 276 return IRQ_NONE; 277 278 /* Read interrupt status bits */ 279 status = readl(idev->base + MST_INT_STATUS); 280 281 if (!idev->msg) { 282 dev_warn(idev->dev, "unexpected interrupt\n"); 283 goto out; 284 } 285 286 /* RX FIFO needs service? */ 287 if (i2c_m_rd(idev->msg) && (status & MST_STATUS_RFL)) 288 axxia_i2c_empty_rx_fifo(idev); 289 290 /* TX FIFO needs service? */ 291 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) { 292 if (axxia_i2c_fill_tx_fifo(idev) == 0) 293 i2c_int_disable(idev, MST_STATUS_TFL); 294 } 295 296 if (status & MST_STATUS_SCC) { 297 /* Stop completed */ 298 i2c_int_disable(idev, ~0); 299 complete(&idev->msg_complete); 300 } else if (status & MST_STATUS_SNS) { 301 /* Transfer done */ 302 i2c_int_disable(idev, ~0); 303 if (i2c_m_rd(idev->msg) && idev->msg_xfrd < idev->msg->len) 304 axxia_i2c_empty_rx_fifo(idev); 305 complete(&idev->msg_complete); 306 } else if (unlikely(status & MST_STATUS_ERR)) { 307 /* Transfer error */ 308 i2c_int_disable(idev, ~0); 309 if (status & MST_STATUS_AL) 310 idev->msg_err = -EAGAIN; 311 else if (status & MST_STATUS_NAK) 312 idev->msg_err = -ENXIO; 313 else 314 idev->msg_err = -EIO; 315 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n", 316 status, 317 idev->msg->addr, 318 readl(idev->base + MST_RX_BYTES_XFRD), 319 readl(idev->base + MST_RX_XFER), 320 readl(idev->base + MST_TX_BYTES_XFRD), 321 readl(idev->base + MST_TX_XFER)); 322 complete(&idev->msg_complete); 323 } 324 325 out: 326 /* Clear interrupt */ 327 writel(INT_MST, idev->base + INTERRUPT_STATUS); 328 329 return IRQ_HANDLED; 330 } 331 332 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg) 333 { 334 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS; 335 u32 rx_xfer, tx_xfer; 336 u32 addr_1, addr_2; 337 int ret; 338 339 if (msg->len > 255) { 340 dev_warn(idev->dev, "unsupported length %u\n", msg->len); 341 return -EINVAL; 342 } 343 344 idev->msg = msg; 345 idev->msg_xfrd = 0; 346 idev->msg_err = 0; 347 reinit_completion(&idev->msg_complete); 348 349 if (i2c_m_ten(msg)) { 350 /* 10-bit address 351 * addr_1: 5'b11110 | addr[9:8] | (R/nW) 352 * addr_2: addr[7:0] 353 */ 354 addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06); 355 addr_2 = msg->addr & 0xFF; 356 } else { 357 /* 7-bit address 358 * addr_1: addr[6:0] | (R/nW) 359 * addr_2: dont care 360 */ 361 addr_1 = (msg->addr << 1) & 0xFF; 362 addr_2 = 0; 363 } 364 365 if (i2c_m_rd(msg)) { 366 /* I2C read transfer */ 367 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len; 368 tx_xfer = 0; 369 addr_1 |= 1; /* Set the R/nW bit of the address */ 370 } else { 371 /* I2C write transfer */ 372 rx_xfer = 0; 373 tx_xfer = msg->len; 374 } 375 376 writel(rx_xfer, idev->base + MST_RX_XFER); 377 writel(tx_xfer, idev->base + MST_TX_XFER); 378 writel(addr_1, idev->base + MST_ADDR_1); 379 writel(addr_2, idev->base + MST_ADDR_2); 380 381 if (i2c_m_rd(msg)) 382 int_mask |= MST_STATUS_RFL; 383 else if (axxia_i2c_fill_tx_fifo(idev) != 0) 384 int_mask |= MST_STATUS_TFL; 385 386 /* Start manual mode */ 387 writel(CMD_MANUAL, idev->base + MST_COMMAND); 388 389 i2c_int_enable(idev, int_mask); 390 391 ret = wait_for_completion_timeout(&idev->msg_complete, 392 I2C_XFER_TIMEOUT); 393 394 i2c_int_disable(idev, int_mask); 395 396 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 397 dev_warn(idev->dev, "busy after xfer\n"); 398 399 if (ret == 0) 400 idev->msg_err = -ETIMEDOUT; 401 402 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) 403 axxia_i2c_init(idev); 404 405 return idev->msg_err; 406 } 407 408 static int axxia_i2c_stop(struct axxia_i2c_dev *idev) 409 { 410 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC; 411 int ret; 412 413 reinit_completion(&idev->msg_complete); 414 415 /* Issue stop */ 416 writel(0xb, idev->base + MST_COMMAND); 417 i2c_int_enable(idev, int_mask); 418 ret = wait_for_completion_timeout(&idev->msg_complete, 419 I2C_STOP_TIMEOUT); 420 i2c_int_disable(idev, int_mask); 421 if (ret == 0) 422 return -ETIMEDOUT; 423 424 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 425 dev_warn(idev->dev, "busy after stop\n"); 426 427 return 0; 428 } 429 430 static int 431 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 432 { 433 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 434 int i; 435 int ret = 0; 436 437 for (i = 0; ret == 0 && i < num; ++i) 438 ret = axxia_i2c_xfer_msg(idev, &msgs[i]); 439 440 axxia_i2c_stop(idev); 441 442 return ret ? : i; 443 } 444 445 static u32 axxia_i2c_func(struct i2c_adapter *adap) 446 { 447 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 448 I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA); 449 return caps; 450 } 451 452 static const struct i2c_algorithm axxia_i2c_algo = { 453 .master_xfer = axxia_i2c_xfer, 454 .functionality = axxia_i2c_func, 455 }; 456 457 static int axxia_i2c_probe(struct platform_device *pdev) 458 { 459 struct device_node *np = pdev->dev.of_node; 460 struct axxia_i2c_dev *idev = NULL; 461 struct resource *res; 462 void __iomem *base; 463 int irq; 464 int ret = 0; 465 466 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); 467 if (!idev) 468 return -ENOMEM; 469 470 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 471 base = devm_ioremap_resource(&pdev->dev, res); 472 if (IS_ERR(base)) 473 return PTR_ERR(base); 474 475 irq = platform_get_irq(pdev, 0); 476 if (irq < 0) { 477 dev_err(&pdev->dev, "missing interrupt resource\n"); 478 return irq; 479 } 480 481 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c"); 482 if (IS_ERR(idev->i2c_clk)) { 483 dev_err(&pdev->dev, "missing clock\n"); 484 return PTR_ERR(idev->i2c_clk); 485 } 486 487 idev->base = base; 488 idev->dev = &pdev->dev; 489 init_completion(&idev->msg_complete); 490 491 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate); 492 if (idev->bus_clk_rate == 0) 493 idev->bus_clk_rate = 100000; /* default clock rate */ 494 495 ret = axxia_i2c_init(idev); 496 if (ret) { 497 dev_err(&pdev->dev, "failed to initialize\n"); 498 return ret; 499 } 500 501 ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0, 502 pdev->name, idev); 503 if (ret) { 504 dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq); 505 return ret; 506 } 507 508 clk_prepare_enable(idev->i2c_clk); 509 510 i2c_set_adapdata(&idev->adapter, idev); 511 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 512 idev->adapter.owner = THIS_MODULE; 513 idev->adapter.algo = &axxia_i2c_algo; 514 idev->adapter.dev.parent = &pdev->dev; 515 idev->adapter.dev.of_node = pdev->dev.of_node; 516 517 platform_set_drvdata(pdev, idev); 518 519 ret = i2c_add_adapter(&idev->adapter); 520 if (ret) { 521 dev_err(&pdev->dev, "failed to add adapter\n"); 522 return ret; 523 } 524 525 return 0; 526 } 527 528 static int axxia_i2c_remove(struct platform_device *pdev) 529 { 530 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev); 531 532 clk_disable_unprepare(idev->i2c_clk); 533 i2c_del_adapter(&idev->adapter); 534 535 return 0; 536 } 537 538 /* Match table for of_platform binding */ 539 static const struct of_device_id axxia_i2c_of_match[] = { 540 { .compatible = "lsi,api2c", }, 541 {}, 542 }; 543 544 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match); 545 546 static struct platform_driver axxia_i2c_driver = { 547 .probe = axxia_i2c_probe, 548 .remove = axxia_i2c_remove, 549 .driver = { 550 .name = "axxia-i2c", 551 .of_match_table = axxia_i2c_of_match, 552 }, 553 }; 554 555 module_platform_driver(axxia_i2c_driver); 556 557 MODULE_DESCRIPTION("Axxia I2C Bus driver"); 558 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>"); 559 MODULE_LICENSE("GPL v2"); 560