1 /* 2 * This driver implements I2C master functionality using the LSI API2C 3 * controller. 4 * 5 * NOTE: The controller has a limitation in that it can only do transfers of 6 * maximum 255 bytes at a time. If a larger transfer is attempted, error code 7 * (-EINVAL) is returned. 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 */ 13 #include <linux/clk.h> 14 #include <linux/clkdev.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/module.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/platform_device.h> 24 25 #define SCL_WAIT_TIMEOUT_NS 25000000 26 #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) 27 #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100)) 28 #define FIFO_SIZE 8 29 #define SEQ_LEN 2 30 31 #define GLOBAL_CONTROL 0x00 32 #define GLOBAL_MST_EN BIT(0) 33 #define GLOBAL_SLV_EN BIT(1) 34 #define GLOBAL_IBML_EN BIT(2) 35 #define INTERRUPT_STATUS 0x04 36 #define INTERRUPT_ENABLE 0x08 37 #define INT_SLV BIT(1) 38 #define INT_MST BIT(0) 39 #define WAIT_TIMER_CONTROL 0x0c 40 #define WT_EN BIT(15) 41 #define WT_VALUE(_x) ((_x) & 0x7fff) 42 #define IBML_TIMEOUT 0x10 43 #define IBML_LOW_MEXT 0x14 44 #define IBML_LOW_SEXT 0x18 45 #define TIMER_CLOCK_DIV 0x1c 46 #define I2C_BUS_MONITOR 0x20 47 #define BM_SDAC BIT(3) 48 #define BM_SCLC BIT(2) 49 #define BM_SDAS BIT(1) 50 #define BM_SCLS BIT(0) 51 #define SOFT_RESET 0x24 52 #define MST_COMMAND 0x28 53 #define CMD_BUSY (1<<3) 54 #define CMD_MANUAL (0x00 | CMD_BUSY) 55 #define CMD_AUTO (0x01 | CMD_BUSY) 56 #define CMD_SEQUENCE (0x02 | CMD_BUSY) 57 #define MST_RX_XFER 0x2c 58 #define MST_TX_XFER 0x30 59 #define MST_ADDR_1 0x34 60 #define MST_ADDR_2 0x38 61 #define MST_DATA 0x3c 62 #define MST_TX_FIFO 0x40 63 #define MST_RX_FIFO 0x44 64 #define MST_INT_ENABLE 0x48 65 #define MST_INT_STATUS 0x4c 66 #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */ 67 #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */ 68 #define MST_STATUS_SNS (1 << 11) /* Manual mode done */ 69 #define MST_STATUS_SS (1 << 10) /* Automatic mode done */ 70 #define MST_STATUS_SCC (1 << 9) /* Stop complete */ 71 #define MST_STATUS_IP (1 << 8) /* Invalid parameter */ 72 #define MST_STATUS_TSS (1 << 7) /* Timeout */ 73 #define MST_STATUS_AL (1 << 6) /* Arbitration lost */ 74 #define MST_STATUS_ND (1 << 5) /* NAK on data phase */ 75 #define MST_STATUS_NA (1 << 4) /* NAK on address phase */ 76 #define MST_STATUS_NAK (MST_STATUS_NA | \ 77 MST_STATUS_ND) 78 #define MST_STATUS_ERR (MST_STATUS_NAK | \ 79 MST_STATUS_AL | \ 80 MST_STATUS_IP) 81 #define MST_TX_BYTES_XFRD 0x50 82 #define MST_RX_BYTES_XFRD 0x54 83 #define SCL_HIGH_PERIOD 0x80 84 #define SCL_LOW_PERIOD 0x84 85 #define SPIKE_FLTR_LEN 0x88 86 #define SDA_SETUP_TIME 0x8c 87 #define SDA_HOLD_TIME 0x90 88 89 /** 90 * axxia_i2c_dev - I2C device context 91 * @base: pointer to register struct 92 * @msg: pointer to current message 93 * @msg_r: pointer to current read message (sequence transfer) 94 * @msg_xfrd: number of bytes transferred in tx_fifo 95 * @msg_xfrd_r: number of bytes transferred in rx_fifo 96 * @msg_err: error code for completed message 97 * @msg_complete: xfer completion object 98 * @dev: device reference 99 * @adapter: core i2c abstraction 100 * @i2c_clk: clock reference for i2c input clock 101 * @bus_clk_rate: current i2c bus clock rate 102 * @last: a flag indicating is this is last message in transfer 103 */ 104 struct axxia_i2c_dev { 105 void __iomem *base; 106 struct i2c_msg *msg; 107 struct i2c_msg *msg_r; 108 size_t msg_xfrd; 109 size_t msg_xfrd_r; 110 int msg_err; 111 struct completion msg_complete; 112 struct device *dev; 113 struct i2c_adapter adapter; 114 struct clk *i2c_clk; 115 u32 bus_clk_rate; 116 bool last; 117 }; 118 119 static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask) 120 { 121 u32 int_en; 122 123 int_en = readl(idev->base + MST_INT_ENABLE); 124 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); 125 } 126 127 static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask) 128 { 129 u32 int_en; 130 131 int_en = readl(idev->base + MST_INT_ENABLE); 132 writel(int_en | mask, idev->base + MST_INT_ENABLE); 133 } 134 135 /** 136 * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency. 137 */ 138 static u32 ns_to_clk(u64 ns, u32 clk_mhz) 139 { 140 return div_u64(ns * clk_mhz, 1000); 141 } 142 143 static int axxia_i2c_init(struct axxia_i2c_dev *idev) 144 { 145 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; 146 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; 147 u32 t_setup; 148 u32 t_high, t_low; 149 u32 tmo_clk; 150 u32 prescale; 151 unsigned long timeout; 152 153 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", 154 idev->bus_clk_rate, clk_mhz, divisor); 155 156 /* Reset controller */ 157 writel(0x01, idev->base + SOFT_RESET); 158 timeout = jiffies + msecs_to_jiffies(100); 159 while (readl(idev->base + SOFT_RESET) & 1) { 160 if (time_after(jiffies, timeout)) { 161 dev_warn(idev->dev, "Soft reset failed\n"); 162 break; 163 } 164 } 165 166 /* Enable Master Mode */ 167 writel(0x1, idev->base + GLOBAL_CONTROL); 168 169 if (idev->bus_clk_rate <= 100000) { 170 /* Standard mode SCL 50/50, tSU:DAT = 250 ns */ 171 t_high = divisor * 1 / 2; 172 t_low = divisor * 1 / 2; 173 t_setup = ns_to_clk(250, clk_mhz); 174 } else { 175 /* Fast mode SCL 33/66, tSU:DAT = 100 ns */ 176 t_high = divisor * 1 / 3; 177 t_low = divisor * 2 / 3; 178 t_setup = ns_to_clk(100, clk_mhz); 179 } 180 181 /* SCL High Time */ 182 writel(t_high, idev->base + SCL_HIGH_PERIOD); 183 /* SCL Low Time */ 184 writel(t_low, idev->base + SCL_LOW_PERIOD); 185 /* SDA Setup Time */ 186 writel(t_setup, idev->base + SDA_SETUP_TIME); 187 /* SDA Hold Time, 300ns */ 188 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); 189 /* Filter <50ns spikes */ 190 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); 191 192 /* Configure Time-Out Registers */ 193 tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz); 194 195 /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */ 196 for (prescale = 0; prescale < 15; ++prescale) { 197 if (tmo_clk <= 0x7fff) 198 break; 199 tmo_clk >>= 1; 200 } 201 if (tmo_clk > 0x7fff) 202 tmo_clk = 0x7fff; 203 204 /* Prescale divider (log2) */ 205 writel(prescale, idev->base + TIMER_CLOCK_DIV); 206 /* Timeout in divided clocks */ 207 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); 208 209 /* Mask all master interrupt bits */ 210 i2c_int_disable(idev, ~0); 211 212 /* Interrupt enable */ 213 writel(0x01, idev->base + INTERRUPT_ENABLE); 214 215 return 0; 216 } 217 218 static int i2c_m_rd(const struct i2c_msg *msg) 219 { 220 return (msg->flags & I2C_M_RD) != 0; 221 } 222 223 static int i2c_m_ten(const struct i2c_msg *msg) 224 { 225 return (msg->flags & I2C_M_TEN) != 0; 226 } 227 228 static int i2c_m_recv_len(const struct i2c_msg *msg) 229 { 230 return (msg->flags & I2C_M_RECV_LEN) != 0; 231 } 232 233 /** 234 * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block 235 * transfer length if this is the first byte of such a transfer. 236 */ 237 static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev) 238 { 239 struct i2c_msg *msg = idev->msg_r; 240 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO); 241 int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r); 242 243 while (bytes_to_transfer-- > 0) { 244 int c = readl(idev->base + MST_DATA); 245 246 if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) { 247 /* 248 * Check length byte for SMBus block read 249 */ 250 if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) { 251 idev->msg_err = -EPROTO; 252 i2c_int_disable(idev, ~MST_STATUS_TSS); 253 complete(&idev->msg_complete); 254 break; 255 } 256 msg->len = 1 + c; 257 writel(msg->len, idev->base + MST_RX_XFER); 258 } 259 msg->buf[idev->msg_xfrd_r++] = c; 260 } 261 262 return 0; 263 } 264 265 /** 266 * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. 267 * @return: Number of bytes left to transfer. 268 */ 269 static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev) 270 { 271 struct i2c_msg *msg = idev->msg; 272 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO); 273 int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd); 274 int ret = msg->len - idev->msg_xfrd - bytes_to_transfer; 275 276 while (bytes_to_transfer-- > 0) 277 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); 278 279 return ret; 280 } 281 282 static irqreturn_t axxia_i2c_isr(int irq, void *_dev) 283 { 284 struct axxia_i2c_dev *idev = _dev; 285 u32 status; 286 287 if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST)) 288 return IRQ_NONE; 289 290 /* Read interrupt status bits */ 291 status = readl(idev->base + MST_INT_STATUS); 292 293 if (!idev->msg) { 294 dev_warn(idev->dev, "unexpected interrupt\n"); 295 goto out; 296 } 297 298 /* RX FIFO needs service? */ 299 if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL)) 300 axxia_i2c_empty_rx_fifo(idev); 301 302 /* TX FIFO needs service? */ 303 if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) { 304 if (axxia_i2c_fill_tx_fifo(idev) == 0) 305 i2c_int_disable(idev, MST_STATUS_TFL); 306 } 307 308 if (unlikely(status & MST_STATUS_ERR)) { 309 /* Transfer error */ 310 i2c_int_disable(idev, ~0); 311 if (status & MST_STATUS_AL) 312 idev->msg_err = -EAGAIN; 313 else if (status & MST_STATUS_NAK) 314 idev->msg_err = -ENXIO; 315 else 316 idev->msg_err = -EIO; 317 dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n", 318 status, 319 idev->msg->addr, 320 readl(idev->base + MST_RX_BYTES_XFRD), 321 readl(idev->base + MST_RX_XFER), 322 readl(idev->base + MST_TX_BYTES_XFRD), 323 readl(idev->base + MST_TX_XFER)); 324 complete(&idev->msg_complete); 325 } else if (status & MST_STATUS_SCC) { 326 /* Stop completed */ 327 i2c_int_disable(idev, ~MST_STATUS_TSS); 328 complete(&idev->msg_complete); 329 } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) { 330 /* Transfer done */ 331 int mask = idev->last ? ~0 : ~MST_STATUS_TSS; 332 333 i2c_int_disable(idev, mask); 334 if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len) 335 axxia_i2c_empty_rx_fifo(idev); 336 complete(&idev->msg_complete); 337 } else if (status & MST_STATUS_TSS) { 338 /* Transfer timeout */ 339 idev->msg_err = -ETIMEDOUT; 340 i2c_int_disable(idev, ~MST_STATUS_TSS); 341 complete(&idev->msg_complete); 342 } 343 344 out: 345 /* Clear interrupt */ 346 writel(INT_MST, idev->base + INTERRUPT_STATUS); 347 348 return IRQ_HANDLED; 349 } 350 351 static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg) 352 { 353 u32 addr_1, addr_2; 354 355 if (i2c_m_ten(msg)) { 356 /* 10-bit address 357 * addr_1: 5'b11110 | addr[9:8] | (R/nW) 358 * addr_2: addr[7:0] 359 */ 360 addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06); 361 if (i2c_m_rd(msg)) 362 addr_1 |= 1; /* Set the R/nW bit of the address */ 363 addr_2 = msg->addr & 0xFF; 364 } else { 365 /* 7-bit address 366 * addr_1: addr[6:0] | (R/nW) 367 * addr_2: dont care 368 */ 369 addr_1 = i2c_8bit_addr_from_msg(msg); 370 addr_2 = 0; 371 } 372 373 writel(addr_1, idev->base + MST_ADDR_1); 374 writel(addr_2, idev->base + MST_ADDR_2); 375 } 376 377 /* The NAK interrupt will be sent _before_ issuing STOP command 378 * so the controller might still be busy processing it. No 379 * interrupt will be sent at the end so we have to poll for it 380 */ 381 static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev) 382 { 383 unsigned long timeout = jiffies + I2C_XFER_TIMEOUT; 384 385 do { 386 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0) 387 return 0; 388 usleep_range(1, 100); 389 } while (time_before(jiffies, timeout)); 390 391 return -ETIMEDOUT; 392 } 393 394 static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[]) 395 { 396 u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL; 397 u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len; 398 unsigned long time_left; 399 400 axxia_i2c_set_addr(idev, &msgs[0]); 401 402 writel(msgs[0].len, idev->base + MST_TX_XFER); 403 writel(rlen, idev->base + MST_RX_XFER); 404 405 idev->msg = &msgs[0]; 406 idev->msg_r = &msgs[1]; 407 idev->msg_xfrd = 0; 408 idev->msg_xfrd_r = 0; 409 idev->last = true; 410 axxia_i2c_fill_tx_fifo(idev); 411 412 writel(CMD_SEQUENCE, idev->base + MST_COMMAND); 413 414 reinit_completion(&idev->msg_complete); 415 i2c_int_enable(idev, int_mask); 416 417 time_left = wait_for_completion_timeout(&idev->msg_complete, 418 I2C_XFER_TIMEOUT); 419 420 if (idev->msg_err == -ENXIO) { 421 if (axxia_i2c_handle_seq_nak(idev)) 422 axxia_i2c_init(idev); 423 } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) { 424 dev_warn(idev->dev, "busy after xfer\n"); 425 } 426 427 if (time_left == 0) { 428 idev->msg_err = -ETIMEDOUT; 429 i2c_recover_bus(&idev->adapter); 430 axxia_i2c_init(idev); 431 } 432 433 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO) 434 axxia_i2c_init(idev); 435 436 return idev->msg_err; 437 } 438 439 static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg, 440 bool last) 441 { 442 u32 int_mask = MST_STATUS_ERR; 443 u32 rx_xfer, tx_xfer; 444 unsigned long time_left; 445 unsigned int wt_value; 446 447 idev->msg = msg; 448 idev->msg_r = msg; 449 idev->msg_xfrd = 0; 450 idev->msg_xfrd_r = 0; 451 idev->last = last; 452 reinit_completion(&idev->msg_complete); 453 454 axxia_i2c_set_addr(idev, msg); 455 456 if (i2c_m_rd(msg)) { 457 /* I2C read transfer */ 458 rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len; 459 tx_xfer = 0; 460 } else { 461 /* I2C write transfer */ 462 rx_xfer = 0; 463 tx_xfer = msg->len; 464 } 465 466 writel(rx_xfer, idev->base + MST_RX_XFER); 467 writel(tx_xfer, idev->base + MST_TX_XFER); 468 469 if (i2c_m_rd(msg)) 470 int_mask |= MST_STATUS_RFL; 471 else if (axxia_i2c_fill_tx_fifo(idev) != 0) 472 int_mask |= MST_STATUS_TFL; 473 474 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL)); 475 /* Disable wait timer temporarly */ 476 writel(wt_value, idev->base + WAIT_TIMER_CONTROL); 477 /* Check if timeout error happened */ 478 if (idev->msg_err) 479 goto out; 480 481 if (!last) { 482 writel(CMD_MANUAL, idev->base + MST_COMMAND); 483 int_mask |= MST_STATUS_SNS; 484 } else { 485 writel(CMD_AUTO, idev->base + MST_COMMAND); 486 int_mask |= MST_STATUS_SS; 487 } 488 489 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL); 490 491 i2c_int_enable(idev, int_mask); 492 493 time_left = wait_for_completion_timeout(&idev->msg_complete, 494 I2C_XFER_TIMEOUT); 495 496 i2c_int_disable(idev, int_mask); 497 498 if (readl(idev->base + MST_COMMAND) & CMD_BUSY) 499 dev_warn(idev->dev, "busy after xfer\n"); 500 501 if (time_left == 0) { 502 idev->msg_err = -ETIMEDOUT; 503 i2c_recover_bus(&idev->adapter); 504 axxia_i2c_init(idev); 505 } 506 507 out: 508 if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO && 509 idev->msg_err != -ETIMEDOUT) 510 axxia_i2c_init(idev); 511 512 return idev->msg_err; 513 } 514 515 /* This function checks if the msgs[] array contains messages compatible with 516 * Sequence mode of operation. This mode assumes there will be exactly one 517 * write of non-zero length followed by exactly one read of non-zero length, 518 * both targeted at the same client device. 519 */ 520 static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num) 521 { 522 return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) && 523 msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE && 524 msgs[1].len > 0 && msgs[0].addr == msgs[1].addr; 525 } 526 527 static int 528 axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 529 { 530 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 531 int i; 532 int ret = 0; 533 534 idev->msg_err = 0; 535 536 if (axxia_i2c_sequence_ok(msgs, num)) { 537 ret = axxia_i2c_xfer_seq(idev, msgs); 538 return ret ? : SEQ_LEN; 539 } 540 541 i2c_int_enable(idev, MST_STATUS_TSS); 542 543 for (i = 0; ret == 0 && i < num; ++i) 544 ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1)); 545 546 return ret ? : i; 547 } 548 549 static int axxia_i2c_get_scl(struct i2c_adapter *adap) 550 { 551 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 552 553 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS); 554 } 555 556 static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val) 557 { 558 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 559 u32 tmp; 560 561 /* Preserve SDA Control */ 562 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC; 563 if (!val) 564 tmp |= BM_SCLC; 565 writel(tmp, idev->base + I2C_BUS_MONITOR); 566 } 567 568 static int axxia_i2c_get_sda(struct i2c_adapter *adap) 569 { 570 struct axxia_i2c_dev *idev = i2c_get_adapdata(adap); 571 572 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS); 573 } 574 575 static struct i2c_bus_recovery_info axxia_i2c_recovery_info = { 576 .recover_bus = i2c_generic_scl_recovery, 577 .get_scl = axxia_i2c_get_scl, 578 .set_scl = axxia_i2c_set_scl, 579 .get_sda = axxia_i2c_get_sda, 580 }; 581 582 static u32 axxia_i2c_func(struct i2c_adapter *adap) 583 { 584 u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | 585 I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA); 586 return caps; 587 } 588 589 static const struct i2c_algorithm axxia_i2c_algo = { 590 .master_xfer = axxia_i2c_xfer, 591 .functionality = axxia_i2c_func, 592 }; 593 594 static const struct i2c_adapter_quirks axxia_i2c_quirks = { 595 .max_read_len = 255, 596 .max_write_len = 255, 597 }; 598 599 static int axxia_i2c_probe(struct platform_device *pdev) 600 { 601 struct device_node *np = pdev->dev.of_node; 602 struct axxia_i2c_dev *idev = NULL; 603 struct resource *res; 604 void __iomem *base; 605 int irq; 606 int ret = 0; 607 608 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); 609 if (!idev) 610 return -ENOMEM; 611 612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 613 base = devm_ioremap_resource(&pdev->dev, res); 614 if (IS_ERR(base)) 615 return PTR_ERR(base); 616 617 irq = platform_get_irq(pdev, 0); 618 if (irq < 0) { 619 dev_err(&pdev->dev, "missing interrupt resource\n"); 620 return irq; 621 } 622 623 idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c"); 624 if (IS_ERR(idev->i2c_clk)) { 625 dev_err(&pdev->dev, "missing clock\n"); 626 return PTR_ERR(idev->i2c_clk); 627 } 628 629 idev->base = base; 630 idev->dev = &pdev->dev; 631 init_completion(&idev->msg_complete); 632 633 of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate); 634 if (idev->bus_clk_rate == 0) 635 idev->bus_clk_rate = 100000; /* default clock rate */ 636 637 ret = clk_prepare_enable(idev->i2c_clk); 638 if (ret) { 639 dev_err(&pdev->dev, "failed to enable clock\n"); 640 return ret; 641 } 642 643 ret = axxia_i2c_init(idev); 644 if (ret) { 645 dev_err(&pdev->dev, "failed to initialize\n"); 646 goto error_disable_clk; 647 } 648 649 ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0, 650 pdev->name, idev); 651 if (ret) { 652 dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq); 653 goto error_disable_clk; 654 } 655 656 i2c_set_adapdata(&idev->adapter, idev); 657 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 658 idev->adapter.owner = THIS_MODULE; 659 idev->adapter.algo = &axxia_i2c_algo; 660 idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info; 661 idev->adapter.quirks = &axxia_i2c_quirks; 662 idev->adapter.dev.parent = &pdev->dev; 663 idev->adapter.dev.of_node = pdev->dev.of_node; 664 665 platform_set_drvdata(pdev, idev); 666 667 ret = i2c_add_adapter(&idev->adapter); 668 if (ret) 669 goto error_disable_clk; 670 671 return 0; 672 673 error_disable_clk: 674 clk_disable_unprepare(idev->i2c_clk); 675 return ret; 676 } 677 678 static int axxia_i2c_remove(struct platform_device *pdev) 679 { 680 struct axxia_i2c_dev *idev = platform_get_drvdata(pdev); 681 682 clk_disable_unprepare(idev->i2c_clk); 683 i2c_del_adapter(&idev->adapter); 684 685 return 0; 686 } 687 688 /* Match table for of_platform binding */ 689 static const struct of_device_id axxia_i2c_of_match[] = { 690 { .compatible = "lsi,api2c", }, 691 {}, 692 }; 693 694 MODULE_DEVICE_TABLE(of, axxia_i2c_of_match); 695 696 static struct platform_driver axxia_i2c_driver = { 697 .probe = axxia_i2c_probe, 698 .remove = axxia_i2c_remove, 699 .driver = { 700 .name = "axxia-i2c", 701 .of_match_table = axxia_i2c_of_match, 702 }, 703 }; 704 705 module_platform_driver(axxia_i2c_driver); 706 707 MODULE_DESCRIPTION("Axxia I2C Bus driver"); 708 MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>"); 709 MODULE_LICENSE("GPL v2"); 710