1 /* 2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface 3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> 4 * 5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org> 6 * 7 * The documentation describes this as an SMBus controller, but it doesn't 8 * understand any of the SMBus protocol in hardware. It's really an I2C 9 * controller that could emulate most of the SMBus in software. 10 * 11 * This is just a skeleton adapter to use with the Au1550 PSC 12 * algorithm. It was developed for the Pb1550, but will work with 13 * any Au1550 board that has a similar PSC configuration. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 2 18 * of the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 28 */ 29 30 #include <linux/delay.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/platform_device.h> 34 #include <linux/errno.h> 35 #include <linux/i2c.h> 36 #include <linux/slab.h> 37 38 #include <asm/mach-au1x00/au1000.h> 39 #include <asm/mach-au1x00/au1xxx_psc.h> 40 41 #define PSC_SEL 0x00 42 #define PSC_CTRL 0x04 43 #define PSC_SMBCFG 0x08 44 #define PSC_SMBMSK 0x0C 45 #define PSC_SMBPCR 0x10 46 #define PSC_SMBSTAT 0x14 47 #define PSC_SMBEVNT 0x18 48 #define PSC_SMBTXRX 0x1C 49 #define PSC_SMBTMR 0x20 50 51 struct i2c_au1550_data { 52 void __iomem *psc_base; 53 int xfer_timeout; 54 struct i2c_adapter adap; 55 struct resource *ioarea; 56 }; 57 58 static inline void WR(struct i2c_au1550_data *a, int r, unsigned long v) 59 { 60 __raw_writel(v, a->psc_base + r); 61 wmb(); 62 } 63 64 static inline unsigned long RD(struct i2c_au1550_data *a, int r) 65 { 66 return __raw_readl(a->psc_base + r); 67 } 68 69 static int wait_xfer_done(struct i2c_au1550_data *adap) 70 { 71 int i; 72 73 /* Wait for Tx Buffer Empty */ 74 for (i = 0; i < adap->xfer_timeout; i++) { 75 if (RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_TE) 76 return 0; 77 78 udelay(1); 79 } 80 81 return -ETIMEDOUT; 82 } 83 84 static int wait_ack(struct i2c_au1550_data *adap) 85 { 86 unsigned long stat; 87 88 if (wait_xfer_done(adap)) 89 return -ETIMEDOUT; 90 91 stat = RD(adap, PSC_SMBEVNT); 92 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) 93 return -ETIMEDOUT; 94 95 return 0; 96 } 97 98 static int wait_master_done(struct i2c_au1550_data *adap) 99 { 100 int i; 101 102 /* Wait for Master Done. */ 103 for (i = 0; i < 2 * adap->xfer_timeout; i++) { 104 if ((RD(adap, PSC_SMBEVNT) & PSC_SMBEVNT_MD) != 0) 105 return 0; 106 udelay(1); 107 } 108 109 return -ETIMEDOUT; 110 } 111 112 static int 113 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd, int q) 114 { 115 unsigned long stat; 116 117 /* Reset the FIFOs, clear events. */ 118 stat = RD(adap, PSC_SMBSTAT); 119 WR(adap, PSC_SMBEVNT, PSC_SMBEVNT_ALLCLR); 120 121 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { 122 WR(adap, PSC_SMBPCR, PSC_SMBPCR_DC); 123 while ((RD(adap, PSC_SMBPCR) & PSC_SMBPCR_DC) != 0) 124 cpu_relax(); 125 udelay(50); 126 } 127 128 /* Write out the i2c chip address and specify operation */ 129 addr <<= 1; 130 if (rd) 131 addr |= 1; 132 133 /* zero-byte xfers stop immediately */ 134 if (q) 135 addr |= PSC_SMBTXRX_STP; 136 137 /* Put byte into fifo, start up master. */ 138 WR(adap, PSC_SMBTXRX, addr); 139 WR(adap, PSC_SMBPCR, PSC_SMBPCR_MS); 140 if (wait_ack(adap)) 141 return -EIO; 142 return (q) ? wait_master_done(adap) : 0; 143 } 144 145 static int wait_for_rx_byte(struct i2c_au1550_data *adap, unsigned char *out) 146 { 147 int j; 148 149 if (wait_xfer_done(adap)) 150 return -EIO; 151 152 j = adap->xfer_timeout * 100; 153 do { 154 j--; 155 if (j <= 0) 156 return -EIO; 157 158 if ((RD(adap, PSC_SMBSTAT) & PSC_SMBSTAT_RE) == 0) 159 j = 0; 160 else 161 udelay(1); 162 } while (j > 0); 163 164 *out = RD(adap, PSC_SMBTXRX); 165 166 return 0; 167 } 168 169 static int i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, 170 unsigned int len) 171 { 172 int i; 173 174 if (len == 0) 175 return 0; 176 177 /* A read is performed by stuffing the transmit fifo with 178 * zero bytes for timing, waiting for bytes to appear in the 179 * receive fifo, then reading the bytes. 180 */ 181 i = 0; 182 while (i < (len - 1)) { 183 WR(adap, PSC_SMBTXRX, 0); 184 if (wait_for_rx_byte(adap, &buf[i])) 185 return -EIO; 186 187 i++; 188 } 189 190 /* The last byte has to indicate transfer done. */ 191 WR(adap, PSC_SMBTXRX, PSC_SMBTXRX_STP); 192 if (wait_master_done(adap)) 193 return -EIO; 194 195 buf[i] = (unsigned char)(RD(adap, PSC_SMBTXRX) & 0xff); 196 return 0; 197 } 198 199 static int i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, 200 unsigned int len) 201 { 202 int i; 203 unsigned long data; 204 205 if (len == 0) 206 return 0; 207 208 i = 0; 209 while (i < (len-1)) { 210 data = buf[i]; 211 WR(adap, PSC_SMBTXRX, data); 212 if (wait_ack(adap)) 213 return -EIO; 214 i++; 215 } 216 217 /* The last byte has to indicate transfer done. */ 218 data = buf[i]; 219 data |= PSC_SMBTXRX_STP; 220 WR(adap, PSC_SMBTXRX, data); 221 if (wait_master_done(adap)) 222 return -EIO; 223 return 0; 224 } 225 226 static int 227 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) 228 { 229 struct i2c_au1550_data *adap = i2c_adap->algo_data; 230 struct i2c_msg *p; 231 int i, err = 0; 232 233 WR(adap, PSC_CTRL, PSC_CTRL_ENABLE); 234 235 for (i = 0; !err && i < num; i++) { 236 p = &msgs[i]; 237 err = do_address(adap, p->addr, p->flags & I2C_M_RD, 238 (p->len == 0)); 239 if (err || !p->len) 240 continue; 241 if (p->flags & I2C_M_RD) 242 err = i2c_read(adap, p->buf, p->len); 243 else 244 err = i2c_write(adap, p->buf, p->len); 245 } 246 247 /* Return the number of messages processed, or the error code. 248 */ 249 if (err == 0) 250 err = num; 251 252 WR(adap, PSC_CTRL, PSC_CTRL_SUSPEND); 253 254 return err; 255 } 256 257 static u32 au1550_func(struct i2c_adapter *adap) 258 { 259 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 260 } 261 262 static const struct i2c_algorithm au1550_algo = { 263 .master_xfer = au1550_xfer, 264 .functionality = au1550_func, 265 }; 266 267 static void i2c_au1550_setup(struct i2c_au1550_data *priv) 268 { 269 unsigned long cfg; 270 271 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); 272 WR(priv, PSC_SEL, PSC_SEL_PS_SMBUSMODE); 273 WR(priv, PSC_SMBCFG, 0); 274 WR(priv, PSC_CTRL, PSC_CTRL_ENABLE); 275 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) 276 cpu_relax(); 277 278 cfg = PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | PSC_SMBCFG_DD_DISABLE; 279 WR(priv, PSC_SMBCFG, cfg); 280 281 /* Divide by 8 to get a 6.25 MHz clock. The later protocol 282 * timings are based on this clock. 283 */ 284 cfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); 285 WR(priv, PSC_SMBCFG, cfg); 286 WR(priv, PSC_SMBMSK, PSC_SMBMSK_ALLMASK); 287 288 /* Set the protocol timer values. See Table 71 in the 289 * Au1550 Data Book for standard timing values. 290 */ 291 WR(priv, PSC_SMBTMR, PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ 292 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ 293 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ 294 PSC_SMBTMR_SET_CH(15)); 295 296 cfg |= PSC_SMBCFG_DE_ENABLE; 297 WR(priv, PSC_SMBCFG, cfg); 298 while ((RD(priv, PSC_SMBSTAT) & PSC_SMBSTAT_SR) == 0) 299 cpu_relax(); 300 301 WR(priv, PSC_CTRL, PSC_CTRL_SUSPEND); 302 } 303 304 static void i2c_au1550_disable(struct i2c_au1550_data *priv) 305 { 306 WR(priv, PSC_SMBCFG, 0); 307 WR(priv, PSC_CTRL, PSC_CTRL_DISABLE); 308 } 309 310 /* 311 * registering functions to load algorithms at runtime 312 * Prior to calling us, the 50MHz clock frequency and routing 313 * must have been set up for the PSC indicated by the adapter. 314 */ 315 static int 316 i2c_au1550_probe(struct platform_device *pdev) 317 { 318 struct i2c_au1550_data *priv; 319 struct resource *r; 320 int ret; 321 322 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 323 if (!r) { 324 ret = -ENODEV; 325 goto out; 326 } 327 328 priv = kzalloc(sizeof(struct i2c_au1550_data), GFP_KERNEL); 329 if (!priv) { 330 ret = -ENOMEM; 331 goto out; 332 } 333 334 priv->ioarea = request_mem_region(r->start, resource_size(r), 335 pdev->name); 336 if (!priv->ioarea) { 337 ret = -EBUSY; 338 goto out_mem; 339 } 340 341 priv->psc_base = ioremap(r->start, resource_size(r)); 342 if (!priv->psc_base) { 343 ret = -EIO; 344 goto out_map; 345 } 346 priv->xfer_timeout = 200; 347 348 priv->adap.nr = pdev->id; 349 priv->adap.algo = &au1550_algo; 350 priv->adap.algo_data = priv; 351 priv->adap.dev.parent = &pdev->dev; 352 strlcpy(priv->adap.name, "Au1xxx PSC I2C", sizeof(priv->adap.name)); 353 354 /* Now, set up the PSC for SMBus PIO mode. */ 355 i2c_au1550_setup(priv); 356 357 ret = i2c_add_numbered_adapter(&priv->adap); 358 if (ret == 0) { 359 platform_set_drvdata(pdev, priv); 360 return 0; 361 } 362 363 i2c_au1550_disable(priv); 364 iounmap(priv->psc_base); 365 out_map: 366 release_resource(priv->ioarea); 367 kfree(priv->ioarea); 368 out_mem: 369 kfree(priv); 370 out: 371 return ret; 372 } 373 374 static int i2c_au1550_remove(struct platform_device *pdev) 375 { 376 struct i2c_au1550_data *priv = platform_get_drvdata(pdev); 377 378 i2c_del_adapter(&priv->adap); 379 i2c_au1550_disable(priv); 380 iounmap(priv->psc_base); 381 release_resource(priv->ioarea); 382 kfree(priv->ioarea); 383 kfree(priv); 384 return 0; 385 } 386 387 #ifdef CONFIG_PM 388 static int i2c_au1550_suspend(struct device *dev) 389 { 390 struct i2c_au1550_data *priv = dev_get_drvdata(dev); 391 392 i2c_au1550_disable(priv); 393 394 return 0; 395 } 396 397 static int i2c_au1550_resume(struct device *dev) 398 { 399 struct i2c_au1550_data *priv = dev_get_drvdata(dev); 400 401 i2c_au1550_setup(priv); 402 403 return 0; 404 } 405 406 static const struct dev_pm_ops i2c_au1550_pmops = { 407 .suspend = i2c_au1550_suspend, 408 .resume = i2c_au1550_resume, 409 }; 410 411 #define AU1XPSC_SMBUS_PMOPS (&i2c_au1550_pmops) 412 413 #else 414 #define AU1XPSC_SMBUS_PMOPS NULL 415 #endif 416 417 static struct platform_driver au1xpsc_smbus_driver = { 418 .driver = { 419 .name = "au1xpsc_smbus", 420 .owner = THIS_MODULE, 421 .pm = AU1XPSC_SMBUS_PMOPS, 422 }, 423 .probe = i2c_au1550_probe, 424 .remove = i2c_au1550_remove, 425 }; 426 427 module_platform_driver(au1xpsc_smbus_driver); 428 429 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); 430 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); 431 MODULE_LICENSE("GPL"); 432 MODULE_ALIAS("platform:au1xpsc_smbus"); 433