1 /* 2 * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface 3 * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com> 4 * 5 * 2.6 port by Matt Porter <mporter@kernel.crashing.org> 6 * 7 * The documentation describes this as an SMBus controller, but it doesn't 8 * understand any of the SMBus protocol in hardware. It's really an I2C 9 * controller that could emulate most of the SMBus in software. 10 * 11 * This is just a skeleton adapter to use with the Au1550 PSC 12 * algorithm. It was developed for the Pb1550, but will work with 13 * any Au1550 board that has a similar PSC configuration. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License 17 * as published by the Free Software Foundation; either version 2 18 * of the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 28 */ 29 30 #include <linux/delay.h> 31 #include <linux/kernel.h> 32 #include <linux/module.h> 33 #include <linux/init.h> 34 #include <linux/errno.h> 35 #include <linux/i2c.h> 36 37 #include <asm/mach-au1x00/au1xxx.h> 38 #include <asm/mach-au1x00/au1xxx_psc.h> 39 40 #include "i2c-au1550.h" 41 42 static int 43 wait_xfer_done(struct i2c_au1550_data *adap) 44 { 45 u32 stat; 46 int i; 47 volatile psc_smb_t *sp; 48 49 sp = (volatile psc_smb_t *)(adap->psc_base); 50 51 /* Wait for Tx FIFO Underflow. 52 */ 53 for (i = 0; i < adap->xfer_timeout; i++) { 54 stat = sp->psc_smbevnt; 55 au_sync(); 56 if ((stat & PSC_SMBEVNT_TU) != 0) { 57 /* Clear it. */ 58 sp->psc_smbevnt = PSC_SMBEVNT_TU; 59 au_sync(); 60 return 0; 61 } 62 udelay(1); 63 } 64 65 return -ETIMEDOUT; 66 } 67 68 static int 69 wait_ack(struct i2c_au1550_data *adap) 70 { 71 u32 stat; 72 volatile psc_smb_t *sp; 73 74 if (wait_xfer_done(adap)) 75 return -ETIMEDOUT; 76 77 sp = (volatile psc_smb_t *)(adap->psc_base); 78 79 stat = sp->psc_smbevnt; 80 au_sync(); 81 82 if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0) 83 return -ETIMEDOUT; 84 85 return 0; 86 } 87 88 static int 89 wait_master_done(struct i2c_au1550_data *adap) 90 { 91 u32 stat; 92 int i; 93 volatile psc_smb_t *sp; 94 95 sp = (volatile psc_smb_t *)(adap->psc_base); 96 97 /* Wait for Master Done. 98 */ 99 for (i = 0; i < adap->xfer_timeout; i++) { 100 stat = sp->psc_smbevnt; 101 au_sync(); 102 if ((stat & PSC_SMBEVNT_MD) != 0) 103 return 0; 104 udelay(1); 105 } 106 107 return -ETIMEDOUT; 108 } 109 110 static int 111 do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd) 112 { 113 volatile psc_smb_t *sp; 114 u32 stat; 115 116 sp = (volatile psc_smb_t *)(adap->psc_base); 117 118 /* Reset the FIFOs, clear events. 119 */ 120 stat = sp->psc_smbstat; 121 sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR; 122 au_sync(); 123 124 if (!(stat & PSC_SMBSTAT_TE) || !(stat & PSC_SMBSTAT_RE)) { 125 sp->psc_smbpcr = PSC_SMBPCR_DC; 126 au_sync(); 127 do { 128 stat = sp->psc_smbpcr; 129 au_sync(); 130 } while ((stat & PSC_SMBPCR_DC) != 0); 131 udelay(50); 132 } 133 134 /* Write out the i2c chip address and specify operation 135 */ 136 addr <<= 1; 137 if (rd) 138 addr |= 1; 139 140 /* Put byte into fifo, start up master. 141 */ 142 sp->psc_smbtxrx = addr; 143 au_sync(); 144 sp->psc_smbpcr = PSC_SMBPCR_MS; 145 au_sync(); 146 if (wait_ack(adap)) 147 return -EIO; 148 return 0; 149 } 150 151 static u32 152 wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data) 153 { 154 int j; 155 u32 data, stat; 156 volatile psc_smb_t *sp; 157 158 if (wait_xfer_done(adap)) 159 return -EIO; 160 161 sp = (volatile psc_smb_t *)(adap->psc_base); 162 163 j = adap->xfer_timeout * 100; 164 do { 165 j--; 166 if (j <= 0) 167 return -EIO; 168 169 stat = sp->psc_smbstat; 170 au_sync(); 171 if ((stat & PSC_SMBSTAT_RE) == 0) 172 j = 0; 173 else 174 udelay(1); 175 } while (j > 0); 176 data = sp->psc_smbtxrx; 177 au_sync(); 178 *ret_data = data; 179 180 return 0; 181 } 182 183 static int 184 i2c_read(struct i2c_au1550_data *adap, unsigned char *buf, 185 unsigned int len) 186 { 187 int i; 188 u32 data; 189 volatile psc_smb_t *sp; 190 191 if (len == 0) 192 return 0; 193 194 /* A read is performed by stuffing the transmit fifo with 195 * zero bytes for timing, waiting for bytes to appear in the 196 * receive fifo, then reading the bytes. 197 */ 198 199 sp = (volatile psc_smb_t *)(adap->psc_base); 200 201 i = 0; 202 while (i < (len-1)) { 203 sp->psc_smbtxrx = 0; 204 au_sync(); 205 if (wait_for_rx_byte(adap, &data)) 206 return -EIO; 207 208 buf[i] = data; 209 i++; 210 } 211 212 /* The last byte has to indicate transfer done. 213 */ 214 sp->psc_smbtxrx = PSC_SMBTXRX_STP; 215 au_sync(); 216 if (wait_master_done(adap)) 217 return -EIO; 218 219 data = sp->psc_smbtxrx; 220 au_sync(); 221 buf[i] = data; 222 return 0; 223 } 224 225 static int 226 i2c_write(struct i2c_au1550_data *adap, unsigned char *buf, 227 unsigned int len) 228 { 229 int i; 230 u32 data; 231 volatile psc_smb_t *sp; 232 233 if (len == 0) 234 return 0; 235 236 sp = (volatile psc_smb_t *)(adap->psc_base); 237 238 i = 0; 239 while (i < (len-1)) { 240 data = buf[i]; 241 sp->psc_smbtxrx = data; 242 au_sync(); 243 if (wait_ack(adap)) 244 return -EIO; 245 i++; 246 } 247 248 /* The last byte has to indicate transfer done. 249 */ 250 data = buf[i]; 251 data |= PSC_SMBTXRX_STP; 252 sp->psc_smbtxrx = data; 253 au_sync(); 254 if (wait_master_done(adap)) 255 return -EIO; 256 return 0; 257 } 258 259 static int 260 au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num) 261 { 262 struct i2c_au1550_data *adap = i2c_adap->algo_data; 263 struct i2c_msg *p; 264 int i, err = 0; 265 266 for (i = 0; !err && i < num; i++) { 267 p = &msgs[i]; 268 err = do_address(adap, p->addr, p->flags & I2C_M_RD); 269 if (err || !p->len) 270 continue; 271 if (p->flags & I2C_M_RD) 272 err = i2c_read(adap, p->buf, p->len); 273 else 274 err = i2c_write(adap, p->buf, p->len); 275 } 276 277 /* Return the number of messages processed, or the error code. 278 */ 279 if (err == 0) 280 err = num; 281 return err; 282 } 283 284 static u32 285 au1550_func(struct i2c_adapter *adap) 286 { 287 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 288 } 289 290 static const struct i2c_algorithm au1550_algo = { 291 .master_xfer = au1550_xfer, 292 .functionality = au1550_func, 293 }; 294 295 /* 296 * registering functions to load algorithms at runtime 297 * Prior to calling us, the 50MHz clock frequency and routing 298 * must have been set up for the PSC indicated by the adapter. 299 */ 300 int 301 i2c_au1550_add_bus(struct i2c_adapter *i2c_adap) 302 { 303 struct i2c_au1550_data *adap = i2c_adap->algo_data; 304 volatile psc_smb_t *sp; 305 u32 stat; 306 307 i2c_adap->algo = &au1550_algo; 308 309 /* Now, set up the PSC for SMBus PIO mode. 310 */ 311 sp = (volatile psc_smb_t *)(adap->psc_base); 312 sp->psc_ctrl = PSC_CTRL_DISABLE; 313 au_sync(); 314 sp->psc_sel = PSC_SEL_PS_SMBUSMODE; 315 sp->psc_smbcfg = 0; 316 au_sync(); 317 sp->psc_ctrl = PSC_CTRL_ENABLE; 318 au_sync(); 319 do { 320 stat = sp->psc_smbstat; 321 au_sync(); 322 } while ((stat & PSC_SMBSTAT_SR) == 0); 323 324 sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 | 325 PSC_SMBCFG_DD_DISABLE); 326 327 /* Divide by 8 to get a 6.25 MHz clock. The later protocol 328 * timings are based on this clock. 329 */ 330 sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8); 331 sp->psc_smbmsk = PSC_SMBMSK_ALLMASK; 332 au_sync(); 333 334 /* Set the protocol timer values. See Table 71 in the 335 * Au1550 Data Book for standard timing values. 336 */ 337 sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \ 338 PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \ 339 PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \ 340 PSC_SMBTMR_SET_CH(15); 341 au_sync(); 342 343 sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE; 344 do { 345 stat = sp->psc_smbstat; 346 au_sync(); 347 } while ((stat & PSC_SMBSTAT_DR) == 0); 348 349 return i2c_add_adapter(i2c_adap); 350 } 351 352 353 int 354 i2c_au1550_del_bus(struct i2c_adapter *adap) 355 { 356 return i2c_del_adapter(adap); 357 } 358 359 static int 360 pb1550_reg(struct i2c_client *client) 361 { 362 return 0; 363 } 364 365 static int 366 pb1550_unreg(struct i2c_client *client) 367 { 368 return 0; 369 } 370 371 static struct i2c_au1550_data pb1550_i2c_info = { 372 SMBUS_PSC_BASE, 200, 200 373 }; 374 375 static struct i2c_adapter pb1550_board_adapter = { 376 name: "pb1550 adapter", 377 id: I2C_HW_AU1550_PSC, 378 algo: NULL, 379 algo_data: &pb1550_i2c_info, 380 client_register: pb1550_reg, 381 client_unregister: pb1550_unreg, 382 }; 383 384 /* BIG hack to support the control interface on the Wolfson WM8731 385 * audio codec on the Pb1550 board. We get an address and two data 386 * bytes to write, create an i2c message, and send it across the 387 * i2c transfer function. We do this here because we have access to 388 * the i2c adapter structure. 389 */ 390 static struct i2c_msg wm_i2c_msg; /* We don't want this stuff on the stack */ 391 static u8 i2cbuf[2]; 392 393 int 394 pb1550_wm_codec_write(u8 addr, u8 reg, u8 val) 395 { 396 wm_i2c_msg.addr = addr; 397 wm_i2c_msg.flags = 0; 398 wm_i2c_msg.buf = i2cbuf; 399 wm_i2c_msg.len = 2; 400 i2cbuf[0] = reg; 401 i2cbuf[1] = val; 402 403 return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1); 404 } 405 406 static int __init 407 i2c_au1550_init(void) 408 { 409 printk(KERN_INFO "Au1550 I2C: "); 410 411 /* This is where we would set up a 50MHz clock source 412 * and routing. On the Pb1550, the SMBus is PSC2, which 413 * uses a shared clock with USB. This has been already 414 * configured by Yamon as a 48MHz clock, close enough 415 * for our work. 416 */ 417 if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) { 418 printk("failed to initialize.\n"); 419 return -ENODEV; 420 } 421 422 printk("initialized.\n"); 423 return 0; 424 } 425 426 static void __exit 427 i2c_au1550_exit(void) 428 { 429 i2c_au1550_del_bus(&pb1550_board_adapter); 430 } 431 432 MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC."); 433 MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550"); 434 MODULE_LICENSE("GPL"); 435 436 module_init (i2c_au1550_init); 437 module_exit (i2c_au1550_exit); 438