1 /* 2 * Aspeed 24XX/25XX I2C Controller. 3 * 4 * Copyright (C) 2012-2017 ASPEED Technology Inc. 5 * Copyright 2017 IBM Corporation 6 * Copyright 2017 Google, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/completion.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/slab.h> 31 32 /* I2C Register */ 33 #define ASPEED_I2C_FUN_CTRL_REG 0x00 34 #define ASPEED_I2C_AC_TIMING_REG1 0x04 35 #define ASPEED_I2C_AC_TIMING_REG2 0x08 36 #define ASPEED_I2C_INTR_CTRL_REG 0x0c 37 #define ASPEED_I2C_INTR_STS_REG 0x10 38 #define ASPEED_I2C_CMD_REG 0x14 39 #define ASPEED_I2C_DEV_ADDR_REG 0x18 40 #define ASPEED_I2C_BYTE_BUF_REG 0x20 41 42 /* Global Register Definition */ 43 /* 0x00 : I2C Interrupt Status Register */ 44 /* 0x08 : I2C Interrupt Target Assignment */ 45 46 /* Device Register Definition */ 47 /* 0x00 : I2CD Function Control Register */ 48 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15) 49 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8) 50 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7) 51 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6) 52 #define ASPEED_I2CD_SLAVE_EN BIT(1) 53 #define ASPEED_I2CD_MASTER_EN BIT(0) 54 55 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */ 56 #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28) 57 #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24) 58 #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20) 59 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16 60 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16) 61 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12 62 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12) 63 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0) 64 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0) 65 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ 66 #define ASPEED_NO_TIMEOUT_CTRL 0 67 68 /* 0x0c : I2CD Interrupt Control Register & 69 * 0x10 : I2CD Interrupt Status Register 70 * 71 * These share bit definitions, so use the same values for the enable & 72 * status bits. 73 */ 74 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14) 75 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13) 76 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7) 77 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6) 78 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5) 79 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4) 80 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3) 81 #define ASPEED_I2CD_INTR_RX_DONE BIT(2) 82 #define ASPEED_I2CD_INTR_TX_NAK BIT(1) 83 #define ASPEED_I2CD_INTR_TX_ACK BIT(0) 84 #define ASPEED_I2CD_INTR_ALL \ 85 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \ 86 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \ 87 ASPEED_I2CD_INTR_SCL_TIMEOUT | \ 88 ASPEED_I2CD_INTR_ABNORMAL | \ 89 ASPEED_I2CD_INTR_NORMAL_STOP | \ 90 ASPEED_I2CD_INTR_ARBIT_LOSS | \ 91 ASPEED_I2CD_INTR_RX_DONE | \ 92 ASPEED_I2CD_INTR_TX_NAK | \ 93 ASPEED_I2CD_INTR_TX_ACK) 94 95 /* 0x14 : I2CD Command/Status Register */ 96 #define ASPEED_I2CD_SCL_LINE_STS BIT(18) 97 #define ASPEED_I2CD_SDA_LINE_STS BIT(17) 98 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16) 99 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11) 100 101 /* Command Bit */ 102 #define ASPEED_I2CD_M_STOP_CMD BIT(5) 103 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4) 104 #define ASPEED_I2CD_M_RX_CMD BIT(3) 105 #define ASPEED_I2CD_S_TX_CMD BIT(2) 106 #define ASPEED_I2CD_M_TX_CMD BIT(1) 107 #define ASPEED_I2CD_M_START_CMD BIT(0) 108 109 /* 0x18 : I2CD Slave Device Address Register */ 110 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0) 111 112 enum aspeed_i2c_master_state { 113 ASPEED_I2C_MASTER_START, 114 ASPEED_I2C_MASTER_TX_FIRST, 115 ASPEED_I2C_MASTER_TX, 116 ASPEED_I2C_MASTER_RX_FIRST, 117 ASPEED_I2C_MASTER_RX, 118 ASPEED_I2C_MASTER_STOP, 119 ASPEED_I2C_MASTER_INACTIVE, 120 }; 121 122 enum aspeed_i2c_slave_state { 123 ASPEED_I2C_SLAVE_START, 124 ASPEED_I2C_SLAVE_READ_REQUESTED, 125 ASPEED_I2C_SLAVE_READ_PROCESSED, 126 ASPEED_I2C_SLAVE_WRITE_REQUESTED, 127 ASPEED_I2C_SLAVE_WRITE_RECEIVED, 128 ASPEED_I2C_SLAVE_STOP, 129 }; 130 131 struct aspeed_i2c_bus { 132 struct i2c_adapter adap; 133 struct device *dev; 134 void __iomem *base; 135 /* Synchronizes I/O mem access to base. */ 136 spinlock_t lock; 137 struct completion cmd_complete; 138 u32 (*get_clk_reg_val)(u32 divisor); 139 unsigned long parent_clk_frequency; 140 u32 bus_frequency; 141 /* Transaction state. */ 142 enum aspeed_i2c_master_state master_state; 143 struct i2c_msg *msgs; 144 size_t buf_index; 145 size_t msgs_index; 146 size_t msgs_count; 147 bool send_stop; 148 int cmd_err; 149 /* Protected only by i2c_lock_bus */ 150 int master_xfer_result; 151 #if IS_ENABLED(CONFIG_I2C_SLAVE) 152 struct i2c_client *slave; 153 enum aspeed_i2c_slave_state slave_state; 154 #endif /* CONFIG_I2C_SLAVE */ 155 }; 156 157 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus); 158 159 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus) 160 { 161 unsigned long time_left, flags; 162 int ret = 0; 163 u32 command; 164 165 spin_lock_irqsave(&bus->lock, flags); 166 command = readl(bus->base + ASPEED_I2C_CMD_REG); 167 168 if (command & ASPEED_I2CD_SDA_LINE_STS) { 169 /* Bus is idle: no recovery needed. */ 170 if (command & ASPEED_I2CD_SCL_LINE_STS) 171 goto out; 172 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n", 173 command); 174 175 reinit_completion(&bus->cmd_complete); 176 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); 177 spin_unlock_irqrestore(&bus->lock, flags); 178 179 time_left = wait_for_completion_timeout( 180 &bus->cmd_complete, bus->adap.timeout); 181 182 spin_lock_irqsave(&bus->lock, flags); 183 if (time_left == 0) 184 goto reset_out; 185 else if (bus->cmd_err) 186 goto reset_out; 187 /* Recovery failed. */ 188 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & 189 ASPEED_I2CD_SCL_LINE_STS)) 190 goto reset_out; 191 /* Bus error. */ 192 } else { 193 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n", 194 command); 195 196 reinit_completion(&bus->cmd_complete); 197 /* Writes 1 to 8 SCL clock cycles until SDA is released. */ 198 writel(ASPEED_I2CD_BUS_RECOVER_CMD, 199 bus->base + ASPEED_I2C_CMD_REG); 200 spin_unlock_irqrestore(&bus->lock, flags); 201 202 time_left = wait_for_completion_timeout( 203 &bus->cmd_complete, bus->adap.timeout); 204 205 spin_lock_irqsave(&bus->lock, flags); 206 if (time_left == 0) 207 goto reset_out; 208 else if (bus->cmd_err) 209 goto reset_out; 210 /* Recovery failed. */ 211 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & 212 ASPEED_I2CD_SDA_LINE_STS)) 213 goto reset_out; 214 } 215 216 out: 217 spin_unlock_irqrestore(&bus->lock, flags); 218 219 return ret; 220 221 reset_out: 222 spin_unlock_irqrestore(&bus->lock, flags); 223 224 return aspeed_i2c_reset(bus); 225 } 226 227 #if IS_ENABLED(CONFIG_I2C_SLAVE) 228 static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus) 229 { 230 u32 command, irq_status, status_ack = 0; 231 struct i2c_client *slave = bus->slave; 232 bool irq_handled = true; 233 u8 value; 234 235 spin_lock(&bus->lock); 236 if (!slave) { 237 irq_handled = false; 238 goto out; 239 } 240 241 command = readl(bus->base + ASPEED_I2C_CMD_REG); 242 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG); 243 244 /* Slave was requested, restart state machine. */ 245 if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) { 246 status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH; 247 bus->slave_state = ASPEED_I2C_SLAVE_START; 248 } 249 250 /* Slave is not currently active, irq was for someone else. */ 251 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) { 252 irq_handled = false; 253 goto out; 254 } 255 256 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n", 257 irq_status, command); 258 259 /* Slave was sent something. */ 260 if (irq_status & ASPEED_I2CD_INTR_RX_DONE) { 261 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; 262 /* Handle address frame. */ 263 if (bus->slave_state == ASPEED_I2C_SLAVE_START) { 264 if (value & 0x1) 265 bus->slave_state = 266 ASPEED_I2C_SLAVE_READ_REQUESTED; 267 else 268 bus->slave_state = 269 ASPEED_I2C_SLAVE_WRITE_REQUESTED; 270 } 271 status_ack |= ASPEED_I2CD_INTR_RX_DONE; 272 } 273 274 /* Slave was asked to stop. */ 275 if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) { 276 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP; 277 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 278 } 279 if (irq_status & ASPEED_I2CD_INTR_TX_NAK) { 280 status_ack |= ASPEED_I2CD_INTR_TX_NAK; 281 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 282 } 283 284 switch (bus->slave_state) { 285 case ASPEED_I2C_SLAVE_READ_REQUESTED: 286 if (irq_status & ASPEED_I2CD_INTR_TX_ACK) 287 dev_err(bus->dev, "Unexpected ACK on read request.\n"); 288 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED; 289 290 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 291 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); 292 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); 293 break; 294 case ASPEED_I2C_SLAVE_READ_PROCESSED: 295 status_ack |= ASPEED_I2CD_INTR_TX_ACK; 296 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK)) 297 dev_err(bus->dev, 298 "Expected ACK after processed read.\n"); 299 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 300 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); 301 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); 302 break; 303 case ASPEED_I2C_SLAVE_WRITE_REQUESTED: 304 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED; 305 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 306 break; 307 case ASPEED_I2C_SLAVE_WRITE_RECEIVED: 308 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value); 309 break; 310 case ASPEED_I2C_SLAVE_STOP: 311 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 312 break; 313 default: 314 dev_err(bus->dev, "unhandled slave_state: %d\n", 315 bus->slave_state); 316 break; 317 } 318 319 if (status_ack != irq_status) 320 dev_err(bus->dev, 321 "irq handled != irq. expected %x, but was %x\n", 322 irq_status, status_ack); 323 writel(status_ack, bus->base + ASPEED_I2C_INTR_STS_REG); 324 325 out: 326 spin_unlock(&bus->lock); 327 return irq_handled; 328 } 329 #endif /* CONFIG_I2C_SLAVE */ 330 331 /* precondition: bus.lock has been acquired. */ 332 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus) 333 { 334 u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD; 335 struct i2c_msg *msg = &bus->msgs[bus->msgs_index]; 336 u8 slave_addr = msg->addr << 1; 337 338 bus->master_state = ASPEED_I2C_MASTER_START; 339 bus->buf_index = 0; 340 341 if (msg->flags & I2C_M_RD) { 342 slave_addr |= 1; 343 command |= ASPEED_I2CD_M_RX_CMD; 344 /* Need to let the hardware know to NACK after RX. */ 345 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) 346 command |= ASPEED_I2CD_M_S_RX_CMD_LAST; 347 } 348 349 writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG); 350 writel(command, bus->base + ASPEED_I2C_CMD_REG); 351 } 352 353 /* precondition: bus.lock has been acquired. */ 354 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus) 355 { 356 bus->master_state = ASPEED_I2C_MASTER_STOP; 357 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); 358 } 359 360 /* precondition: bus.lock has been acquired. */ 361 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus) 362 { 363 if (bus->msgs_index + 1 < bus->msgs_count) { 364 bus->msgs_index++; 365 aspeed_i2c_do_start(bus); 366 } else { 367 aspeed_i2c_do_stop(bus); 368 } 369 } 370 371 static int aspeed_i2c_is_irq_error(u32 irq_status) 372 { 373 if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS) 374 return -EAGAIN; 375 if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | 376 ASPEED_I2CD_INTR_SCL_TIMEOUT)) 377 return -EBUSY; 378 if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL)) 379 return -EPROTO; 380 381 return 0; 382 } 383 384 static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus) 385 { 386 u32 irq_status, status_ack = 0, command = 0; 387 struct i2c_msg *msg; 388 u8 recv_byte; 389 int ret; 390 391 spin_lock(&bus->lock); 392 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG); 393 /* Ack all interrupt bits. */ 394 writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG); 395 396 if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) { 397 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 398 status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE; 399 goto out_complete; 400 } 401 402 /* 403 * We encountered an interrupt that reports an error: the hardware 404 * should clear the command queue effectively taking us back to the 405 * INACTIVE state. 406 */ 407 ret = aspeed_i2c_is_irq_error(irq_status); 408 if (ret < 0) { 409 dev_dbg(bus->dev, "received error interrupt: 0x%08x", 410 irq_status); 411 bus->cmd_err = ret; 412 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 413 goto out_complete; 414 } 415 416 /* We are in an invalid state; reset bus to a known state. */ 417 if (!bus->msgs) { 418 dev_err(bus->dev, "bus in unknown state"); 419 bus->cmd_err = -EIO; 420 if (bus->master_state != ASPEED_I2C_MASTER_STOP) 421 aspeed_i2c_do_stop(bus); 422 goto out_no_complete; 423 } 424 msg = &bus->msgs[bus->msgs_index]; 425 426 /* 427 * START is a special case because we still have to handle a subsequent 428 * TX or RX immediately after we handle it, so we handle it here and 429 * then update the state and handle the new state below. 430 */ 431 if (bus->master_state == ASPEED_I2C_MASTER_START) { 432 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { 433 pr_devel("no slave present at %02x", msg->addr); 434 status_ack |= ASPEED_I2CD_INTR_TX_NAK; 435 bus->cmd_err = -ENXIO; 436 aspeed_i2c_do_stop(bus); 437 goto out_no_complete; 438 } 439 status_ack |= ASPEED_I2CD_INTR_TX_ACK; 440 if (msg->len == 0) { /* SMBUS_QUICK */ 441 aspeed_i2c_do_stop(bus); 442 goto out_no_complete; 443 } 444 if (msg->flags & I2C_M_RD) 445 bus->master_state = ASPEED_I2C_MASTER_RX_FIRST; 446 else 447 bus->master_state = ASPEED_I2C_MASTER_TX_FIRST; 448 } 449 450 switch (bus->master_state) { 451 case ASPEED_I2C_MASTER_TX: 452 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) { 453 dev_dbg(bus->dev, "slave NACKed TX"); 454 status_ack |= ASPEED_I2CD_INTR_TX_NAK; 455 goto error_and_stop; 456 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { 457 dev_err(bus->dev, "slave failed to ACK TX"); 458 goto error_and_stop; 459 } 460 status_ack |= ASPEED_I2CD_INTR_TX_ACK; 461 /* fallthrough intended */ 462 case ASPEED_I2C_MASTER_TX_FIRST: 463 if (bus->buf_index < msg->len) { 464 bus->master_state = ASPEED_I2C_MASTER_TX; 465 writel(msg->buf[bus->buf_index++], 466 bus->base + ASPEED_I2C_BYTE_BUF_REG); 467 writel(ASPEED_I2CD_M_TX_CMD, 468 bus->base + ASPEED_I2C_CMD_REG); 469 } else { 470 aspeed_i2c_next_msg_or_stop(bus); 471 } 472 goto out_no_complete; 473 case ASPEED_I2C_MASTER_RX_FIRST: 474 /* RX may not have completed yet (only address cycle) */ 475 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE)) 476 goto out_no_complete; 477 /* fallthrough intended */ 478 case ASPEED_I2C_MASTER_RX: 479 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) { 480 dev_err(bus->dev, "master failed to RX"); 481 goto error_and_stop; 482 } 483 status_ack |= ASPEED_I2CD_INTR_RX_DONE; 484 485 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; 486 msg->buf[bus->buf_index++] = recv_byte; 487 488 if (msg->flags & I2C_M_RECV_LEN) { 489 if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) { 490 bus->cmd_err = -EPROTO; 491 aspeed_i2c_do_stop(bus); 492 goto out_no_complete; 493 } 494 msg->len = recv_byte + 495 ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1); 496 msg->flags &= ~I2C_M_RECV_LEN; 497 } 498 499 if (bus->buf_index < msg->len) { 500 bus->master_state = ASPEED_I2C_MASTER_RX; 501 command = ASPEED_I2CD_M_RX_CMD; 502 if (bus->buf_index + 1 == msg->len) 503 command |= ASPEED_I2CD_M_S_RX_CMD_LAST; 504 writel(command, bus->base + ASPEED_I2C_CMD_REG); 505 } else { 506 aspeed_i2c_next_msg_or_stop(bus); 507 } 508 goto out_no_complete; 509 case ASPEED_I2C_MASTER_STOP: 510 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) { 511 dev_err(bus->dev, "master failed to STOP"); 512 bus->cmd_err = -EIO; 513 /* Do not STOP as we have already tried. */ 514 } else { 515 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP; 516 } 517 518 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 519 goto out_complete; 520 case ASPEED_I2C_MASTER_INACTIVE: 521 dev_err(bus->dev, 522 "master received interrupt 0x%08x, but is inactive", 523 irq_status); 524 bus->cmd_err = -EIO; 525 /* Do not STOP as we should be inactive. */ 526 goto out_complete; 527 default: 528 WARN(1, "unknown master state\n"); 529 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 530 bus->cmd_err = -EINVAL; 531 goto out_complete; 532 } 533 error_and_stop: 534 bus->cmd_err = -EIO; 535 aspeed_i2c_do_stop(bus); 536 goto out_no_complete; 537 out_complete: 538 bus->msgs = NULL; 539 if (bus->cmd_err) 540 bus->master_xfer_result = bus->cmd_err; 541 else 542 bus->master_xfer_result = bus->msgs_index + 1; 543 complete(&bus->cmd_complete); 544 out_no_complete: 545 if (irq_status != status_ack) 546 dev_err(bus->dev, 547 "irq handled != irq. expected 0x%08x, but was 0x%08x\n", 548 irq_status, status_ack); 549 spin_unlock(&bus->lock); 550 return !!irq_status; 551 } 552 553 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) 554 { 555 struct aspeed_i2c_bus *bus = dev_id; 556 557 #if IS_ENABLED(CONFIG_I2C_SLAVE) 558 if (aspeed_i2c_slave_irq(bus)) { 559 dev_dbg(bus->dev, "irq handled by slave.\n"); 560 return IRQ_HANDLED; 561 } 562 #endif /* CONFIG_I2C_SLAVE */ 563 564 return aspeed_i2c_master_irq(bus) ? IRQ_HANDLED : IRQ_NONE; 565 } 566 567 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap, 568 struct i2c_msg *msgs, int num) 569 { 570 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap); 571 unsigned long time_left, flags; 572 int ret = 0; 573 574 spin_lock_irqsave(&bus->lock, flags); 575 bus->cmd_err = 0; 576 577 /* If bus is busy, attempt recovery. We assume a single master 578 * environment. 579 */ 580 if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) { 581 spin_unlock_irqrestore(&bus->lock, flags); 582 ret = aspeed_i2c_recover_bus(bus); 583 if (ret) 584 return ret; 585 spin_lock_irqsave(&bus->lock, flags); 586 } 587 588 bus->cmd_err = 0; 589 bus->msgs = msgs; 590 bus->msgs_index = 0; 591 bus->msgs_count = num; 592 593 reinit_completion(&bus->cmd_complete); 594 aspeed_i2c_do_start(bus); 595 spin_unlock_irqrestore(&bus->lock, flags); 596 597 time_left = wait_for_completion_timeout(&bus->cmd_complete, 598 bus->adap.timeout); 599 600 if (time_left == 0) 601 return -ETIMEDOUT; 602 else 603 return bus->master_xfer_result; 604 } 605 606 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap) 607 { 608 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; 609 } 610 611 #if IS_ENABLED(CONFIG_I2C_SLAVE) 612 /* precondition: bus.lock has been acquired. */ 613 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr) 614 { 615 u32 addr_reg_val, func_ctrl_reg_val; 616 617 /* Set slave addr. */ 618 addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG); 619 addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK; 620 addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK; 621 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG); 622 623 /* Turn on slave mode. */ 624 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); 625 func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN; 626 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); 627 } 628 629 static int aspeed_i2c_reg_slave(struct i2c_client *client) 630 { 631 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter); 632 unsigned long flags; 633 634 spin_lock_irqsave(&bus->lock, flags); 635 if (bus->slave) { 636 spin_unlock_irqrestore(&bus->lock, flags); 637 return -EINVAL; 638 } 639 640 __aspeed_i2c_reg_slave(bus, client->addr); 641 642 bus->slave = client; 643 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 644 spin_unlock_irqrestore(&bus->lock, flags); 645 646 return 0; 647 } 648 649 static int aspeed_i2c_unreg_slave(struct i2c_client *client) 650 { 651 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter); 652 u32 func_ctrl_reg_val; 653 unsigned long flags; 654 655 spin_lock_irqsave(&bus->lock, flags); 656 if (!bus->slave) { 657 spin_unlock_irqrestore(&bus->lock, flags); 658 return -EINVAL; 659 } 660 661 /* Turn off slave mode. */ 662 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); 663 func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN; 664 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); 665 666 bus->slave = NULL; 667 spin_unlock_irqrestore(&bus->lock, flags); 668 669 return 0; 670 } 671 #endif /* CONFIG_I2C_SLAVE */ 672 673 static const struct i2c_algorithm aspeed_i2c_algo = { 674 .master_xfer = aspeed_i2c_master_xfer, 675 .functionality = aspeed_i2c_functionality, 676 #if IS_ENABLED(CONFIG_I2C_SLAVE) 677 .reg_slave = aspeed_i2c_reg_slave, 678 .unreg_slave = aspeed_i2c_unreg_slave, 679 #endif /* CONFIG_I2C_SLAVE */ 680 }; 681 682 static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor) 683 { 684 u32 base_clk, clk_high, clk_low, tmp; 685 686 /* 687 * The actual clock frequency of SCL is: 688 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low)) 689 * = APB_freq / divisor 690 * where base_freq is a programmable clock divider; its value is 691 * base_freq = 1 << base_clk 692 * SCL_high is the number of base_freq clock cycles that SCL stays high 693 * and SCL_low is the number of base_freq clock cycles that SCL stays 694 * low for a period of SCL. 695 * The actual register has a minimum SCL_high and SCL_low minimum of 1; 696 * thus, they start counting at zero. So 697 * SCL_high = clk_high + 1 698 * SCL_low = clk_low + 1 699 * Thus, 700 * SCL_freq = APB_freq / 701 * ((1 << base_clk) * (clk_high + 1 + clk_low + 1)) 702 * The documentation recommends clk_high >= clk_high_max / 2 and 703 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint 704 * gives us the following solution: 705 */ 706 base_clk = divisor > clk_high_low_max ? 707 ilog2((divisor - 1) / clk_high_low_max) + 1 : 0; 708 tmp = (divisor + (1 << base_clk) - 1) >> base_clk; 709 clk_low = tmp / 2; 710 clk_high = tmp - clk_low; 711 712 if (clk_high) 713 clk_high--; 714 715 if (clk_low) 716 clk_low--; 717 718 719 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT) 720 & ASPEED_I2CD_TIME_SCL_HIGH_MASK) 721 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT) 722 & ASPEED_I2CD_TIME_SCL_LOW_MASK) 723 | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK); 724 } 725 726 static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor) 727 { 728 /* 729 * clk_high and clk_low are each 3 bits wide, so each can hold a max 730 * value of 8 giving a clk_high_low_max of 16. 731 */ 732 return aspeed_i2c_get_clk_reg_val(16, divisor); 733 } 734 735 static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor) 736 { 737 /* 738 * clk_high and clk_low are each 4 bits wide, so each can hold a max 739 * value of 16 giving a clk_high_low_max of 32. 740 */ 741 return aspeed_i2c_get_clk_reg_val(32, divisor); 742 } 743 744 /* precondition: bus.lock has been acquired. */ 745 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) 746 { 747 u32 divisor, clk_reg_val; 748 749 divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency); 750 clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); 751 clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK | 752 ASPEED_I2CD_TIME_THDSTA_MASK | 753 ASPEED_I2CD_TIME_TACST_MASK); 754 clk_reg_val |= bus->get_clk_reg_val(divisor); 755 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); 756 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); 757 758 return 0; 759 } 760 761 /* precondition: bus.lock has been acquired. */ 762 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, 763 struct platform_device *pdev) 764 { 765 u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN; 766 int ret; 767 768 /* Disable everything. */ 769 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); 770 771 ret = aspeed_i2c_init_clk(bus); 772 if (ret < 0) 773 return ret; 774 775 if (!of_property_read_bool(pdev->dev.of_node, "multi-master")) 776 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS; 777 778 /* Enable Master Mode */ 779 writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg, 780 bus->base + ASPEED_I2C_FUN_CTRL_REG); 781 782 #if IS_ENABLED(CONFIG_I2C_SLAVE) 783 /* If slave has already been registered, re-enable it. */ 784 if (bus->slave) 785 __aspeed_i2c_reg_slave(bus, bus->slave->addr); 786 #endif /* CONFIG_I2C_SLAVE */ 787 788 /* Set interrupt generation of I2C controller */ 789 writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG); 790 791 return 0; 792 } 793 794 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus) 795 { 796 struct platform_device *pdev = to_platform_device(bus->dev); 797 unsigned long flags; 798 int ret; 799 800 spin_lock_irqsave(&bus->lock, flags); 801 802 /* Disable and ack all interrupts. */ 803 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); 804 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); 805 806 ret = aspeed_i2c_init(bus, pdev); 807 808 spin_unlock_irqrestore(&bus->lock, flags); 809 810 return ret; 811 } 812 813 static const struct of_device_id aspeed_i2c_bus_of_table[] = { 814 { 815 .compatible = "aspeed,ast2400-i2c-bus", 816 .data = aspeed_i2c_24xx_get_clk_reg_val, 817 }, 818 { 819 .compatible = "aspeed,ast2500-i2c-bus", 820 .data = aspeed_i2c_25xx_get_clk_reg_val, 821 }, 822 { }, 823 }; 824 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table); 825 826 static int aspeed_i2c_probe_bus(struct platform_device *pdev) 827 { 828 const struct of_device_id *match; 829 struct aspeed_i2c_bus *bus; 830 struct clk *parent_clk; 831 struct resource *res; 832 int irq, ret; 833 834 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); 835 if (!bus) 836 return -ENOMEM; 837 838 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 839 bus->base = devm_ioremap_resource(&pdev->dev, res); 840 if (IS_ERR(bus->base)) 841 return PTR_ERR(bus->base); 842 843 parent_clk = devm_clk_get(&pdev->dev, NULL); 844 if (IS_ERR(parent_clk)) 845 return PTR_ERR(parent_clk); 846 bus->parent_clk_frequency = clk_get_rate(parent_clk); 847 /* We just need the clock rate, we don't actually use the clk object. */ 848 devm_clk_put(&pdev->dev, parent_clk); 849 850 ret = of_property_read_u32(pdev->dev.of_node, 851 "bus-frequency", &bus->bus_frequency); 852 if (ret < 0) { 853 dev_err(&pdev->dev, 854 "Could not read bus-frequency property\n"); 855 bus->bus_frequency = 100000; 856 } 857 858 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node); 859 if (!match) 860 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val; 861 else 862 bus->get_clk_reg_val = match->data; 863 864 /* Initialize the I2C adapter */ 865 spin_lock_init(&bus->lock); 866 init_completion(&bus->cmd_complete); 867 bus->adap.owner = THIS_MODULE; 868 bus->adap.retries = 0; 869 bus->adap.timeout = 5 * HZ; 870 bus->adap.algo = &aspeed_i2c_algo; 871 bus->adap.dev.parent = &pdev->dev; 872 bus->adap.dev.of_node = pdev->dev.of_node; 873 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); 874 i2c_set_adapdata(&bus->adap, bus); 875 876 bus->dev = &pdev->dev; 877 878 /* Clean up any left over interrupt state. */ 879 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); 880 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); 881 /* 882 * bus.lock does not need to be held because the interrupt handler has 883 * not been enabled yet. 884 */ 885 ret = aspeed_i2c_init(bus, pdev); 886 if (ret < 0) 887 return ret; 888 889 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 890 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq, 891 0, dev_name(&pdev->dev), bus); 892 if (ret < 0) 893 return ret; 894 895 ret = i2c_add_adapter(&bus->adap); 896 if (ret < 0) 897 return ret; 898 899 platform_set_drvdata(pdev, bus); 900 901 dev_info(bus->dev, "i2c bus %d registered, irq %d\n", 902 bus->adap.nr, irq); 903 904 return 0; 905 } 906 907 static int aspeed_i2c_remove_bus(struct platform_device *pdev) 908 { 909 struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev); 910 unsigned long flags; 911 912 spin_lock_irqsave(&bus->lock, flags); 913 914 /* Disable everything. */ 915 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); 916 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); 917 918 spin_unlock_irqrestore(&bus->lock, flags); 919 920 i2c_del_adapter(&bus->adap); 921 922 return 0; 923 } 924 925 static struct platform_driver aspeed_i2c_bus_driver = { 926 .probe = aspeed_i2c_probe_bus, 927 .remove = aspeed_i2c_remove_bus, 928 .driver = { 929 .name = "aspeed-i2c-bus", 930 .of_match_table = aspeed_i2c_bus_of_table, 931 }, 932 }; 933 module_platform_driver(aspeed_i2c_bus_driver); 934 935 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>"); 936 MODULE_DESCRIPTION("Aspeed I2C Bus Driver"); 937 MODULE_LICENSE("GPL v2"); 938