1 /* 2 * Aspeed 24XX/25XX I2C Controller. 3 * 4 * Copyright (C) 2012-2017 ASPEED Technology Inc. 5 * Copyright 2017 IBM Corporation 6 * Copyright 2017 Google, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/completion.h> 15 #include <linux/err.h> 16 #include <linux/errno.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/irq.h> 22 #include <linux/irqchip/chained_irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/of_address.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/reset.h> 31 #include <linux/slab.h> 32 33 /* I2C Register */ 34 #define ASPEED_I2C_FUN_CTRL_REG 0x00 35 #define ASPEED_I2C_AC_TIMING_REG1 0x04 36 #define ASPEED_I2C_AC_TIMING_REG2 0x08 37 #define ASPEED_I2C_INTR_CTRL_REG 0x0c 38 #define ASPEED_I2C_INTR_STS_REG 0x10 39 #define ASPEED_I2C_CMD_REG 0x14 40 #define ASPEED_I2C_DEV_ADDR_REG 0x18 41 #define ASPEED_I2C_BYTE_BUF_REG 0x20 42 43 /* Global Register Definition */ 44 /* 0x00 : I2C Interrupt Status Register */ 45 /* 0x08 : I2C Interrupt Target Assignment */ 46 47 /* Device Register Definition */ 48 /* 0x00 : I2CD Function Control Register */ 49 #define ASPEED_I2CD_MULTI_MASTER_DIS BIT(15) 50 #define ASPEED_I2CD_SDA_DRIVE_1T_EN BIT(8) 51 #define ASPEED_I2CD_M_SDA_DRIVE_1T_EN BIT(7) 52 #define ASPEED_I2CD_M_HIGH_SPEED_EN BIT(6) 53 #define ASPEED_I2CD_SLAVE_EN BIT(1) 54 #define ASPEED_I2CD_MASTER_EN BIT(0) 55 56 /* 0x04 : I2CD Clock and AC Timing Control Register #1 */ 57 #define ASPEED_I2CD_TIME_TBUF_MASK GENMASK(31, 28) 58 #define ASPEED_I2CD_TIME_THDSTA_MASK GENMASK(27, 24) 59 #define ASPEED_I2CD_TIME_TACST_MASK GENMASK(23, 20) 60 #define ASPEED_I2CD_TIME_SCL_HIGH_SHIFT 16 61 #define ASPEED_I2CD_TIME_SCL_HIGH_MASK GENMASK(19, 16) 62 #define ASPEED_I2CD_TIME_SCL_LOW_SHIFT 12 63 #define ASPEED_I2CD_TIME_SCL_LOW_MASK GENMASK(15, 12) 64 #define ASPEED_I2CD_TIME_BASE_DIVISOR_MASK GENMASK(3, 0) 65 #define ASPEED_I2CD_TIME_SCL_REG_MAX GENMASK(3, 0) 66 /* 0x08 : I2CD Clock and AC Timing Control Register #2 */ 67 #define ASPEED_NO_TIMEOUT_CTRL 0 68 69 /* 0x0c : I2CD Interrupt Control Register & 70 * 0x10 : I2CD Interrupt Status Register 71 * 72 * These share bit definitions, so use the same values for the enable & 73 * status bits. 74 */ 75 #define ASPEED_I2CD_INTR_SDA_DL_TIMEOUT BIT(14) 76 #define ASPEED_I2CD_INTR_BUS_RECOVER_DONE BIT(13) 77 #define ASPEED_I2CD_INTR_SLAVE_MATCH BIT(7) 78 #define ASPEED_I2CD_INTR_SCL_TIMEOUT BIT(6) 79 #define ASPEED_I2CD_INTR_ABNORMAL BIT(5) 80 #define ASPEED_I2CD_INTR_NORMAL_STOP BIT(4) 81 #define ASPEED_I2CD_INTR_ARBIT_LOSS BIT(3) 82 #define ASPEED_I2CD_INTR_RX_DONE BIT(2) 83 #define ASPEED_I2CD_INTR_TX_NAK BIT(1) 84 #define ASPEED_I2CD_INTR_TX_ACK BIT(0) 85 #define ASPEED_I2CD_INTR_ALL \ 86 (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | \ 87 ASPEED_I2CD_INTR_BUS_RECOVER_DONE | \ 88 ASPEED_I2CD_INTR_SCL_TIMEOUT | \ 89 ASPEED_I2CD_INTR_ABNORMAL | \ 90 ASPEED_I2CD_INTR_NORMAL_STOP | \ 91 ASPEED_I2CD_INTR_ARBIT_LOSS | \ 92 ASPEED_I2CD_INTR_RX_DONE | \ 93 ASPEED_I2CD_INTR_TX_NAK | \ 94 ASPEED_I2CD_INTR_TX_ACK) 95 96 /* 0x14 : I2CD Command/Status Register */ 97 #define ASPEED_I2CD_SCL_LINE_STS BIT(18) 98 #define ASPEED_I2CD_SDA_LINE_STS BIT(17) 99 #define ASPEED_I2CD_BUS_BUSY_STS BIT(16) 100 #define ASPEED_I2CD_BUS_RECOVER_CMD BIT(11) 101 102 /* Command Bit */ 103 #define ASPEED_I2CD_M_STOP_CMD BIT(5) 104 #define ASPEED_I2CD_M_S_RX_CMD_LAST BIT(4) 105 #define ASPEED_I2CD_M_RX_CMD BIT(3) 106 #define ASPEED_I2CD_S_TX_CMD BIT(2) 107 #define ASPEED_I2CD_M_TX_CMD BIT(1) 108 #define ASPEED_I2CD_M_START_CMD BIT(0) 109 110 /* 0x18 : I2CD Slave Device Address Register */ 111 #define ASPEED_I2CD_DEV_ADDR_MASK GENMASK(6, 0) 112 113 enum aspeed_i2c_master_state { 114 ASPEED_I2C_MASTER_START, 115 ASPEED_I2C_MASTER_TX_FIRST, 116 ASPEED_I2C_MASTER_TX, 117 ASPEED_I2C_MASTER_RX_FIRST, 118 ASPEED_I2C_MASTER_RX, 119 ASPEED_I2C_MASTER_STOP, 120 ASPEED_I2C_MASTER_INACTIVE, 121 }; 122 123 enum aspeed_i2c_slave_state { 124 ASPEED_I2C_SLAVE_START, 125 ASPEED_I2C_SLAVE_READ_REQUESTED, 126 ASPEED_I2C_SLAVE_READ_PROCESSED, 127 ASPEED_I2C_SLAVE_WRITE_REQUESTED, 128 ASPEED_I2C_SLAVE_WRITE_RECEIVED, 129 ASPEED_I2C_SLAVE_STOP, 130 }; 131 132 struct aspeed_i2c_bus { 133 struct i2c_adapter adap; 134 struct device *dev; 135 void __iomem *base; 136 struct reset_control *rst; 137 /* Synchronizes I/O mem access to base. */ 138 spinlock_t lock; 139 struct completion cmd_complete; 140 u32 (*get_clk_reg_val)(u32 divisor); 141 unsigned long parent_clk_frequency; 142 u32 bus_frequency; 143 /* Transaction state. */ 144 enum aspeed_i2c_master_state master_state; 145 struct i2c_msg *msgs; 146 size_t buf_index; 147 size_t msgs_index; 148 size_t msgs_count; 149 bool send_stop; 150 int cmd_err; 151 /* Protected only by i2c_lock_bus */ 152 int master_xfer_result; 153 #if IS_ENABLED(CONFIG_I2C_SLAVE) 154 struct i2c_client *slave; 155 enum aspeed_i2c_slave_state slave_state; 156 #endif /* CONFIG_I2C_SLAVE */ 157 }; 158 159 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus); 160 161 static int aspeed_i2c_recover_bus(struct aspeed_i2c_bus *bus) 162 { 163 unsigned long time_left, flags; 164 int ret = 0; 165 u32 command; 166 167 spin_lock_irqsave(&bus->lock, flags); 168 command = readl(bus->base + ASPEED_I2C_CMD_REG); 169 170 if (command & ASPEED_I2CD_SDA_LINE_STS) { 171 /* Bus is idle: no recovery needed. */ 172 if (command & ASPEED_I2CD_SCL_LINE_STS) 173 goto out; 174 dev_dbg(bus->dev, "SCL hung (state %x), attempting recovery\n", 175 command); 176 177 reinit_completion(&bus->cmd_complete); 178 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); 179 spin_unlock_irqrestore(&bus->lock, flags); 180 181 time_left = wait_for_completion_timeout( 182 &bus->cmd_complete, bus->adap.timeout); 183 184 spin_lock_irqsave(&bus->lock, flags); 185 if (time_left == 0) 186 goto reset_out; 187 else if (bus->cmd_err) 188 goto reset_out; 189 /* Recovery failed. */ 190 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & 191 ASPEED_I2CD_SCL_LINE_STS)) 192 goto reset_out; 193 /* Bus error. */ 194 } else { 195 dev_dbg(bus->dev, "SDA hung (state %x), attempting recovery\n", 196 command); 197 198 reinit_completion(&bus->cmd_complete); 199 /* Writes 1 to 8 SCL clock cycles until SDA is released. */ 200 writel(ASPEED_I2CD_BUS_RECOVER_CMD, 201 bus->base + ASPEED_I2C_CMD_REG); 202 spin_unlock_irqrestore(&bus->lock, flags); 203 204 time_left = wait_for_completion_timeout( 205 &bus->cmd_complete, bus->adap.timeout); 206 207 spin_lock_irqsave(&bus->lock, flags); 208 if (time_left == 0) 209 goto reset_out; 210 else if (bus->cmd_err) 211 goto reset_out; 212 /* Recovery failed. */ 213 else if (!(readl(bus->base + ASPEED_I2C_CMD_REG) & 214 ASPEED_I2CD_SDA_LINE_STS)) 215 goto reset_out; 216 } 217 218 out: 219 spin_unlock_irqrestore(&bus->lock, flags); 220 221 return ret; 222 223 reset_out: 224 spin_unlock_irqrestore(&bus->lock, flags); 225 226 return aspeed_i2c_reset(bus); 227 } 228 229 #if IS_ENABLED(CONFIG_I2C_SLAVE) 230 static bool aspeed_i2c_slave_irq(struct aspeed_i2c_bus *bus) 231 { 232 u32 command, irq_status, status_ack = 0; 233 struct i2c_client *slave = bus->slave; 234 bool irq_handled = true; 235 u8 value; 236 237 spin_lock(&bus->lock); 238 if (!slave) { 239 irq_handled = false; 240 goto out; 241 } 242 243 command = readl(bus->base + ASPEED_I2C_CMD_REG); 244 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG); 245 246 /* Slave was requested, restart state machine. */ 247 if (irq_status & ASPEED_I2CD_INTR_SLAVE_MATCH) { 248 status_ack |= ASPEED_I2CD_INTR_SLAVE_MATCH; 249 bus->slave_state = ASPEED_I2C_SLAVE_START; 250 } 251 252 /* Slave is not currently active, irq was for someone else. */ 253 if (bus->slave_state == ASPEED_I2C_SLAVE_STOP) { 254 irq_handled = false; 255 goto out; 256 } 257 258 dev_dbg(bus->dev, "slave irq status 0x%08x, cmd 0x%08x\n", 259 irq_status, command); 260 261 /* Slave was sent something. */ 262 if (irq_status & ASPEED_I2CD_INTR_RX_DONE) { 263 value = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; 264 /* Handle address frame. */ 265 if (bus->slave_state == ASPEED_I2C_SLAVE_START) { 266 if (value & 0x1) 267 bus->slave_state = 268 ASPEED_I2C_SLAVE_READ_REQUESTED; 269 else 270 bus->slave_state = 271 ASPEED_I2C_SLAVE_WRITE_REQUESTED; 272 } 273 status_ack |= ASPEED_I2CD_INTR_RX_DONE; 274 } 275 276 /* Slave was asked to stop. */ 277 if (irq_status & ASPEED_I2CD_INTR_NORMAL_STOP) { 278 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP; 279 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 280 } 281 if (irq_status & ASPEED_I2CD_INTR_TX_NAK) { 282 status_ack |= ASPEED_I2CD_INTR_TX_NAK; 283 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 284 } 285 286 switch (bus->slave_state) { 287 case ASPEED_I2C_SLAVE_READ_REQUESTED: 288 if (irq_status & ASPEED_I2CD_INTR_TX_ACK) 289 dev_err(bus->dev, "Unexpected ACK on read request.\n"); 290 bus->slave_state = ASPEED_I2C_SLAVE_READ_PROCESSED; 291 292 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 293 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); 294 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); 295 break; 296 case ASPEED_I2C_SLAVE_READ_PROCESSED: 297 status_ack |= ASPEED_I2CD_INTR_TX_ACK; 298 if (!(irq_status & ASPEED_I2CD_INTR_TX_ACK)) 299 dev_err(bus->dev, 300 "Expected ACK after processed read.\n"); 301 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 302 writel(value, bus->base + ASPEED_I2C_BYTE_BUF_REG); 303 writel(ASPEED_I2CD_S_TX_CMD, bus->base + ASPEED_I2C_CMD_REG); 304 break; 305 case ASPEED_I2C_SLAVE_WRITE_REQUESTED: 306 bus->slave_state = ASPEED_I2C_SLAVE_WRITE_RECEIVED; 307 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 308 break; 309 case ASPEED_I2C_SLAVE_WRITE_RECEIVED: 310 i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, &value); 311 break; 312 case ASPEED_I2C_SLAVE_STOP: 313 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 314 break; 315 default: 316 dev_err(bus->dev, "unhandled slave_state: %d\n", 317 bus->slave_state); 318 break; 319 } 320 321 if (status_ack != irq_status) 322 dev_err(bus->dev, 323 "irq handled != irq. expected %x, but was %x\n", 324 irq_status, status_ack); 325 writel(status_ack, bus->base + ASPEED_I2C_INTR_STS_REG); 326 327 out: 328 spin_unlock(&bus->lock); 329 return irq_handled; 330 } 331 #endif /* CONFIG_I2C_SLAVE */ 332 333 /* precondition: bus.lock has been acquired. */ 334 static void aspeed_i2c_do_start(struct aspeed_i2c_bus *bus) 335 { 336 u32 command = ASPEED_I2CD_M_START_CMD | ASPEED_I2CD_M_TX_CMD; 337 struct i2c_msg *msg = &bus->msgs[bus->msgs_index]; 338 u8 slave_addr = i2c_8bit_addr_from_msg(msg); 339 340 bus->master_state = ASPEED_I2C_MASTER_START; 341 bus->buf_index = 0; 342 343 if (msg->flags & I2C_M_RD) { 344 command |= ASPEED_I2CD_M_RX_CMD; 345 /* Need to let the hardware know to NACK after RX. */ 346 if (msg->len == 1 && !(msg->flags & I2C_M_RECV_LEN)) 347 command |= ASPEED_I2CD_M_S_RX_CMD_LAST; 348 } 349 350 writel(slave_addr, bus->base + ASPEED_I2C_BYTE_BUF_REG); 351 writel(command, bus->base + ASPEED_I2C_CMD_REG); 352 } 353 354 /* precondition: bus.lock has been acquired. */ 355 static void aspeed_i2c_do_stop(struct aspeed_i2c_bus *bus) 356 { 357 bus->master_state = ASPEED_I2C_MASTER_STOP; 358 writel(ASPEED_I2CD_M_STOP_CMD, bus->base + ASPEED_I2C_CMD_REG); 359 } 360 361 /* precondition: bus.lock has been acquired. */ 362 static void aspeed_i2c_next_msg_or_stop(struct aspeed_i2c_bus *bus) 363 { 364 if (bus->msgs_index + 1 < bus->msgs_count) { 365 bus->msgs_index++; 366 aspeed_i2c_do_start(bus); 367 } else { 368 aspeed_i2c_do_stop(bus); 369 } 370 } 371 372 static int aspeed_i2c_is_irq_error(u32 irq_status) 373 { 374 if (irq_status & ASPEED_I2CD_INTR_ARBIT_LOSS) 375 return -EAGAIN; 376 if (irq_status & (ASPEED_I2CD_INTR_SDA_DL_TIMEOUT | 377 ASPEED_I2CD_INTR_SCL_TIMEOUT)) 378 return -EBUSY; 379 if (irq_status & (ASPEED_I2CD_INTR_ABNORMAL)) 380 return -EPROTO; 381 382 return 0; 383 } 384 385 static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus) 386 { 387 u32 irq_status, status_ack = 0, command = 0; 388 struct i2c_msg *msg; 389 u8 recv_byte; 390 int ret; 391 392 spin_lock(&bus->lock); 393 irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG); 394 /* Ack all interrupt bits. */ 395 writel(irq_status, bus->base + ASPEED_I2C_INTR_STS_REG); 396 397 if (irq_status & ASPEED_I2CD_INTR_BUS_RECOVER_DONE) { 398 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 399 status_ack |= ASPEED_I2CD_INTR_BUS_RECOVER_DONE; 400 goto out_complete; 401 } 402 403 /* 404 * We encountered an interrupt that reports an error: the hardware 405 * should clear the command queue effectively taking us back to the 406 * INACTIVE state. 407 */ 408 ret = aspeed_i2c_is_irq_error(irq_status); 409 if (ret < 0) { 410 dev_dbg(bus->dev, "received error interrupt: 0x%08x", 411 irq_status); 412 bus->cmd_err = ret; 413 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 414 goto out_complete; 415 } 416 417 /* We are in an invalid state; reset bus to a known state. */ 418 if (!bus->msgs) { 419 dev_err(bus->dev, "bus in unknown state"); 420 bus->cmd_err = -EIO; 421 if (bus->master_state != ASPEED_I2C_MASTER_STOP) 422 aspeed_i2c_do_stop(bus); 423 goto out_no_complete; 424 } 425 msg = &bus->msgs[bus->msgs_index]; 426 427 /* 428 * START is a special case because we still have to handle a subsequent 429 * TX or RX immediately after we handle it, so we handle it here and 430 * then update the state and handle the new state below. 431 */ 432 if (bus->master_state == ASPEED_I2C_MASTER_START) { 433 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { 434 pr_devel("no slave present at %02x", msg->addr); 435 status_ack |= ASPEED_I2CD_INTR_TX_NAK; 436 bus->cmd_err = -ENXIO; 437 aspeed_i2c_do_stop(bus); 438 goto out_no_complete; 439 } 440 status_ack |= ASPEED_I2CD_INTR_TX_ACK; 441 if (msg->len == 0) { /* SMBUS_QUICK */ 442 aspeed_i2c_do_stop(bus); 443 goto out_no_complete; 444 } 445 if (msg->flags & I2C_M_RD) 446 bus->master_state = ASPEED_I2C_MASTER_RX_FIRST; 447 else 448 bus->master_state = ASPEED_I2C_MASTER_TX_FIRST; 449 } 450 451 switch (bus->master_state) { 452 case ASPEED_I2C_MASTER_TX: 453 if (unlikely(irq_status & ASPEED_I2CD_INTR_TX_NAK)) { 454 dev_dbg(bus->dev, "slave NACKed TX"); 455 status_ack |= ASPEED_I2CD_INTR_TX_NAK; 456 goto error_and_stop; 457 } else if (unlikely(!(irq_status & ASPEED_I2CD_INTR_TX_ACK))) { 458 dev_err(bus->dev, "slave failed to ACK TX"); 459 goto error_and_stop; 460 } 461 status_ack |= ASPEED_I2CD_INTR_TX_ACK; 462 /* fallthrough intended */ 463 case ASPEED_I2C_MASTER_TX_FIRST: 464 if (bus->buf_index < msg->len) { 465 bus->master_state = ASPEED_I2C_MASTER_TX; 466 writel(msg->buf[bus->buf_index++], 467 bus->base + ASPEED_I2C_BYTE_BUF_REG); 468 writel(ASPEED_I2CD_M_TX_CMD, 469 bus->base + ASPEED_I2C_CMD_REG); 470 } else { 471 aspeed_i2c_next_msg_or_stop(bus); 472 } 473 goto out_no_complete; 474 case ASPEED_I2C_MASTER_RX_FIRST: 475 /* RX may not have completed yet (only address cycle) */ 476 if (!(irq_status & ASPEED_I2CD_INTR_RX_DONE)) 477 goto out_no_complete; 478 /* fallthrough intended */ 479 case ASPEED_I2C_MASTER_RX: 480 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_RX_DONE))) { 481 dev_err(bus->dev, "master failed to RX"); 482 goto error_and_stop; 483 } 484 status_ack |= ASPEED_I2CD_INTR_RX_DONE; 485 486 recv_byte = readl(bus->base + ASPEED_I2C_BYTE_BUF_REG) >> 8; 487 msg->buf[bus->buf_index++] = recv_byte; 488 489 if (msg->flags & I2C_M_RECV_LEN) { 490 if (unlikely(recv_byte > I2C_SMBUS_BLOCK_MAX)) { 491 bus->cmd_err = -EPROTO; 492 aspeed_i2c_do_stop(bus); 493 goto out_no_complete; 494 } 495 msg->len = recv_byte + 496 ((msg->flags & I2C_CLIENT_PEC) ? 2 : 1); 497 msg->flags &= ~I2C_M_RECV_LEN; 498 } 499 500 if (bus->buf_index < msg->len) { 501 bus->master_state = ASPEED_I2C_MASTER_RX; 502 command = ASPEED_I2CD_M_RX_CMD; 503 if (bus->buf_index + 1 == msg->len) 504 command |= ASPEED_I2CD_M_S_RX_CMD_LAST; 505 writel(command, bus->base + ASPEED_I2C_CMD_REG); 506 } else { 507 aspeed_i2c_next_msg_or_stop(bus); 508 } 509 goto out_no_complete; 510 case ASPEED_I2C_MASTER_STOP: 511 if (unlikely(!(irq_status & ASPEED_I2CD_INTR_NORMAL_STOP))) { 512 dev_err(bus->dev, "master failed to STOP"); 513 bus->cmd_err = -EIO; 514 /* Do not STOP as we have already tried. */ 515 } else { 516 status_ack |= ASPEED_I2CD_INTR_NORMAL_STOP; 517 } 518 519 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 520 goto out_complete; 521 case ASPEED_I2C_MASTER_INACTIVE: 522 dev_err(bus->dev, 523 "master received interrupt 0x%08x, but is inactive", 524 irq_status); 525 bus->cmd_err = -EIO; 526 /* Do not STOP as we should be inactive. */ 527 goto out_complete; 528 default: 529 WARN(1, "unknown master state\n"); 530 bus->master_state = ASPEED_I2C_MASTER_INACTIVE; 531 bus->cmd_err = -EINVAL; 532 goto out_complete; 533 } 534 error_and_stop: 535 bus->cmd_err = -EIO; 536 aspeed_i2c_do_stop(bus); 537 goto out_no_complete; 538 out_complete: 539 bus->msgs = NULL; 540 if (bus->cmd_err) 541 bus->master_xfer_result = bus->cmd_err; 542 else 543 bus->master_xfer_result = bus->msgs_index + 1; 544 complete(&bus->cmd_complete); 545 out_no_complete: 546 if (irq_status != status_ack) 547 dev_err(bus->dev, 548 "irq handled != irq. expected 0x%08x, but was 0x%08x\n", 549 irq_status, status_ack); 550 spin_unlock(&bus->lock); 551 return !!irq_status; 552 } 553 554 static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) 555 { 556 struct aspeed_i2c_bus *bus = dev_id; 557 558 #if IS_ENABLED(CONFIG_I2C_SLAVE) 559 if (aspeed_i2c_slave_irq(bus)) { 560 dev_dbg(bus->dev, "irq handled by slave.\n"); 561 return IRQ_HANDLED; 562 } 563 #endif /* CONFIG_I2C_SLAVE */ 564 565 return aspeed_i2c_master_irq(bus) ? IRQ_HANDLED : IRQ_NONE; 566 } 567 568 static int aspeed_i2c_master_xfer(struct i2c_adapter *adap, 569 struct i2c_msg *msgs, int num) 570 { 571 struct aspeed_i2c_bus *bus = i2c_get_adapdata(adap); 572 unsigned long time_left, flags; 573 int ret = 0; 574 575 spin_lock_irqsave(&bus->lock, flags); 576 bus->cmd_err = 0; 577 578 /* If bus is busy, attempt recovery. We assume a single master 579 * environment. 580 */ 581 if (readl(bus->base + ASPEED_I2C_CMD_REG) & ASPEED_I2CD_BUS_BUSY_STS) { 582 spin_unlock_irqrestore(&bus->lock, flags); 583 ret = aspeed_i2c_recover_bus(bus); 584 if (ret) 585 return ret; 586 spin_lock_irqsave(&bus->lock, flags); 587 } 588 589 bus->cmd_err = 0; 590 bus->msgs = msgs; 591 bus->msgs_index = 0; 592 bus->msgs_count = num; 593 594 reinit_completion(&bus->cmd_complete); 595 aspeed_i2c_do_start(bus); 596 spin_unlock_irqrestore(&bus->lock, flags); 597 598 time_left = wait_for_completion_timeout(&bus->cmd_complete, 599 bus->adap.timeout); 600 601 if (time_left == 0) 602 return -ETIMEDOUT; 603 else 604 return bus->master_xfer_result; 605 } 606 607 static u32 aspeed_i2c_functionality(struct i2c_adapter *adap) 608 { 609 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; 610 } 611 612 #if IS_ENABLED(CONFIG_I2C_SLAVE) 613 /* precondition: bus.lock has been acquired. */ 614 static void __aspeed_i2c_reg_slave(struct aspeed_i2c_bus *bus, u16 slave_addr) 615 { 616 u32 addr_reg_val, func_ctrl_reg_val; 617 618 /* Set slave addr. */ 619 addr_reg_val = readl(bus->base + ASPEED_I2C_DEV_ADDR_REG); 620 addr_reg_val &= ~ASPEED_I2CD_DEV_ADDR_MASK; 621 addr_reg_val |= slave_addr & ASPEED_I2CD_DEV_ADDR_MASK; 622 writel(addr_reg_val, bus->base + ASPEED_I2C_DEV_ADDR_REG); 623 624 /* Turn on slave mode. */ 625 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); 626 func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN; 627 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); 628 } 629 630 static int aspeed_i2c_reg_slave(struct i2c_client *client) 631 { 632 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter); 633 unsigned long flags; 634 635 spin_lock_irqsave(&bus->lock, flags); 636 if (bus->slave) { 637 spin_unlock_irqrestore(&bus->lock, flags); 638 return -EINVAL; 639 } 640 641 __aspeed_i2c_reg_slave(bus, client->addr); 642 643 bus->slave = client; 644 bus->slave_state = ASPEED_I2C_SLAVE_STOP; 645 spin_unlock_irqrestore(&bus->lock, flags); 646 647 return 0; 648 } 649 650 static int aspeed_i2c_unreg_slave(struct i2c_client *client) 651 { 652 struct aspeed_i2c_bus *bus = i2c_get_adapdata(client->adapter); 653 u32 func_ctrl_reg_val; 654 unsigned long flags; 655 656 spin_lock_irqsave(&bus->lock, flags); 657 if (!bus->slave) { 658 spin_unlock_irqrestore(&bus->lock, flags); 659 return -EINVAL; 660 } 661 662 /* Turn off slave mode. */ 663 func_ctrl_reg_val = readl(bus->base + ASPEED_I2C_FUN_CTRL_REG); 664 func_ctrl_reg_val &= ~ASPEED_I2CD_SLAVE_EN; 665 writel(func_ctrl_reg_val, bus->base + ASPEED_I2C_FUN_CTRL_REG); 666 667 bus->slave = NULL; 668 spin_unlock_irqrestore(&bus->lock, flags); 669 670 return 0; 671 } 672 #endif /* CONFIG_I2C_SLAVE */ 673 674 static const struct i2c_algorithm aspeed_i2c_algo = { 675 .master_xfer = aspeed_i2c_master_xfer, 676 .functionality = aspeed_i2c_functionality, 677 #if IS_ENABLED(CONFIG_I2C_SLAVE) 678 .reg_slave = aspeed_i2c_reg_slave, 679 .unreg_slave = aspeed_i2c_unreg_slave, 680 #endif /* CONFIG_I2C_SLAVE */ 681 }; 682 683 static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor) 684 { 685 u32 base_clk, clk_high, clk_low, tmp; 686 687 /* 688 * The actual clock frequency of SCL is: 689 * SCL_freq = APB_freq / (base_freq * (SCL_high + SCL_low)) 690 * = APB_freq / divisor 691 * where base_freq is a programmable clock divider; its value is 692 * base_freq = 1 << base_clk 693 * SCL_high is the number of base_freq clock cycles that SCL stays high 694 * and SCL_low is the number of base_freq clock cycles that SCL stays 695 * low for a period of SCL. 696 * The actual register has a minimum SCL_high and SCL_low minimum of 1; 697 * thus, they start counting at zero. So 698 * SCL_high = clk_high + 1 699 * SCL_low = clk_low + 1 700 * Thus, 701 * SCL_freq = APB_freq / 702 * ((1 << base_clk) * (clk_high + 1 + clk_low + 1)) 703 * The documentation recommends clk_high >= clk_high_max / 2 and 704 * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint 705 * gives us the following solution: 706 */ 707 base_clk = divisor > clk_high_low_max ? 708 ilog2((divisor - 1) / clk_high_low_max) + 1 : 0; 709 tmp = (divisor + (1 << base_clk) - 1) >> base_clk; 710 clk_low = tmp / 2; 711 clk_high = tmp - clk_low; 712 713 if (clk_high) 714 clk_high--; 715 716 if (clk_low) 717 clk_low--; 718 719 720 return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT) 721 & ASPEED_I2CD_TIME_SCL_HIGH_MASK) 722 | ((clk_low << ASPEED_I2CD_TIME_SCL_LOW_SHIFT) 723 & ASPEED_I2CD_TIME_SCL_LOW_MASK) 724 | (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK); 725 } 726 727 static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor) 728 { 729 /* 730 * clk_high and clk_low are each 3 bits wide, so each can hold a max 731 * value of 8 giving a clk_high_low_max of 16. 732 */ 733 return aspeed_i2c_get_clk_reg_val(16, divisor); 734 } 735 736 static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor) 737 { 738 /* 739 * clk_high and clk_low are each 4 bits wide, so each can hold a max 740 * value of 16 giving a clk_high_low_max of 32. 741 */ 742 return aspeed_i2c_get_clk_reg_val(32, divisor); 743 } 744 745 /* precondition: bus.lock has been acquired. */ 746 static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus) 747 { 748 u32 divisor, clk_reg_val; 749 750 divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency); 751 clk_reg_val = readl(bus->base + ASPEED_I2C_AC_TIMING_REG1); 752 clk_reg_val &= (ASPEED_I2CD_TIME_TBUF_MASK | 753 ASPEED_I2CD_TIME_THDSTA_MASK | 754 ASPEED_I2CD_TIME_TACST_MASK); 755 clk_reg_val |= bus->get_clk_reg_val(divisor); 756 writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1); 757 writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2); 758 759 return 0; 760 } 761 762 /* precondition: bus.lock has been acquired. */ 763 static int aspeed_i2c_init(struct aspeed_i2c_bus *bus, 764 struct platform_device *pdev) 765 { 766 u32 fun_ctrl_reg = ASPEED_I2CD_MASTER_EN; 767 int ret; 768 769 /* Disable everything. */ 770 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); 771 772 ret = aspeed_i2c_init_clk(bus); 773 if (ret < 0) 774 return ret; 775 776 if (!of_property_read_bool(pdev->dev.of_node, "multi-master")) 777 fun_ctrl_reg |= ASPEED_I2CD_MULTI_MASTER_DIS; 778 779 /* Enable Master Mode */ 780 writel(readl(bus->base + ASPEED_I2C_FUN_CTRL_REG) | fun_ctrl_reg, 781 bus->base + ASPEED_I2C_FUN_CTRL_REG); 782 783 #if IS_ENABLED(CONFIG_I2C_SLAVE) 784 /* If slave has already been registered, re-enable it. */ 785 if (bus->slave) 786 __aspeed_i2c_reg_slave(bus, bus->slave->addr); 787 #endif /* CONFIG_I2C_SLAVE */ 788 789 /* Set interrupt generation of I2C controller */ 790 writel(ASPEED_I2CD_INTR_ALL, bus->base + ASPEED_I2C_INTR_CTRL_REG); 791 792 return 0; 793 } 794 795 static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus) 796 { 797 struct platform_device *pdev = to_platform_device(bus->dev); 798 unsigned long flags; 799 int ret; 800 801 spin_lock_irqsave(&bus->lock, flags); 802 803 /* Disable and ack all interrupts. */ 804 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); 805 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); 806 807 ret = aspeed_i2c_init(bus, pdev); 808 809 spin_unlock_irqrestore(&bus->lock, flags); 810 811 return ret; 812 } 813 814 static const struct of_device_id aspeed_i2c_bus_of_table[] = { 815 { 816 .compatible = "aspeed,ast2400-i2c-bus", 817 .data = aspeed_i2c_24xx_get_clk_reg_val, 818 }, 819 { 820 .compatible = "aspeed,ast2500-i2c-bus", 821 .data = aspeed_i2c_25xx_get_clk_reg_val, 822 }, 823 { }, 824 }; 825 MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table); 826 827 static int aspeed_i2c_probe_bus(struct platform_device *pdev) 828 { 829 const struct of_device_id *match; 830 struct aspeed_i2c_bus *bus; 831 struct clk *parent_clk; 832 struct resource *res; 833 int irq, ret; 834 835 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); 836 if (!bus) 837 return -ENOMEM; 838 839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 840 bus->base = devm_ioremap_resource(&pdev->dev, res); 841 if (IS_ERR(bus->base)) 842 return PTR_ERR(bus->base); 843 844 parent_clk = devm_clk_get(&pdev->dev, NULL); 845 if (IS_ERR(parent_clk)) 846 return PTR_ERR(parent_clk); 847 bus->parent_clk_frequency = clk_get_rate(parent_clk); 848 /* We just need the clock rate, we don't actually use the clk object. */ 849 devm_clk_put(&pdev->dev, parent_clk); 850 851 bus->rst = devm_reset_control_get_shared(&pdev->dev, NULL); 852 if (IS_ERR(bus->rst)) { 853 dev_err(&pdev->dev, 854 "missing or invalid reset controller device tree entry"); 855 return PTR_ERR(bus->rst); 856 } 857 reset_control_deassert(bus->rst); 858 859 ret = of_property_read_u32(pdev->dev.of_node, 860 "bus-frequency", &bus->bus_frequency); 861 if (ret < 0) { 862 dev_err(&pdev->dev, 863 "Could not read bus-frequency property\n"); 864 bus->bus_frequency = 100000; 865 } 866 867 match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node); 868 if (!match) 869 bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val; 870 else 871 bus->get_clk_reg_val = match->data; 872 873 /* Initialize the I2C adapter */ 874 spin_lock_init(&bus->lock); 875 init_completion(&bus->cmd_complete); 876 bus->adap.owner = THIS_MODULE; 877 bus->adap.retries = 0; 878 bus->adap.timeout = 5 * HZ; 879 bus->adap.algo = &aspeed_i2c_algo; 880 bus->adap.dev.parent = &pdev->dev; 881 bus->adap.dev.of_node = pdev->dev.of_node; 882 strlcpy(bus->adap.name, pdev->name, sizeof(bus->adap.name)); 883 i2c_set_adapdata(&bus->adap, bus); 884 885 bus->dev = &pdev->dev; 886 887 /* Clean up any left over interrupt state. */ 888 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); 889 writel(0xffffffff, bus->base + ASPEED_I2C_INTR_STS_REG); 890 /* 891 * bus.lock does not need to be held because the interrupt handler has 892 * not been enabled yet. 893 */ 894 ret = aspeed_i2c_init(bus, pdev); 895 if (ret < 0) 896 return ret; 897 898 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 899 ret = devm_request_irq(&pdev->dev, irq, aspeed_i2c_bus_irq, 900 0, dev_name(&pdev->dev), bus); 901 if (ret < 0) 902 return ret; 903 904 ret = i2c_add_adapter(&bus->adap); 905 if (ret < 0) 906 return ret; 907 908 platform_set_drvdata(pdev, bus); 909 910 dev_info(bus->dev, "i2c bus %d registered, irq %d\n", 911 bus->adap.nr, irq); 912 913 return 0; 914 } 915 916 static int aspeed_i2c_remove_bus(struct platform_device *pdev) 917 { 918 struct aspeed_i2c_bus *bus = platform_get_drvdata(pdev); 919 unsigned long flags; 920 921 spin_lock_irqsave(&bus->lock, flags); 922 923 /* Disable everything. */ 924 writel(0, bus->base + ASPEED_I2C_FUN_CTRL_REG); 925 writel(0, bus->base + ASPEED_I2C_INTR_CTRL_REG); 926 927 spin_unlock_irqrestore(&bus->lock, flags); 928 929 reset_control_assert(bus->rst); 930 931 i2c_del_adapter(&bus->adap); 932 933 return 0; 934 } 935 936 static struct platform_driver aspeed_i2c_bus_driver = { 937 .probe = aspeed_i2c_probe_bus, 938 .remove = aspeed_i2c_remove_bus, 939 .driver = { 940 .name = "aspeed-i2c-bus", 941 .of_match_table = aspeed_i2c_bus_of_table, 942 }, 943 }; 944 module_platform_driver(aspeed_i2c_bus_driver); 945 946 MODULE_AUTHOR("Brendan Higgins <brendanhiggins@google.com>"); 947 MODULE_DESCRIPTION("Aspeed I2C Bus Driver"); 948 MODULE_LICENSE("GPL v2"); 949