1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright Intel Corporation (C) 2017. 4 * 5 * Based on the i2c-axxia.c driver. 6 */ 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/err.h> 10 #include <linux/i2c.h> 11 #include <linux/iopoll.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/platform_device.h> 17 18 #define ALTR_I2C_TFR_CMD 0x00 /* Transfer Command register */ 19 #define ALTR_I2C_TFR_CMD_STA BIT(9) /* send START before byte */ 20 #define ALTR_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */ 21 #define ALTR_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */ 22 #define ALTR_I2C_RX_DATA 0x04 /* RX data FIFO register */ 23 #define ALTR_I2C_CTRL 0x08 /* Control register */ 24 #define ALTR_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */ 25 #define ALTR_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */ 26 #define ALTR_I2C_CTRL_BSPEED BIT(1) /* Bus Speed (1=Fast) */ 27 #define ALTR_I2C_CTRL_EN BIT(0) /* Enable Core (1=Enable) */ 28 #define ALTR_I2C_ISER 0x0C /* Interrupt Status Enable register */ 29 #define ALTR_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */ 30 #define ALTR_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */ 31 #define ALTR_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */ 32 #define ALTR_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */ 33 #define ALTR_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */ 34 #define ALTR_I2C_ISR 0x10 /* Interrupt Status register */ 35 #define ALTR_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW IRQ */ 36 #define ALTR_I2C_ISR_ARB BIT(3) /* ARB LOST IRQ */ 37 #define ALTR_I2C_ISR_NACK BIT(2) /* NACK DET IRQ */ 38 #define ALTR_I2C_ISR_RXRDY BIT(1) /* RX Ready IRQ */ 39 #define ALTR_I2C_ISR_TXRDY BIT(0) /* TX Ready IRQ */ 40 #define ALTR_I2C_STATUS 0x14 /* Status register */ 41 #define ALTR_I2C_STAT_CORE BIT(0) /* Core Status (0=idle) */ 42 #define ALTR_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */ 43 #define ALTR_I2C_RX_FIFO_LVL 0x1C /* Receive FIFO LVL register */ 44 #define ALTR_I2C_SCL_LOW 0x20 /* SCL low count register */ 45 #define ALTR_I2C_SCL_HIGH 0x24 /* SCL high count register */ 46 #define ALTR_I2C_SDA_HOLD 0x28 /* SDA hold count register */ 47 48 #define ALTR_I2C_ALL_IRQ (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \ 49 ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \ 50 ALTR_I2C_ISR_TXRDY) 51 52 #define ALTR_I2C_THRESHOLD 0 /* IRQ Threshold at 1 element */ 53 #define ALTR_I2C_DFLT_FIFO_SZ 4 54 #define ALTR_I2C_TIMEOUT 100000 /* 100ms */ 55 #define ALTR_I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) 56 57 /** 58 * altr_i2c_dev - I2C device context 59 * @base: pointer to register struct 60 * @msg: pointer to current message 61 * @msg_len: number of bytes transferred in msg 62 * @msg_err: error code for completed message 63 * @msg_complete: xfer completion object 64 * @dev: device reference 65 * @adapter: core i2c abstraction 66 * @i2c_clk: clock reference for i2c input clock 67 * @bus_clk_rate: current i2c bus clock rate 68 * @buf: ptr to msg buffer for easier use. 69 * @fifo_size: size of the FIFO passed in. 70 * @isr_mask: cached copy of local ISR enables. 71 * @isr_status: cached copy of local ISR status. 72 * @isr_mutex: mutex for IRQ thread. 73 */ 74 struct altr_i2c_dev { 75 void __iomem *base; 76 struct i2c_msg *msg; 77 size_t msg_len; 78 int msg_err; 79 struct completion msg_complete; 80 struct device *dev; 81 struct i2c_adapter adapter; 82 struct clk *i2c_clk; 83 u32 bus_clk_rate; 84 u8 *buf; 85 u32 fifo_size; 86 u32 isr_mask; 87 u32 isr_status; 88 struct mutex isr_mutex; 89 }; 90 91 static void 92 altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable) 93 { 94 u32 int_en; 95 96 int_en = readl(idev->base + ALTR_I2C_ISER); 97 if (enable) 98 idev->isr_mask = int_en | mask; 99 else 100 idev->isr_mask = int_en & ~mask; 101 102 writel(idev->isr_mask, idev->base + ALTR_I2C_ISER); 103 } 104 105 static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask) 106 { 107 u32 int_en = readl(idev->base + ALTR_I2C_ISR); 108 109 writel(int_en | mask, idev->base + ALTR_I2C_ISR); 110 } 111 112 static void altr_i2c_core_disable(struct altr_i2c_dev *idev) 113 { 114 u32 tmp = readl(idev->base + ALTR_I2C_CTRL); 115 116 writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL); 117 } 118 119 static void altr_i2c_core_enable(struct altr_i2c_dev *idev) 120 { 121 u32 tmp = readl(idev->base + ALTR_I2C_CTRL); 122 123 writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL); 124 } 125 126 static void altr_i2c_reset(struct altr_i2c_dev *idev) 127 { 128 altr_i2c_core_disable(idev); 129 altr_i2c_core_enable(idev); 130 } 131 132 static inline void altr_i2c_stop(struct altr_i2c_dev *idev) 133 { 134 writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD); 135 } 136 137 static void altr_i2c_init(struct altr_i2c_dev *idev) 138 { 139 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; 140 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; 141 u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) | 142 (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT); 143 u32 t_high, t_low; 144 145 if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) { 146 tmp &= ~ALTR_I2C_CTRL_BSPEED; 147 /* Standard mode SCL 50/50 */ 148 t_high = divisor * 1 / 2; 149 t_low = divisor * 1 / 2; 150 } else { 151 tmp |= ALTR_I2C_CTRL_BSPEED; 152 /* Fast mode SCL 33/66 */ 153 t_high = divisor * 1 / 3; 154 t_low = divisor * 2 / 3; 155 } 156 writel(tmp, idev->base + ALTR_I2C_CTRL); 157 158 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", 159 idev->bus_clk_rate, clk_mhz, divisor); 160 161 /* Reset controller */ 162 altr_i2c_reset(idev); 163 164 /* SCL High Time */ 165 writel(t_high, idev->base + ALTR_I2C_SCL_HIGH); 166 /* SCL Low Time */ 167 writel(t_low, idev->base + ALTR_I2C_SCL_LOW); 168 /* SDA Hold Time, 300ns */ 169 writel(3 * clk_mhz / 10, idev->base + ALTR_I2C_SDA_HOLD); 170 171 /* Mask all master interrupt bits */ 172 altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false); 173 } 174 175 /** 176 * altr_i2c_transfer - On the last byte to be transmitted, send 177 * a Stop bit on the last byte. 178 */ 179 static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data) 180 { 181 /* On the last byte to be transmitted, send STOP */ 182 if (idev->msg_len == 1) 183 data |= ALTR_I2C_TFR_CMD_STO; 184 if (idev->msg_len > 0) 185 writel(data, idev->base + ALTR_I2C_TFR_CMD); 186 } 187 188 /** 189 * altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of 190 * transfer. Send a Stop bit on the last byte. 191 */ 192 static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev) 193 { 194 size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL); 195 int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len); 196 197 while (bytes_to_transfer-- > 0) { 198 *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA); 199 idev->msg_len--; 200 altr_i2c_transfer(idev, 0); 201 } 202 } 203 204 /** 205 * altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. 206 * @return: Number of bytes left to transfer. 207 */ 208 static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev) 209 { 210 size_t tx_fifo_avail = idev->fifo_size - readl(idev->base + 211 ALTR_I2C_TC_FIFO_LVL); 212 int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len); 213 int ret = idev->msg_len - bytes_to_transfer; 214 215 while (bytes_to_transfer-- > 0) { 216 altr_i2c_transfer(idev, *idev->buf++); 217 idev->msg_len--; 218 } 219 220 return ret; 221 } 222 223 static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev) 224 { 225 struct altr_i2c_dev *idev = _dev; 226 irqreturn_t ret = IRQ_HANDLED; 227 228 /* Read IRQ status but only interested in Enabled IRQs. */ 229 idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask; 230 if (idev->isr_status) 231 ret = IRQ_WAKE_THREAD; 232 233 return ret; 234 } 235 236 static irqreturn_t altr_i2c_isr(int irq, void *_dev) 237 { 238 int ret; 239 bool read, finish = false; 240 struct altr_i2c_dev *idev = _dev; 241 u32 status = idev->isr_status; 242 243 mutex_lock(&idev->isr_mutex); 244 if (!idev->msg) { 245 dev_warn(idev->dev, "unexpected interrupt\n"); 246 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ); 247 goto out; 248 } 249 read = (idev->msg->flags & I2C_M_RD) != 0; 250 251 /* handle Lost Arbitration */ 252 if (unlikely(status & ALTR_I2C_ISR_ARB)) { 253 altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB); 254 idev->msg_err = -EAGAIN; 255 finish = true; 256 } else if (unlikely(status & ALTR_I2C_ISR_NACK)) { 257 dev_dbg(idev->dev, "Could not get ACK\n"); 258 idev->msg_err = -ENXIO; 259 altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK); 260 altr_i2c_stop(idev); 261 finish = true; 262 } else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) { 263 /* handle RX FIFO Overflow */ 264 altr_i2c_empty_rx_fifo(idev); 265 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY); 266 altr_i2c_stop(idev); 267 dev_err(idev->dev, "RX FIFO Overflow\n"); 268 finish = true; 269 } else if (read && (status & ALTR_I2C_ISR_RXRDY)) { 270 /* RX FIFO needs service? */ 271 altr_i2c_empty_rx_fifo(idev); 272 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY); 273 if (!idev->msg_len) 274 finish = true; 275 } else if (!read && (status & ALTR_I2C_ISR_TXRDY)) { 276 /* TX FIFO needs service? */ 277 altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY); 278 if (idev->msg_len > 0) 279 altr_i2c_fill_tx_fifo(idev); 280 else 281 finish = true; 282 } else { 283 dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status); 284 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ); 285 } 286 287 if (finish) { 288 /* Wait for the Core to finish */ 289 ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS, 290 status, 291 !(status & ALTR_I2C_STAT_CORE), 292 1, ALTR_I2C_TIMEOUT); 293 if (ret) 294 dev_err(idev->dev, "message timeout\n"); 295 altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false); 296 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ); 297 complete(&idev->msg_complete); 298 dev_dbg(idev->dev, "Message Complete\n"); 299 } 300 out: 301 mutex_unlock(&idev->isr_mutex); 302 303 return IRQ_HANDLED; 304 } 305 306 static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg) 307 { 308 u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK; 309 unsigned long time_left; 310 u32 value; 311 u8 addr = i2c_8bit_addr_from_msg(msg); 312 313 mutex_lock(&idev->isr_mutex); 314 idev->msg = msg; 315 idev->msg_len = msg->len; 316 idev->buf = msg->buf; 317 idev->msg_err = 0; 318 reinit_completion(&idev->msg_complete); 319 altr_i2c_core_enable(idev); 320 321 /* Make sure RX FIFO is empty */ 322 do { 323 readl(idev->base + ALTR_I2C_RX_DATA); 324 } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL)); 325 326 writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD); 327 328 if ((msg->flags & I2C_M_RD) != 0) { 329 imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN; 330 altr_i2c_int_enable(idev, imask, true); 331 /* write the first byte to start the RX */ 332 altr_i2c_transfer(idev, 0); 333 } else { 334 imask |= ALTR_I2C_ISR_TXRDY; 335 altr_i2c_int_enable(idev, imask, true); 336 altr_i2c_fill_tx_fifo(idev); 337 } 338 mutex_unlock(&idev->isr_mutex); 339 340 time_left = wait_for_completion_timeout(&idev->msg_complete, 341 ALTR_I2C_XFER_TIMEOUT); 342 mutex_lock(&idev->isr_mutex); 343 altr_i2c_int_enable(idev, imask, false); 344 345 value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE; 346 if (value) 347 dev_err(idev->dev, "Core Status not IDLE...\n"); 348 349 if (time_left == 0) { 350 idev->msg_err = -ETIMEDOUT; 351 dev_dbg(idev->dev, "Transaction timed out.\n"); 352 } 353 354 altr_i2c_core_disable(idev); 355 mutex_unlock(&idev->isr_mutex); 356 357 return idev->msg_err; 358 } 359 360 static int 361 altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 362 { 363 struct altr_i2c_dev *idev = i2c_get_adapdata(adap); 364 int i, ret; 365 366 for (i = 0; i < num; i++) { 367 ret = altr_i2c_xfer_msg(idev, msgs++); 368 if (ret) 369 return ret; 370 } 371 return num; 372 } 373 374 static u32 altr_i2c_func(struct i2c_adapter *adap) 375 { 376 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 377 } 378 379 static const struct i2c_algorithm altr_i2c_algo = { 380 .master_xfer = altr_i2c_xfer, 381 .functionality = altr_i2c_func, 382 }; 383 384 static int altr_i2c_probe(struct platform_device *pdev) 385 { 386 struct altr_i2c_dev *idev = NULL; 387 int irq, ret; 388 389 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); 390 if (!idev) 391 return -ENOMEM; 392 393 idev->base = devm_platform_ioremap_resource(pdev, 0); 394 if (IS_ERR(idev->base)) 395 return PTR_ERR(idev->base); 396 397 irq = platform_get_irq(pdev, 0); 398 if (irq < 0) 399 return irq; 400 401 idev->i2c_clk = devm_clk_get(&pdev->dev, NULL); 402 if (IS_ERR(idev->i2c_clk)) { 403 dev_err(&pdev->dev, "missing clock\n"); 404 return PTR_ERR(idev->i2c_clk); 405 } 406 407 idev->dev = &pdev->dev; 408 init_completion(&idev->msg_complete); 409 mutex_init(&idev->isr_mutex); 410 411 ret = device_property_read_u32(idev->dev, "fifo-size", 412 &idev->fifo_size); 413 if (ret) { 414 dev_err(&pdev->dev, "FIFO size set to default of %d\n", 415 ALTR_I2C_DFLT_FIFO_SZ); 416 idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ; 417 } 418 419 ret = device_property_read_u32(idev->dev, "clock-frequency", 420 &idev->bus_clk_rate); 421 if (ret) { 422 dev_err(&pdev->dev, "Default to 100kHz\n"); 423 idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */ 424 } 425 426 if (idev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) { 427 dev_err(&pdev->dev, "invalid clock-frequency %d\n", 428 idev->bus_clk_rate); 429 return -EINVAL; 430 } 431 432 ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick, 433 altr_i2c_isr, IRQF_ONESHOT, 434 pdev->name, idev); 435 if (ret) { 436 dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq); 437 return ret; 438 } 439 440 ret = clk_prepare_enable(idev->i2c_clk); 441 if (ret) { 442 dev_err(&pdev->dev, "failed to enable clock\n"); 443 return ret; 444 } 445 446 mutex_lock(&idev->isr_mutex); 447 altr_i2c_init(idev); 448 mutex_unlock(&idev->isr_mutex); 449 450 i2c_set_adapdata(&idev->adapter, idev); 451 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 452 idev->adapter.owner = THIS_MODULE; 453 idev->adapter.algo = &altr_i2c_algo; 454 idev->adapter.dev.parent = &pdev->dev; 455 idev->adapter.dev.of_node = pdev->dev.of_node; 456 457 platform_set_drvdata(pdev, idev); 458 459 ret = i2c_add_adapter(&idev->adapter); 460 if (ret) { 461 clk_disable_unprepare(idev->i2c_clk); 462 return ret; 463 } 464 dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n"); 465 466 return 0; 467 } 468 469 static int altr_i2c_remove(struct platform_device *pdev) 470 { 471 struct altr_i2c_dev *idev = platform_get_drvdata(pdev); 472 473 clk_disable_unprepare(idev->i2c_clk); 474 i2c_del_adapter(&idev->adapter); 475 476 return 0; 477 } 478 479 /* Match table for of_platform binding */ 480 static const struct of_device_id altr_i2c_of_match[] = { 481 { .compatible = "altr,softip-i2c-v1.0" }, 482 {}, 483 }; 484 MODULE_DEVICE_TABLE(of, altr_i2c_of_match); 485 486 static struct platform_driver altr_i2c_driver = { 487 .probe = altr_i2c_probe, 488 .remove = altr_i2c_remove, 489 .driver = { 490 .name = "altera-i2c", 491 .of_match_table = altr_i2c_of_match, 492 }, 493 }; 494 495 module_platform_driver(altr_i2c_driver); 496 497 MODULE_DESCRIPTION("Altera Soft IP I2C bus driver"); 498 MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>"); 499 MODULE_LICENSE("GPL v2"); 500