1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright Intel Corporation (C) 2017. 4 * 5 * Based on the i2c-axxia.c driver. 6 */ 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/err.h> 10 #include <linux/i2c.h> 11 #include <linux/iopoll.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/platform_device.h> 17 18 #define ALTR_I2C_TFR_CMD 0x00 /* Transfer Command register */ 19 #define ALTR_I2C_TFR_CMD_STA BIT(9) /* send START before byte */ 20 #define ALTR_I2C_TFR_CMD_STO BIT(8) /* send STOP after byte */ 21 #define ALTR_I2C_TFR_CMD_RW_D BIT(0) /* Direction of transfer */ 22 #define ALTR_I2C_RX_DATA 0x04 /* RX data FIFO register */ 23 #define ALTR_I2C_CTRL 0x08 /* Control register */ 24 #define ALTR_I2C_CTRL_RXT_SHFT 4 /* RX FIFO Threshold */ 25 #define ALTR_I2C_CTRL_TCT_SHFT 2 /* TFER CMD FIFO Threshold */ 26 #define ALTR_I2C_CTRL_BSPEED BIT(1) /* Bus Speed (1=Fast) */ 27 #define ALTR_I2C_CTRL_EN BIT(0) /* Enable Core (1=Enable) */ 28 #define ALTR_I2C_ISER 0x0C /* Interrupt Status Enable register */ 29 #define ALTR_I2C_ISER_RXOF_EN BIT(4) /* Enable RX OVERFLOW IRQ */ 30 #define ALTR_I2C_ISER_ARB_EN BIT(3) /* Enable ARB LOST IRQ */ 31 #define ALTR_I2C_ISER_NACK_EN BIT(2) /* Enable NACK DET IRQ */ 32 #define ALTR_I2C_ISER_RXRDY_EN BIT(1) /* Enable RX Ready IRQ */ 33 #define ALTR_I2C_ISER_TXRDY_EN BIT(0) /* Enable TX Ready IRQ */ 34 #define ALTR_I2C_ISR 0x10 /* Interrupt Status register */ 35 #define ALTR_I2C_ISR_RXOF BIT(4) /* RX OVERFLOW IRQ */ 36 #define ALTR_I2C_ISR_ARB BIT(3) /* ARB LOST IRQ */ 37 #define ALTR_I2C_ISR_NACK BIT(2) /* NACK DET IRQ */ 38 #define ALTR_I2C_ISR_RXRDY BIT(1) /* RX Ready IRQ */ 39 #define ALTR_I2C_ISR_TXRDY BIT(0) /* TX Ready IRQ */ 40 #define ALTR_I2C_STATUS 0x14 /* Status register */ 41 #define ALTR_I2C_STAT_CORE BIT(0) /* Core Status (0=idle) */ 42 #define ALTR_I2C_TC_FIFO_LVL 0x18 /* Transfer FIFO LVL register */ 43 #define ALTR_I2C_RX_FIFO_LVL 0x1C /* Receive FIFO LVL register */ 44 #define ALTR_I2C_SCL_LOW 0x20 /* SCL low count register */ 45 #define ALTR_I2C_SCL_HIGH 0x24 /* SCL high count register */ 46 #define ALTR_I2C_SDA_HOLD 0x28 /* SDA hold count register */ 47 48 #define ALTR_I2C_ALL_IRQ (ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | \ 49 ALTR_I2C_ISR_NACK | ALTR_I2C_ISR_RXRDY | \ 50 ALTR_I2C_ISR_TXRDY) 51 52 #define ALTR_I2C_THRESHOLD 0 /* IRQ Threshold at 1 element */ 53 #define ALTR_I2C_DFLT_FIFO_SZ 4 54 #define ALTR_I2C_TIMEOUT 100000 /* 100ms */ 55 #define ALTR_I2C_XFER_TIMEOUT (msecs_to_jiffies(250)) 56 57 /** 58 * altr_i2c_dev - I2C device context 59 * @base: pointer to register struct 60 * @msg: pointer to current message 61 * @msg_len: number of bytes transferred in msg 62 * @msg_err: error code for completed message 63 * @msg_complete: xfer completion object 64 * @dev: device reference 65 * @adapter: core i2c abstraction 66 * @i2c_clk: clock reference for i2c input clock 67 * @bus_clk_rate: current i2c bus clock rate 68 * @buf: ptr to msg buffer for easier use. 69 * @fifo_size: size of the FIFO passed in. 70 * @isr_mask: cached copy of local ISR enables. 71 * @isr_status: cached copy of local ISR status. 72 * @lock: spinlock for IRQ synchronization. 73 */ 74 struct altr_i2c_dev { 75 void __iomem *base; 76 struct i2c_msg *msg; 77 size_t msg_len; 78 int msg_err; 79 struct completion msg_complete; 80 struct device *dev; 81 struct i2c_adapter adapter; 82 struct clk *i2c_clk; 83 u32 bus_clk_rate; 84 u8 *buf; 85 u32 fifo_size; 86 u32 isr_mask; 87 u32 isr_status; 88 spinlock_t lock; /* IRQ synchronization */ 89 }; 90 91 static void 92 altr_i2c_int_enable(struct altr_i2c_dev *idev, u32 mask, bool enable) 93 { 94 unsigned long flags; 95 u32 int_en; 96 97 spin_lock_irqsave(&idev->lock, flags); 98 99 int_en = readl(idev->base + ALTR_I2C_ISER); 100 if (enable) 101 idev->isr_mask = int_en | mask; 102 else 103 idev->isr_mask = int_en & ~mask; 104 105 writel(idev->isr_mask, idev->base + ALTR_I2C_ISER); 106 107 spin_unlock_irqrestore(&idev->lock, flags); 108 } 109 110 static void altr_i2c_int_clear(struct altr_i2c_dev *idev, u32 mask) 111 { 112 u32 int_en = readl(idev->base + ALTR_I2C_ISR); 113 114 writel(int_en | mask, idev->base + ALTR_I2C_ISR); 115 } 116 117 static void altr_i2c_core_disable(struct altr_i2c_dev *idev) 118 { 119 u32 tmp = readl(idev->base + ALTR_I2C_CTRL); 120 121 writel(tmp & ~ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL); 122 } 123 124 static void altr_i2c_core_enable(struct altr_i2c_dev *idev) 125 { 126 u32 tmp = readl(idev->base + ALTR_I2C_CTRL); 127 128 writel(tmp | ALTR_I2C_CTRL_EN, idev->base + ALTR_I2C_CTRL); 129 } 130 131 static void altr_i2c_reset(struct altr_i2c_dev *idev) 132 { 133 altr_i2c_core_disable(idev); 134 altr_i2c_core_enable(idev); 135 } 136 137 static inline void altr_i2c_stop(struct altr_i2c_dev *idev) 138 { 139 writel(ALTR_I2C_TFR_CMD_STO, idev->base + ALTR_I2C_TFR_CMD); 140 } 141 142 static void altr_i2c_init(struct altr_i2c_dev *idev) 143 { 144 u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate; 145 u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000; 146 u32 tmp = (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_RXT_SHFT) | 147 (ALTR_I2C_THRESHOLD << ALTR_I2C_CTRL_TCT_SHFT); 148 u32 t_high, t_low; 149 150 if (idev->bus_clk_rate <= 100000) { 151 tmp &= ~ALTR_I2C_CTRL_BSPEED; 152 /* Standard mode SCL 50/50 */ 153 t_high = divisor * 1 / 2; 154 t_low = divisor * 1 / 2; 155 } else { 156 tmp |= ALTR_I2C_CTRL_BSPEED; 157 /* Fast mode SCL 33/66 */ 158 t_high = divisor * 1 / 3; 159 t_low = divisor * 2 / 3; 160 } 161 writel(tmp, idev->base + ALTR_I2C_CTRL); 162 163 dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n", 164 idev->bus_clk_rate, clk_mhz, divisor); 165 166 /* Reset controller */ 167 altr_i2c_reset(idev); 168 169 /* SCL High Time */ 170 writel(t_high, idev->base + ALTR_I2C_SCL_HIGH); 171 /* SCL Low Time */ 172 writel(t_low, idev->base + ALTR_I2C_SCL_LOW); 173 /* SDA Hold Time, 300ns */ 174 writel(div_u64(300 * clk_mhz, 1000), idev->base + ALTR_I2C_SDA_HOLD); 175 176 /* Mask all master interrupt bits */ 177 altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false); 178 } 179 180 /** 181 * altr_i2c_transfer - On the last byte to be transmitted, send 182 * a Stop bit on the last byte. 183 */ 184 static void altr_i2c_transfer(struct altr_i2c_dev *idev, u32 data) 185 { 186 /* On the last byte to be transmitted, send STOP */ 187 if (idev->msg_len == 1) 188 data |= ALTR_I2C_TFR_CMD_STO; 189 if (idev->msg_len > 0) 190 writel(data, idev->base + ALTR_I2C_TFR_CMD); 191 } 192 193 /** 194 * altr_i2c_empty_rx_fifo - Fetch data from RX FIFO until end of 195 * transfer. Send a Stop bit on the last byte. 196 */ 197 static void altr_i2c_empty_rx_fifo(struct altr_i2c_dev *idev) 198 { 199 size_t rx_fifo_avail = readl(idev->base + ALTR_I2C_RX_FIFO_LVL); 200 int bytes_to_transfer = min(rx_fifo_avail, idev->msg_len); 201 202 while (bytes_to_transfer-- > 0) { 203 *idev->buf++ = readl(idev->base + ALTR_I2C_RX_DATA); 204 idev->msg_len--; 205 altr_i2c_transfer(idev, 0); 206 } 207 } 208 209 /** 210 * altr_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer. 211 * @return: Number of bytes left to transfer. 212 */ 213 static int altr_i2c_fill_tx_fifo(struct altr_i2c_dev *idev) 214 { 215 size_t tx_fifo_avail = idev->fifo_size - readl(idev->base + 216 ALTR_I2C_TC_FIFO_LVL); 217 int bytes_to_transfer = min(tx_fifo_avail, idev->msg_len); 218 int ret = idev->msg_len - bytes_to_transfer; 219 220 while (bytes_to_transfer-- > 0) { 221 altr_i2c_transfer(idev, *idev->buf++); 222 idev->msg_len--; 223 } 224 225 return ret; 226 } 227 228 static irqreturn_t altr_i2c_isr_quick(int irq, void *_dev) 229 { 230 struct altr_i2c_dev *idev = _dev; 231 irqreturn_t ret = IRQ_HANDLED; 232 233 /* Read IRQ status but only interested in Enabled IRQs. */ 234 idev->isr_status = readl(idev->base + ALTR_I2C_ISR) & idev->isr_mask; 235 if (idev->isr_status) 236 ret = IRQ_WAKE_THREAD; 237 238 return ret; 239 } 240 241 static irqreturn_t altr_i2c_isr(int irq, void *_dev) 242 { 243 int ret; 244 bool read, finish = false; 245 struct altr_i2c_dev *idev = _dev; 246 u32 status = idev->isr_status; 247 248 if (!idev->msg) { 249 dev_warn(idev->dev, "unexpected interrupt\n"); 250 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ); 251 return IRQ_HANDLED; 252 } 253 read = (idev->msg->flags & I2C_M_RD) != 0; 254 255 /* handle Lost Arbitration */ 256 if (unlikely(status & ALTR_I2C_ISR_ARB)) { 257 altr_i2c_int_clear(idev, ALTR_I2C_ISR_ARB); 258 idev->msg_err = -EAGAIN; 259 finish = true; 260 } else if (unlikely(status & ALTR_I2C_ISR_NACK)) { 261 dev_dbg(idev->dev, "Could not get ACK\n"); 262 idev->msg_err = -ENXIO; 263 altr_i2c_int_clear(idev, ALTR_I2C_ISR_NACK); 264 altr_i2c_stop(idev); 265 finish = true; 266 } else if (read && unlikely(status & ALTR_I2C_ISR_RXOF)) { 267 /* handle RX FIFO Overflow */ 268 altr_i2c_empty_rx_fifo(idev); 269 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY); 270 altr_i2c_stop(idev); 271 dev_err(idev->dev, "RX FIFO Overflow\n"); 272 finish = true; 273 } else if (read && (status & ALTR_I2C_ISR_RXRDY)) { 274 /* RX FIFO needs service? */ 275 altr_i2c_empty_rx_fifo(idev); 276 altr_i2c_int_clear(idev, ALTR_I2C_ISR_RXRDY); 277 if (!idev->msg_len) 278 finish = true; 279 } else if (!read && (status & ALTR_I2C_ISR_TXRDY)) { 280 /* TX FIFO needs service? */ 281 altr_i2c_int_clear(idev, ALTR_I2C_ISR_TXRDY); 282 if (idev->msg_len > 0) 283 altr_i2c_fill_tx_fifo(idev); 284 else 285 finish = true; 286 } else { 287 dev_warn(idev->dev, "Unexpected interrupt: 0x%x\n", status); 288 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ); 289 } 290 291 if (finish) { 292 /* Wait for the Core to finish */ 293 ret = readl_poll_timeout_atomic(idev->base + ALTR_I2C_STATUS, 294 status, 295 !(status & ALTR_I2C_STAT_CORE), 296 1, ALTR_I2C_TIMEOUT); 297 if (ret) 298 dev_err(idev->dev, "message timeout\n"); 299 altr_i2c_int_enable(idev, ALTR_I2C_ALL_IRQ, false); 300 altr_i2c_int_clear(idev, ALTR_I2C_ALL_IRQ); 301 complete(&idev->msg_complete); 302 dev_dbg(idev->dev, "Message Complete\n"); 303 } 304 305 return IRQ_HANDLED; 306 } 307 308 static int altr_i2c_xfer_msg(struct altr_i2c_dev *idev, struct i2c_msg *msg) 309 { 310 u32 imask = ALTR_I2C_ISR_RXOF | ALTR_I2C_ISR_ARB | ALTR_I2C_ISR_NACK; 311 unsigned long time_left; 312 u32 value; 313 u8 addr = i2c_8bit_addr_from_msg(msg); 314 315 idev->msg = msg; 316 idev->msg_len = msg->len; 317 idev->buf = msg->buf; 318 idev->msg_err = 0; 319 reinit_completion(&idev->msg_complete); 320 altr_i2c_core_enable(idev); 321 322 /* Make sure RX FIFO is empty */ 323 do { 324 readl(idev->base + ALTR_I2C_RX_DATA); 325 } while (readl(idev->base + ALTR_I2C_RX_FIFO_LVL)); 326 327 writel(ALTR_I2C_TFR_CMD_STA | addr, idev->base + ALTR_I2C_TFR_CMD); 328 329 if ((msg->flags & I2C_M_RD) != 0) { 330 imask |= ALTR_I2C_ISER_RXOF_EN | ALTR_I2C_ISER_RXRDY_EN; 331 altr_i2c_int_enable(idev, imask, true); 332 /* write the first byte to start the RX */ 333 altr_i2c_transfer(idev, 0); 334 } else { 335 imask |= ALTR_I2C_ISR_TXRDY; 336 altr_i2c_int_enable(idev, imask, true); 337 altr_i2c_fill_tx_fifo(idev); 338 } 339 340 time_left = wait_for_completion_timeout(&idev->msg_complete, 341 ALTR_I2C_XFER_TIMEOUT); 342 altr_i2c_int_enable(idev, imask, false); 343 344 value = readl(idev->base + ALTR_I2C_STATUS) & ALTR_I2C_STAT_CORE; 345 if (value) 346 dev_err(idev->dev, "Core Status not IDLE...\n"); 347 348 if (time_left == 0) { 349 idev->msg_err = -ETIMEDOUT; 350 dev_dbg(idev->dev, "Transaction timed out.\n"); 351 } 352 353 altr_i2c_core_disable(idev); 354 355 return idev->msg_err; 356 } 357 358 static int 359 altr_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 360 { 361 struct altr_i2c_dev *idev = i2c_get_adapdata(adap); 362 int i, ret; 363 364 for (i = 0; i < num; i++) { 365 ret = altr_i2c_xfer_msg(idev, msgs++); 366 if (ret) 367 return ret; 368 } 369 return num; 370 } 371 372 static u32 altr_i2c_func(struct i2c_adapter *adap) 373 { 374 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 375 } 376 377 static const struct i2c_algorithm altr_i2c_algo = { 378 .master_xfer = altr_i2c_xfer, 379 .functionality = altr_i2c_func, 380 }; 381 382 static int altr_i2c_probe(struct platform_device *pdev) 383 { 384 struct altr_i2c_dev *idev = NULL; 385 struct resource *res; 386 int irq, ret; 387 u32 val; 388 389 idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL); 390 if (!idev) 391 return -ENOMEM; 392 393 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 394 idev->base = devm_ioremap_resource(&pdev->dev, res); 395 if (IS_ERR(idev->base)) 396 return PTR_ERR(idev->base); 397 398 irq = platform_get_irq(pdev, 0); 399 if (irq < 0) { 400 dev_err(&pdev->dev, "missing interrupt resource\n"); 401 return irq; 402 } 403 404 idev->i2c_clk = devm_clk_get(&pdev->dev, NULL); 405 if (IS_ERR(idev->i2c_clk)) { 406 dev_err(&pdev->dev, "missing clock\n"); 407 return PTR_ERR(idev->i2c_clk); 408 } 409 410 idev->dev = &pdev->dev; 411 init_completion(&idev->msg_complete); 412 spin_lock_init(&idev->lock); 413 414 val = device_property_read_u32(idev->dev, "fifo-size", 415 &idev->fifo_size); 416 if (val) { 417 dev_err(&pdev->dev, "FIFO size set to default of %d\n", 418 ALTR_I2C_DFLT_FIFO_SZ); 419 idev->fifo_size = ALTR_I2C_DFLT_FIFO_SZ; 420 } 421 422 val = device_property_read_u32(idev->dev, "clock-frequency", 423 &idev->bus_clk_rate); 424 if (val) { 425 dev_err(&pdev->dev, "Default to 100kHz\n"); 426 idev->bus_clk_rate = 100000; /* default clock rate */ 427 } 428 429 if (idev->bus_clk_rate > 400000) { 430 dev_err(&pdev->dev, "invalid clock-frequency %d\n", 431 idev->bus_clk_rate); 432 return -EINVAL; 433 } 434 435 ret = devm_request_threaded_irq(&pdev->dev, irq, altr_i2c_isr_quick, 436 altr_i2c_isr, IRQF_ONESHOT, 437 pdev->name, idev); 438 if (ret) { 439 dev_err(&pdev->dev, "failed to claim IRQ %d\n", irq); 440 return ret; 441 } 442 443 ret = clk_prepare_enable(idev->i2c_clk); 444 if (ret) { 445 dev_err(&pdev->dev, "failed to enable clock\n"); 446 return ret; 447 } 448 449 altr_i2c_init(idev); 450 451 i2c_set_adapdata(&idev->adapter, idev); 452 strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name)); 453 idev->adapter.owner = THIS_MODULE; 454 idev->adapter.algo = &altr_i2c_algo; 455 idev->adapter.dev.parent = &pdev->dev; 456 idev->adapter.dev.of_node = pdev->dev.of_node; 457 458 platform_set_drvdata(pdev, idev); 459 460 ret = i2c_add_adapter(&idev->adapter); 461 if (ret) { 462 clk_disable_unprepare(idev->i2c_clk); 463 return ret; 464 } 465 dev_info(&pdev->dev, "Altera SoftIP I2C Probe Complete\n"); 466 467 return 0; 468 } 469 470 static int altr_i2c_remove(struct platform_device *pdev) 471 { 472 struct altr_i2c_dev *idev = platform_get_drvdata(pdev); 473 474 clk_disable_unprepare(idev->i2c_clk); 475 i2c_del_adapter(&idev->adapter); 476 477 return 0; 478 } 479 480 /* Match table for of_platform binding */ 481 static const struct of_device_id altr_i2c_of_match[] = { 482 { .compatible = "altr,softip-i2c-v1.0" }, 483 {}, 484 }; 485 MODULE_DEVICE_TABLE(of, altr_i2c_of_match); 486 487 static struct platform_driver altr_i2c_driver = { 488 .probe = altr_i2c_probe, 489 .remove = altr_i2c_remove, 490 .driver = { 491 .name = "altera-i2c", 492 .of_match_table = altr_i2c_of_match, 493 }, 494 }; 495 496 module_platform_driver(altr_i2c_driver); 497 498 MODULE_DESCRIPTION("Altera Soft IP I2C bus driver"); 499 MODULE_AUTHOR("Thor Thayer <thor.thayer@linux.intel.com>"); 500 MODULE_LICENSE("GPL v2"); 501