1 /* 2 * Intel(R) Trace Hub Global Trace Hub (GTH) data structures 3 * 4 * Copyright (C) 2014-2015 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __INTEL_TH_GTH_H__ 17 #define __INTEL_TH_GTH_H__ 18 19 /* Map output port parameter bits to symbolic names */ 20 #define TH_OUTPUT_PARM(name) \ 21 TH_OUTPUT_ ## name 22 23 enum intel_th_output_parm { 24 /* output port type */ 25 TH_OUTPUT_PARM(port), 26 /* generate NULL packet */ 27 TH_OUTPUT_PARM(null), 28 /* packet drop */ 29 TH_OUTPUT_PARM(drop), 30 /* port in reset state */ 31 TH_OUTPUT_PARM(reset), 32 /* flush out data */ 33 TH_OUTPUT_PARM(flush), 34 /* mainenance packet frequency */ 35 TH_OUTPUT_PARM(smcfreq), 36 }; 37 38 /* 39 * Register offsets 40 */ 41 enum { 42 REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */ 43 REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */ 44 REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */ 45 REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */ 46 REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */ 47 REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */ 48 REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */ 49 REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */ 50 REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */ 51 REG_GTH_STAT = 0xd4, /* GTH status */ 52 REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */ 53 REG_GTH_DESTOVR = 0xdc, /* Destination override */ 54 REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */ 55 REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */ 56 REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */ 57 REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */ 58 REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */ 59 REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */ 60 }; 61 62 /* waiting for Pipeline Empty bit(s) to assert for GTH */ 63 #define GTH_PLE_WAITLOOP_DEPTH 10000 64 65 #define TSUCTRL_CTCRESYNC BIT(0) 66 #define TSCUSTAT_CTCSYNCING BIT(1) 67 68 #endif /* __INTEL_TH_GTH_H__ */ 69