1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * This contains all required hardware related helper functions for
4  * Trace Buffer Extension (TRBE) driver in the coresight framework.
5  *
6  * Copyright (C) 2020 ARM Ltd.
7  *
8  * Author: Anshuman Khandual <anshuman.khandual@arm.com>
9  */
10 #include <linux/coresight.h>
11 #include <linux/device.h>
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/smp.h>
17 
18 #include "coresight-etm-perf.h"
19 
20 static inline bool is_trbe_available(void)
21 {
22 	u64 aa64dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
23 	unsigned int trbe = cpuid_feature_extract_unsigned_field(aa64dfr0,
24 								 ID_AA64DFR0_EL1_TraceBuffer_SHIFT);
25 
26 	return trbe >= 0b0001;
27 }
28 
29 static inline bool is_trbe_enabled(void)
30 {
31 	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
32 
33 	return trblimitr & TRBLIMITR_EL1_E;
34 }
35 
36 #define TRBE_EC_OTHERS		0
37 #define TRBE_EC_STAGE1_ABORT	36
38 #define TRBE_EC_STAGE2_ABORT	37
39 
40 static inline int get_trbe_ec(u64 trbsr)
41 {
42 	return (trbsr & TRBSR_EL1_EC_MASK) >> TRBSR_EL1_EC_SHIFT;
43 }
44 
45 #define TRBE_BSC_NOT_STOPPED 0
46 #define TRBE_BSC_FILLED      1
47 #define TRBE_BSC_TRIGGERED   2
48 
49 static inline int get_trbe_bsc(u64 trbsr)
50 {
51 	return (trbsr & TRBSR_EL1_BSC_MASK) >> TRBSR_EL1_BSC_SHIFT;
52 }
53 
54 static inline void clr_trbe_irq(void)
55 {
56 	u64 trbsr = read_sysreg_s(SYS_TRBSR_EL1);
57 
58 	trbsr &= ~TRBSR_EL1_IRQ;
59 	write_sysreg_s(trbsr, SYS_TRBSR_EL1);
60 }
61 
62 static inline bool is_trbe_irq(u64 trbsr)
63 {
64 	return trbsr & TRBSR_EL1_IRQ;
65 }
66 
67 static inline bool is_trbe_trg(u64 trbsr)
68 {
69 	return trbsr & TRBSR_EL1_TRG;
70 }
71 
72 static inline bool is_trbe_wrap(u64 trbsr)
73 {
74 	return trbsr & TRBSR_EL1_WRAP;
75 }
76 
77 static inline bool is_trbe_abort(u64 trbsr)
78 {
79 	return trbsr & TRBSR_EL1_EA;
80 }
81 
82 static inline bool is_trbe_running(u64 trbsr)
83 {
84 	return !(trbsr & TRBSR_EL1_S);
85 }
86 
87 #define TRBE_TRIG_MODE_STOP		0
88 #define TRBE_TRIG_MODE_IRQ		1
89 #define TRBLIMITR_EL1_TM_IGNR		3
90 
91 #define TRBLIMITR_EL1_FM_FILL		0
92 #define TRBE_FILL_MODE_FILL		0
93 #define TRBE_FILL_MODE_WRAP		1
94 #define TRBE_FILL_MODE_CIRCULAR_BUFFER	3
95 
96 static inline bool get_trbe_flag_update(u64 trbidr)
97 {
98 	return trbidr & TRBIDR_FLAG;
99 }
100 
101 static inline bool is_trbe_programmable(u64 trbidr)
102 {
103 	return !(trbidr & TRBIDR_PROG);
104 }
105 
106 static inline int get_trbe_address_align(u64 trbidr)
107 {
108 	return (trbidr >> TRBIDR_ALIGN_SHIFT) & TRBIDR_ALIGN_MASK;
109 }
110 
111 static inline unsigned long get_trbe_write_pointer(void)
112 {
113 	return read_sysreg_s(SYS_TRBPTR_EL1);
114 }
115 
116 static inline void set_trbe_write_pointer(unsigned long addr)
117 {
118 	WARN_ON(is_trbe_enabled());
119 	write_sysreg_s(addr, SYS_TRBPTR_EL1);
120 }
121 
122 static inline unsigned long get_trbe_limit_pointer(void)
123 {
124 	u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1);
125 	unsigned long addr = trblimitr & TRBLIMITR_EL1_LIMIT_MASK;
126 
127 	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
128 	return addr;
129 }
130 
131 static inline unsigned long get_trbe_base_pointer(void)
132 {
133 	u64 trbbaser = read_sysreg_s(SYS_TRBBASER_EL1);
134 	unsigned long addr = trbbaser & TRBBASER_EL1_BASE_MASK;
135 
136 	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
137 	return addr;
138 }
139 
140 static inline void set_trbe_base_pointer(unsigned long addr)
141 {
142 	WARN_ON(is_trbe_enabled());
143 	WARN_ON(!IS_ALIGNED(addr, (1UL << TRBBASER_EL1_BASE_SHIFT)));
144 	WARN_ON(!IS_ALIGNED(addr, PAGE_SIZE));
145 	write_sysreg_s(addr, SYS_TRBBASER_EL1);
146 }
147