1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight Trace Port Interface Unit driver 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/err.h> 13 #include <linux/slab.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/coresight.h> 16 #include <linux/amba/bus.h> 17 #include <linux/clk.h> 18 19 #include "coresight-priv.h" 20 21 #define TPIU_SUPP_PORTSZ 0x000 22 #define TPIU_CURR_PORTSZ 0x004 23 #define TPIU_SUPP_TRIGMODES 0x100 24 #define TPIU_TRIG_CNTRVAL 0x104 25 #define TPIU_TRIG_MULT 0x108 26 #define TPIU_SUPP_TESTPATM 0x200 27 #define TPIU_CURR_TESTPATM 0x204 28 #define TPIU_TEST_PATREPCNTR 0x208 29 #define TPIU_FFSR 0x300 30 #define TPIU_FFCR 0x304 31 #define TPIU_FSYNC_CNTR 0x308 32 #define TPIU_EXTCTL_INPORT 0x400 33 #define TPIU_EXTCTL_OUTPORT 0x404 34 #define TPIU_ITTRFLINACK 0xee4 35 #define TPIU_ITTRFLIN 0xee8 36 #define TPIU_ITATBDATA0 0xeec 37 #define TPIU_ITATBCTR2 0xef0 38 #define TPIU_ITATBCTR1 0xef4 39 #define TPIU_ITATBCTR0 0xef8 40 41 /** register definition **/ 42 /* FFSR - 0x300 */ 43 #define FFSR_FT_STOPPED BIT(1) 44 /* FFCR - 0x304 */ 45 #define FFCR_FON_MAN BIT(6) 46 #define FFCR_STOP_FI BIT(12) 47 48 /** 49 * @base: memory mapped base address for this component. 50 * @dev: the device entity associated to this component. 51 * @atclk: optional clock for the core parts of the TPIU. 52 * @csdev: component vitals needed by the framework. 53 */ 54 struct tpiu_drvdata { 55 void __iomem *base; 56 struct device *dev; 57 struct clk *atclk; 58 struct coresight_device *csdev; 59 }; 60 61 static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) 62 { 63 CS_UNLOCK(drvdata->base); 64 65 /* TODO: fill this up */ 66 67 CS_LOCK(drvdata->base); 68 } 69 70 static int tpiu_enable(struct coresight_device *csdev, u32 mode) 71 { 72 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 73 74 tpiu_enable_hw(drvdata); 75 76 dev_info(drvdata->dev, "TPIU enabled\n"); 77 return 0; 78 } 79 80 static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) 81 { 82 CS_UNLOCK(drvdata->base); 83 84 /* Clear formatter and stop on flush */ 85 writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR); 86 /* Generate manual flush */ 87 writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR); 88 /* Wait for flush to complete */ 89 coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN, 0); 90 /* Wait for formatter to stop */ 91 coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED, 1); 92 93 CS_LOCK(drvdata->base); 94 } 95 96 static void tpiu_disable(struct coresight_device *csdev) 97 { 98 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 99 100 tpiu_disable_hw(drvdata); 101 102 dev_info(drvdata->dev, "TPIU disabled\n"); 103 } 104 105 static const struct coresight_ops_sink tpiu_sink_ops = { 106 .enable = tpiu_enable, 107 .disable = tpiu_disable, 108 }; 109 110 static const struct coresight_ops tpiu_cs_ops = { 111 .sink_ops = &tpiu_sink_ops, 112 }; 113 114 static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) 115 { 116 int ret; 117 void __iomem *base; 118 struct device *dev = &adev->dev; 119 struct coresight_platform_data *pdata = NULL; 120 struct tpiu_drvdata *drvdata; 121 struct resource *res = &adev->res; 122 struct coresight_desc desc = { 0 }; 123 struct device_node *np = adev->dev.of_node; 124 125 if (np) { 126 pdata = of_get_coresight_platform_data(dev, np); 127 if (IS_ERR(pdata)) 128 return PTR_ERR(pdata); 129 adev->dev.platform_data = pdata; 130 } 131 132 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 133 if (!drvdata) 134 return -ENOMEM; 135 136 drvdata->dev = &adev->dev; 137 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 138 if (!IS_ERR(drvdata->atclk)) { 139 ret = clk_prepare_enable(drvdata->atclk); 140 if (ret) 141 return ret; 142 } 143 dev_set_drvdata(dev, drvdata); 144 145 /* Validity for the resource is already checked by the AMBA core */ 146 base = devm_ioremap_resource(dev, res); 147 if (IS_ERR(base)) 148 return PTR_ERR(base); 149 150 drvdata->base = base; 151 152 /* Disable tpiu to support older devices */ 153 tpiu_disable_hw(drvdata); 154 155 pm_runtime_put(&adev->dev); 156 157 desc.type = CORESIGHT_DEV_TYPE_SINK; 158 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT; 159 desc.ops = &tpiu_cs_ops; 160 desc.pdata = pdata; 161 desc.dev = dev; 162 drvdata->csdev = coresight_register(&desc); 163 164 return PTR_ERR_OR_ZERO(drvdata->csdev); 165 } 166 167 #ifdef CONFIG_PM 168 static int tpiu_runtime_suspend(struct device *dev) 169 { 170 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev); 171 172 if (drvdata && !IS_ERR(drvdata->atclk)) 173 clk_disable_unprepare(drvdata->atclk); 174 175 return 0; 176 } 177 178 static int tpiu_runtime_resume(struct device *dev) 179 { 180 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev); 181 182 if (drvdata && !IS_ERR(drvdata->atclk)) 183 clk_prepare_enable(drvdata->atclk); 184 185 return 0; 186 } 187 #endif 188 189 static const struct dev_pm_ops tpiu_dev_pm_ops = { 190 SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL) 191 }; 192 193 static const struct amba_id tpiu_ids[] = { 194 { 195 .id = 0x000bb912, 196 .mask = 0x000fffff, 197 }, 198 { 199 .id = 0x0004b912, 200 .mask = 0x0007ffff, 201 }, 202 { 203 /* Coresight SoC-600 */ 204 .id = 0x000bb9e7, 205 .mask = 0x000fffff, 206 }, 207 { 0, 0}, 208 }; 209 210 static struct amba_driver tpiu_driver = { 211 .drv = { 212 .name = "coresight-tpiu", 213 .owner = THIS_MODULE, 214 .pm = &tpiu_dev_pm_ops, 215 .suppress_bind_attrs = true, 216 }, 217 .probe = tpiu_probe, 218 .id_table = tpiu_ids, 219 }; 220 builtin_amba_driver(tpiu_driver); 221