1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight Trace Port Interface Unit driver 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/err.h> 13 #include <linux/slab.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/coresight.h> 16 #include <linux/amba/bus.h> 17 #include <linux/clk.h> 18 19 #include "coresight-priv.h" 20 21 #define TPIU_SUPP_PORTSZ 0x000 22 #define TPIU_CURR_PORTSZ 0x004 23 #define TPIU_SUPP_TRIGMODES 0x100 24 #define TPIU_TRIG_CNTRVAL 0x104 25 #define TPIU_TRIG_MULT 0x108 26 #define TPIU_SUPP_TESTPATM 0x200 27 #define TPIU_CURR_TESTPATM 0x204 28 #define TPIU_TEST_PATREPCNTR 0x208 29 #define TPIU_FFSR 0x300 30 #define TPIU_FFCR 0x304 31 #define TPIU_FSYNC_CNTR 0x308 32 #define TPIU_EXTCTL_INPORT 0x400 33 #define TPIU_EXTCTL_OUTPORT 0x404 34 #define TPIU_ITTRFLINACK 0xee4 35 #define TPIU_ITTRFLIN 0xee8 36 #define TPIU_ITATBDATA0 0xeec 37 #define TPIU_ITATBCTR2 0xef0 38 #define TPIU_ITATBCTR1 0xef4 39 #define TPIU_ITATBCTR0 0xef8 40 41 /** register definition **/ 42 /* FFSR - 0x300 */ 43 #define FFSR_FT_STOPPED_BIT 1 44 /* FFCR - 0x304 */ 45 #define FFCR_FON_MAN_BIT 6 46 #define FFCR_FON_MAN BIT(6) 47 #define FFCR_STOP_FI BIT(12) 48 49 /** 50 * @base: memory mapped base address for this component. 51 * @dev: the device entity associated to this component. 52 * @atclk: optional clock for the core parts of the TPIU. 53 * @csdev: component vitals needed by the framework. 54 */ 55 struct tpiu_drvdata { 56 void __iomem *base; 57 struct device *dev; 58 struct clk *atclk; 59 struct coresight_device *csdev; 60 }; 61 62 static void tpiu_enable_hw(struct tpiu_drvdata *drvdata) 63 { 64 CS_UNLOCK(drvdata->base); 65 66 /* TODO: fill this up */ 67 68 CS_LOCK(drvdata->base); 69 } 70 71 static int tpiu_enable(struct coresight_device *csdev, u32 mode) 72 { 73 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 74 75 tpiu_enable_hw(drvdata); 76 77 dev_info(drvdata->dev, "TPIU enabled\n"); 78 return 0; 79 } 80 81 static void tpiu_disable_hw(struct tpiu_drvdata *drvdata) 82 { 83 CS_UNLOCK(drvdata->base); 84 85 /* Clear formatter and stop on flush */ 86 writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR); 87 /* Generate manual flush */ 88 writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR); 89 /* Wait for flush to complete */ 90 coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0); 91 /* Wait for formatter to stop */ 92 coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1); 93 94 CS_LOCK(drvdata->base); 95 } 96 97 static void tpiu_disable(struct coresight_device *csdev) 98 { 99 struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 100 101 tpiu_disable_hw(drvdata); 102 103 dev_info(drvdata->dev, "TPIU disabled\n"); 104 } 105 106 static const struct coresight_ops_sink tpiu_sink_ops = { 107 .enable = tpiu_enable, 108 .disable = tpiu_disable, 109 }; 110 111 static const struct coresight_ops tpiu_cs_ops = { 112 .sink_ops = &tpiu_sink_ops, 113 }; 114 115 static int tpiu_probe(struct amba_device *adev, const struct amba_id *id) 116 { 117 int ret; 118 void __iomem *base; 119 struct device *dev = &adev->dev; 120 struct coresight_platform_data *pdata = NULL; 121 struct tpiu_drvdata *drvdata; 122 struct resource *res = &adev->res; 123 struct coresight_desc desc = { 0 }; 124 struct device_node *np = adev->dev.of_node; 125 126 if (np) { 127 pdata = of_get_coresight_platform_data(dev, np); 128 if (IS_ERR(pdata)) 129 return PTR_ERR(pdata); 130 adev->dev.platform_data = pdata; 131 } 132 133 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 134 if (!drvdata) 135 return -ENOMEM; 136 137 drvdata->dev = &adev->dev; 138 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 139 if (!IS_ERR(drvdata->atclk)) { 140 ret = clk_prepare_enable(drvdata->atclk); 141 if (ret) 142 return ret; 143 } 144 dev_set_drvdata(dev, drvdata); 145 146 /* Validity for the resource is already checked by the AMBA core */ 147 base = devm_ioremap_resource(dev, res); 148 if (IS_ERR(base)) 149 return PTR_ERR(base); 150 151 drvdata->base = base; 152 153 /* Disable tpiu to support older devices */ 154 tpiu_disable_hw(drvdata); 155 156 pm_runtime_put(&adev->dev); 157 158 desc.type = CORESIGHT_DEV_TYPE_SINK; 159 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_PORT; 160 desc.ops = &tpiu_cs_ops; 161 desc.pdata = pdata; 162 desc.dev = dev; 163 drvdata->csdev = coresight_register(&desc); 164 165 return PTR_ERR_OR_ZERO(drvdata->csdev); 166 } 167 168 #ifdef CONFIG_PM 169 static int tpiu_runtime_suspend(struct device *dev) 170 { 171 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev); 172 173 if (drvdata && !IS_ERR(drvdata->atclk)) 174 clk_disable_unprepare(drvdata->atclk); 175 176 return 0; 177 } 178 179 static int tpiu_runtime_resume(struct device *dev) 180 { 181 struct tpiu_drvdata *drvdata = dev_get_drvdata(dev); 182 183 if (drvdata && !IS_ERR(drvdata->atclk)) 184 clk_prepare_enable(drvdata->atclk); 185 186 return 0; 187 } 188 #endif 189 190 static const struct dev_pm_ops tpiu_dev_pm_ops = { 191 SET_RUNTIME_PM_OPS(tpiu_runtime_suspend, tpiu_runtime_resume, NULL) 192 }; 193 194 static const struct amba_id tpiu_ids[] = { 195 { 196 .id = 0x000bb912, 197 .mask = 0x000fffff, 198 }, 199 { 200 .id = 0x0004b912, 201 .mask = 0x0007ffff, 202 }, 203 { 204 /* Coresight SoC-600 */ 205 .id = 0x000bb9e7, 206 .mask = 0x000fffff, 207 }, 208 { 0, 0}, 209 }; 210 211 static struct amba_driver tpiu_driver = { 212 .drv = { 213 .name = "coresight-tpiu", 214 .owner = THIS_MODULE, 215 .pm = &tpiu_dev_pm_ops, 216 .suppress_bind_attrs = true, 217 }, 218 .probe = tpiu_probe, 219 .id_table = tpiu_ids, 220 }; 221 builtin_amba_driver(tpiu_driver); 222