1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_TMC_H 8 #define _CORESIGHT_TMC_H 9 10 #include <linux/dma-mapping.h> 11 #include <linux/idr.h> 12 #include <linux/miscdevice.h> 13 #include <linux/mutex.h> 14 #include <linux/refcount.h> 15 16 #define TMC_RSZ 0x004 17 #define TMC_STS 0x00c 18 #define TMC_RRD 0x010 19 #define TMC_RRP 0x014 20 #define TMC_RWP 0x018 21 #define TMC_TRG 0x01c 22 #define TMC_CTL 0x020 23 #define TMC_RWD 0x024 24 #define TMC_MODE 0x028 25 #define TMC_LBUFLEVEL 0x02c 26 #define TMC_CBUFLEVEL 0x030 27 #define TMC_BUFWM 0x034 28 #define TMC_RRPHI 0x038 29 #define TMC_RWPHI 0x03c 30 #define TMC_AXICTL 0x110 31 #define TMC_DBALO 0x118 32 #define TMC_DBAHI 0x11c 33 #define TMC_FFSR 0x300 34 #define TMC_FFCR 0x304 35 #define TMC_PSCR 0x308 36 #define TMC_ITMISCOP0 0xee0 37 #define TMC_ITTRFLIN 0xee8 38 #define TMC_ITATBDATA0 0xeec 39 #define TMC_ITATBCTR2 0xef0 40 #define TMC_ITATBCTR1 0xef4 41 #define TMC_ITATBCTR0 0xef8 42 43 /* register description */ 44 /* TMC_CTL - 0x020 */ 45 #define TMC_CTL_CAPT_EN BIT(0) 46 /* TMC_STS - 0x00C */ 47 #define TMC_STS_TMCREADY_BIT 2 48 #define TMC_STS_FULL BIT(0) 49 #define TMC_STS_TRIGGERED BIT(1) 50 #define TMC_STS_MEMERR BIT(5) 51 /* 52 * TMC_AXICTL - 0x110 53 * 54 * TMC AXICTL format for SoC-400 55 * Bits [0-1] : ProtCtrlBit0-1 56 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE) 57 * Bit 6 : Reserved 58 * Bit 7 : ScatterGatherMode 59 * Bits [8-11] : WrBurstLen 60 * Bits [12-31] : Reserved. 61 * TMC AXICTL format for SoC-600, as above except: 62 * Bits [2-5] : AXI WCACHE 63 * Bits [16-19] : AXI RCACHE 64 * Bits [20-31] : Reserved 65 */ 66 #define TMC_AXICTL_CLEAR_MASK 0xfbf 67 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16) 68 69 #define TMC_AXICTL_PROT_CTL_B0 BIT(0) 70 #define TMC_AXICTL_PROT_CTL_B1 BIT(1) 71 #define TMC_AXICTL_SCT_GAT_MODE BIT(7) 72 #define TMC_AXICTL_WR_BURST_16 0xF00 73 /* Write-back Read and Write-allocate */ 74 #define TMC_AXICTL_AXCACHE_OS (0xf << 2) 75 #define TMC_AXICTL_ARCACHE_OS (0xf << 16) 76 77 /* TMC_FFCR - 0x304 */ 78 #define TMC_FFCR_FLUSHMAN_BIT 6 79 #define TMC_FFCR_EN_FMT BIT(0) 80 #define TMC_FFCR_EN_TI BIT(1) 81 #define TMC_FFCR_FON_FLIN BIT(4) 82 #define TMC_FFCR_FON_TRIG_EVT BIT(5) 83 #define TMC_FFCR_TRIGON_TRIGIN BIT(8) 84 #define TMC_FFCR_STOP_ON_FLUSH BIT(12) 85 86 87 #define TMC_DEVID_NOSCAT BIT(24) 88 89 #define TMC_DEVID_AXIAW_VALID BIT(16) 90 #define TMC_DEVID_AXIAW_SHIFT 17 91 #define TMC_DEVID_AXIAW_MASK 0x7f 92 93 enum tmc_config_type { 94 TMC_CONFIG_TYPE_ETB, 95 TMC_CONFIG_TYPE_ETR, 96 TMC_CONFIG_TYPE_ETF, 97 }; 98 99 enum tmc_mode { 100 TMC_MODE_CIRCULAR_BUFFER, 101 TMC_MODE_SOFTWARE_FIFO, 102 TMC_MODE_HARDWARE_FIFO, 103 }; 104 105 enum tmc_mem_intf_width { 106 TMC_MEM_INTF_WIDTH_32BITS = 1, 107 TMC_MEM_INTF_WIDTH_64BITS = 2, 108 TMC_MEM_INTF_WIDTH_128BITS = 4, 109 TMC_MEM_INTF_WIDTH_256BITS = 8, 110 }; 111 112 /* TMC ETR Capability bit definitions */ 113 #define TMC_ETR_SG (0x1U << 0) 114 /* ETR has separate read/write cache encodings */ 115 #define TMC_ETR_AXI_ARCACHE (0x1U << 1) 116 /* 117 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are 118 * retained when TMC leaves Disabled state, allowing us to continue 119 * the tracing from a point where we stopped. This also implies that 120 * the RRP/RWP/STS.Full should always be programmed to the correct 121 * value. Unfortunately this is not advertised by the hardware, 122 * so we have to rely on PID of the IP to detect the functionality. 123 */ 124 #define TMC_ETR_SAVE_RESTORE (0x1U << 2) 125 126 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */ 127 #define CORESIGHT_SOC_600_ETR_CAPS \ 128 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) 129 130 enum etr_mode { 131 ETR_MODE_FLAT, /* Uses contiguous flat buffer */ 132 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ 133 ETR_MODE_CATU, /* Use SG mechanism in CATU */ 134 }; 135 136 struct etr_buf_operations; 137 138 /** 139 * struct etr_buf - Details of the buffer used by ETR 140 * refcount ; Number of sources currently using this etr_buf. 141 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. 142 * @full : Trace data overflow 143 * @size : Size of the buffer. 144 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI} 145 * @offset : Offset of the trace data in the buffer for consumption. 146 * @len : Available trace data @buf (may round up to the beginning). 147 * @ops : ETR buffer operations for the mode. 148 * @private : Backend specific information for the buf 149 */ 150 struct etr_buf { 151 refcount_t refcount; 152 enum etr_mode mode; 153 bool full; 154 ssize_t size; 155 dma_addr_t hwaddr; 156 unsigned long offset; 157 s64 len; 158 const struct etr_buf_operations *ops; 159 void *private; 160 }; 161 162 /** 163 * struct tmc_drvdata - specifics associated to an TMC component 164 * @base: memory mapped base address for this component. 165 * @csdev: component vitals needed by the framework. 166 * @miscdev: specifics to handle "/dev/xyz.tmc" entry. 167 * @spinlock: only one at a time pls. 168 * @pid: Process ID of the process being monitored by the session 169 * that is using this component. 170 * @buf: Snapshot of the trace data for ETF/ETB. 171 * @etr_buf: details of buffer used in TMC-ETR 172 * @len: size of the available trace for ETF/ETB. 173 * @size: trace buffer size for this TMC (common for all modes). 174 * @mode: how this TMC is being used. 175 * @config_type: TMC variant, must be of type @tmc_config_type. 176 * @memwidth: width of the memory interface databus, in bytes. 177 * @trigger_cntr: amount of words to store after a trigger. 178 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the 179 * device configuration register (DEVID) 180 * @idr: Holds etr_bufs allocated for this ETR. 181 * @idr_mutex: Access serialisation for idr. 182 * @perf_data: PERF buffer for ETR. 183 * @sysfs_data: SYSFS buffer for ETR. 184 */ 185 struct tmc_drvdata { 186 void __iomem *base; 187 struct coresight_device *csdev; 188 struct miscdevice miscdev; 189 spinlock_t spinlock; 190 pid_t pid; 191 bool reading; 192 union { 193 char *buf; /* TMC ETB */ 194 struct etr_buf *etr_buf; /* TMC ETR */ 195 }; 196 u32 len; 197 u32 size; 198 u32 mode; 199 enum tmc_config_type config_type; 200 enum tmc_mem_intf_width memwidth; 201 u32 trigger_cntr; 202 u32 etr_caps; 203 struct idr idr; 204 struct mutex idr_mutex; 205 struct etr_buf *sysfs_buf; 206 void *perf_data; 207 }; 208 209 struct etr_buf_operations { 210 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf, 211 int node, void **pages); 212 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp); 213 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len, 214 char **bufpp); 215 void (*free)(struct etr_buf *etr_buf); 216 }; 217 218 /** 219 * struct tmc_pages - Collection of pages used for SG. 220 * @nr_pages: Number of pages in the list. 221 * @daddrs: Array of DMA'able page address. 222 * @pages: Array pages for the buffer. 223 */ 224 struct tmc_pages { 225 int nr_pages; 226 dma_addr_t *daddrs; 227 struct page **pages; 228 }; 229 230 /* 231 * struct tmc_sg_table - Generic SG table for TMC 232 * @dev: Device for DMA allocations 233 * @table_vaddr: Contiguous Virtual address for PageTable 234 * @data_vaddr: Contiguous Virtual address for Data Buffer 235 * @table_daddr: DMA address of the PageTable base 236 * @node: Node for Page allocations 237 * @table_pages: List of pages & dma address for Table 238 * @data_pages: List of pages & dma address for Data 239 */ 240 struct tmc_sg_table { 241 struct device *dev; 242 void *table_vaddr; 243 void *data_vaddr; 244 dma_addr_t table_daddr; 245 int node; 246 struct tmc_pages table_pages; 247 struct tmc_pages data_pages; 248 }; 249 250 /* Generic functions */ 251 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 252 void tmc_flush_and_stop(struct tmc_drvdata *drvdata); 253 void tmc_enable_hw(struct tmc_drvdata *drvdata); 254 void tmc_disable_hw(struct tmc_drvdata *drvdata); 255 256 /* ETB/ETF functions */ 257 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); 258 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); 259 extern const struct coresight_ops tmc_etb_cs_ops; 260 extern const struct coresight_ops tmc_etf_cs_ops; 261 262 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata, 263 loff_t pos, size_t len, char **bufpp); 264 /* ETR functions */ 265 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); 266 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); 267 extern const struct coresight_ops tmc_etr_cs_ops; 268 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, 269 loff_t pos, size_t len, char **bufpp); 270 271 272 #define TMC_REG_PAIR(name, lo_off, hi_off) \ 273 static inline u64 \ 274 tmc_read_##name(struct tmc_drvdata *drvdata) \ 275 { \ 276 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ 277 } \ 278 static inline void \ 279 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ 280 { \ 281 coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ 282 } 283 284 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) 285 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) 286 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) 287 288 /* Initialise the caps from unadvertised static capabilities of the device */ 289 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) 290 { 291 WARN_ON(drvdata->etr_caps); 292 drvdata->etr_caps = dev_caps; 293 } 294 295 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap) 296 { 297 drvdata->etr_caps |= cap; 298 } 299 300 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap) 301 { 302 return !!(drvdata->etr_caps & cap); 303 } 304 305 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev, 306 int node, 307 int nr_tpages, 308 int nr_dpages, 309 void **pages); 310 void tmc_free_sg_table(struct tmc_sg_table *sg_table); 311 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table); 312 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table, 313 u64 offset, u64 size); 314 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, 315 u64 offset, size_t len, char **bufpp); 316 static inline unsigned long 317 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) 318 { 319 return sg_table->data_pages.nr_pages << PAGE_SHIFT; 320 } 321 322 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); 323 324 #endif 325