1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_TMC_H 8 #define _CORESIGHT_TMC_H 9 10 #include <linux/dma-mapping.h> 11 #include <linux/idr.h> 12 #include <linux/miscdevice.h> 13 #include <linux/mutex.h> 14 #include <linux/refcount.h> 15 16 #define TMC_RSZ 0x004 17 #define TMC_STS 0x00c 18 #define TMC_RRD 0x010 19 #define TMC_RRP 0x014 20 #define TMC_RWP 0x018 21 #define TMC_TRG 0x01c 22 #define TMC_CTL 0x020 23 #define TMC_RWD 0x024 24 #define TMC_MODE 0x028 25 #define TMC_LBUFLEVEL 0x02c 26 #define TMC_CBUFLEVEL 0x030 27 #define TMC_BUFWM 0x034 28 #define TMC_RRPHI 0x038 29 #define TMC_RWPHI 0x03c 30 #define TMC_AXICTL 0x110 31 #define TMC_DBALO 0x118 32 #define TMC_DBAHI 0x11c 33 #define TMC_FFSR 0x300 34 #define TMC_FFCR 0x304 35 #define TMC_PSCR 0x308 36 #define TMC_ITMISCOP0 0xee0 37 #define TMC_ITTRFLIN 0xee8 38 #define TMC_ITATBDATA0 0xeec 39 #define TMC_ITATBCTR2 0xef0 40 #define TMC_ITATBCTR1 0xef4 41 #define TMC_ITATBCTR0 0xef8 42 43 /* register description */ 44 /* TMC_CTL - 0x020 */ 45 #define TMC_CTL_CAPT_EN BIT(0) 46 /* TMC_STS - 0x00C */ 47 #define TMC_STS_TMCREADY_BIT 2 48 #define TMC_STS_FULL BIT(0) 49 #define TMC_STS_TRIGGERED BIT(1) 50 /* 51 * TMC_AXICTL - 0x110 52 * 53 * TMC AXICTL format for SoC-400 54 * Bits [0-1] : ProtCtrlBit0-1 55 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE) 56 * Bit 6 : Reserved 57 * Bit 7 : ScatterGatherMode 58 * Bits [8-11] : WrBurstLen 59 * Bits [12-31] : Reserved. 60 * TMC AXICTL format for SoC-600, as above except: 61 * Bits [2-5] : AXI WCACHE 62 * Bits [16-19] : AXI RCACHE 63 * Bits [20-31] : Reserved 64 */ 65 #define TMC_AXICTL_CLEAR_MASK 0xfbf 66 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16) 67 68 #define TMC_AXICTL_PROT_CTL_B0 BIT(0) 69 #define TMC_AXICTL_PROT_CTL_B1 BIT(1) 70 #define TMC_AXICTL_SCT_GAT_MODE BIT(7) 71 #define TMC_AXICTL_WR_BURST_16 0xF00 72 /* Write-back Read and Write-allocate */ 73 #define TMC_AXICTL_AXCACHE_OS (0xf << 2) 74 #define TMC_AXICTL_ARCACHE_OS (0xf << 16) 75 76 /* TMC_FFCR - 0x304 */ 77 #define TMC_FFCR_FLUSHMAN_BIT 6 78 #define TMC_FFCR_EN_FMT BIT(0) 79 #define TMC_FFCR_EN_TI BIT(1) 80 #define TMC_FFCR_FON_FLIN BIT(4) 81 #define TMC_FFCR_FON_TRIG_EVT BIT(5) 82 #define TMC_FFCR_TRIGON_TRIGIN BIT(8) 83 #define TMC_FFCR_STOP_ON_FLUSH BIT(12) 84 85 86 #define TMC_DEVID_NOSCAT BIT(24) 87 88 #define TMC_DEVID_AXIAW_VALID BIT(16) 89 #define TMC_DEVID_AXIAW_SHIFT 17 90 #define TMC_DEVID_AXIAW_MASK 0x7f 91 92 enum tmc_config_type { 93 TMC_CONFIG_TYPE_ETB, 94 TMC_CONFIG_TYPE_ETR, 95 TMC_CONFIG_TYPE_ETF, 96 }; 97 98 enum tmc_mode { 99 TMC_MODE_CIRCULAR_BUFFER, 100 TMC_MODE_SOFTWARE_FIFO, 101 TMC_MODE_HARDWARE_FIFO, 102 }; 103 104 enum tmc_mem_intf_width { 105 TMC_MEM_INTF_WIDTH_32BITS = 1, 106 TMC_MEM_INTF_WIDTH_64BITS = 2, 107 TMC_MEM_INTF_WIDTH_128BITS = 4, 108 TMC_MEM_INTF_WIDTH_256BITS = 8, 109 }; 110 111 /* TMC ETR Capability bit definitions */ 112 #define TMC_ETR_SG (0x1U << 0) 113 /* ETR has separate read/write cache encodings */ 114 #define TMC_ETR_AXI_ARCACHE (0x1U << 1) 115 /* 116 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are 117 * retained when TMC leaves Disabled state, allowing us to continue 118 * the tracing from a point where we stopped. This also implies that 119 * the RRP/RWP/STS.Full should always be programmed to the correct 120 * value. Unfortunately this is not advertised by the hardware, 121 * so we have to rely on PID of the IP to detect the functionality. 122 */ 123 #define TMC_ETR_SAVE_RESTORE (0x1U << 2) 124 125 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */ 126 #define CORESIGHT_SOC_600_ETR_CAPS \ 127 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) 128 129 enum etr_mode { 130 ETR_MODE_FLAT, /* Uses contiguous flat buffer */ 131 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ 132 ETR_MODE_CATU, /* Use SG mechanism in CATU */ 133 }; 134 135 struct etr_buf_operations; 136 137 /** 138 * struct etr_buf - Details of the buffer used by ETR 139 * refcount ; Number of sources currently using this etr_buf. 140 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. 141 * @full : Trace data overflow 142 * @size : Size of the buffer. 143 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI} 144 * @offset : Offset of the trace data in the buffer for consumption. 145 * @len : Available trace data @buf (may round up to the beginning). 146 * @ops : ETR buffer operations for the mode. 147 * @private : Backend specific information for the buf 148 */ 149 struct etr_buf { 150 refcount_t refcount; 151 enum etr_mode mode; 152 bool full; 153 ssize_t size; 154 dma_addr_t hwaddr; 155 unsigned long offset; 156 s64 len; 157 const struct etr_buf_operations *ops; 158 void *private; 159 }; 160 161 /** 162 * struct tmc_drvdata - specifics associated to an TMC component 163 * @base: memory mapped base address for this component. 164 * @csdev: component vitals needed by the framework. 165 * @miscdev: specifics to handle "/dev/xyz.tmc" entry. 166 * @spinlock: only one at a time pls. 167 * @pid: Process ID of the process being monitored by the session 168 * that is using this component. 169 * @buf: Snapshot of the trace data for ETF/ETB. 170 * @etr_buf: details of buffer used in TMC-ETR 171 * @len: size of the available trace for ETF/ETB. 172 * @size: trace buffer size for this TMC (common for all modes). 173 * @mode: how this TMC is being used. 174 * @config_type: TMC variant, must be of type @tmc_config_type. 175 * @memwidth: width of the memory interface databus, in bytes. 176 * @trigger_cntr: amount of words to store after a trigger. 177 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the 178 * device configuration register (DEVID) 179 * @idr: Holds etr_bufs allocated for this ETR. 180 * @idr_mutex: Access serialisation for idr. 181 * @perf_data: PERF buffer for ETR. 182 * @sysfs_data: SYSFS buffer for ETR. 183 */ 184 struct tmc_drvdata { 185 void __iomem *base; 186 struct coresight_device *csdev; 187 struct miscdevice miscdev; 188 spinlock_t spinlock; 189 pid_t pid; 190 bool reading; 191 union { 192 char *buf; /* TMC ETB */ 193 struct etr_buf *etr_buf; /* TMC ETR */ 194 }; 195 u32 len; 196 u32 size; 197 u32 mode; 198 enum tmc_config_type config_type; 199 enum tmc_mem_intf_width memwidth; 200 u32 trigger_cntr; 201 u32 etr_caps; 202 struct idr idr; 203 struct mutex idr_mutex; 204 struct etr_buf *sysfs_buf; 205 void *perf_data; 206 }; 207 208 struct etr_buf_operations { 209 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf, 210 int node, void **pages); 211 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp); 212 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len, 213 char **bufpp); 214 void (*free)(struct etr_buf *etr_buf); 215 }; 216 217 /** 218 * struct tmc_pages - Collection of pages used for SG. 219 * @nr_pages: Number of pages in the list. 220 * @daddrs: Array of DMA'able page address. 221 * @pages: Array pages for the buffer. 222 */ 223 struct tmc_pages { 224 int nr_pages; 225 dma_addr_t *daddrs; 226 struct page **pages; 227 }; 228 229 /* 230 * struct tmc_sg_table - Generic SG table for TMC 231 * @dev: Device for DMA allocations 232 * @table_vaddr: Contiguous Virtual address for PageTable 233 * @data_vaddr: Contiguous Virtual address for Data Buffer 234 * @table_daddr: DMA address of the PageTable base 235 * @node: Node for Page allocations 236 * @table_pages: List of pages & dma address for Table 237 * @data_pages: List of pages & dma address for Data 238 */ 239 struct tmc_sg_table { 240 struct device *dev; 241 void *table_vaddr; 242 void *data_vaddr; 243 dma_addr_t table_daddr; 244 int node; 245 struct tmc_pages table_pages; 246 struct tmc_pages data_pages; 247 }; 248 249 /* Generic functions */ 250 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 251 void tmc_flush_and_stop(struct tmc_drvdata *drvdata); 252 void tmc_enable_hw(struct tmc_drvdata *drvdata); 253 void tmc_disable_hw(struct tmc_drvdata *drvdata); 254 255 /* ETB/ETF functions */ 256 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); 257 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); 258 extern const struct coresight_ops tmc_etb_cs_ops; 259 extern const struct coresight_ops tmc_etf_cs_ops; 260 261 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata, 262 loff_t pos, size_t len, char **bufpp); 263 /* ETR functions */ 264 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); 265 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); 266 extern const struct coresight_ops tmc_etr_cs_ops; 267 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, 268 loff_t pos, size_t len, char **bufpp); 269 270 271 #define TMC_REG_PAIR(name, lo_off, hi_off) \ 272 static inline u64 \ 273 tmc_read_##name(struct tmc_drvdata *drvdata) \ 274 { \ 275 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ 276 } \ 277 static inline void \ 278 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ 279 { \ 280 coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ 281 } 282 283 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) 284 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) 285 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) 286 287 /* Initialise the caps from unadvertised static capabilities of the device */ 288 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) 289 { 290 WARN_ON(drvdata->etr_caps); 291 drvdata->etr_caps = dev_caps; 292 } 293 294 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap) 295 { 296 drvdata->etr_caps |= cap; 297 } 298 299 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap) 300 { 301 return !!(drvdata->etr_caps & cap); 302 } 303 304 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev, 305 int node, 306 int nr_tpages, 307 int nr_dpages, 308 void **pages); 309 void tmc_free_sg_table(struct tmc_sg_table *sg_table); 310 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table); 311 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table, 312 u64 offset, u64 size); 313 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, 314 u64 offset, size_t len, char **bufpp); 315 static inline unsigned long 316 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) 317 { 318 return sg_table->data_pages.nr_pages << PAGE_SHIFT; 319 } 320 321 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); 322 323 #endif 324