1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_TMC_H 8 #define _CORESIGHT_TMC_H 9 10 #include <linux/dma-mapping.h> 11 #include <linux/idr.h> 12 #include <linux/miscdevice.h> 13 #include <linux/mutex.h> 14 #include <linux/refcount.h> 15 16 #define TMC_RSZ 0x004 17 #define TMC_STS 0x00c 18 #define TMC_RRD 0x010 19 #define TMC_RRP 0x014 20 #define TMC_RWP 0x018 21 #define TMC_TRG 0x01c 22 #define TMC_CTL 0x020 23 #define TMC_RWD 0x024 24 #define TMC_MODE 0x028 25 #define TMC_LBUFLEVEL 0x02c 26 #define TMC_CBUFLEVEL 0x030 27 #define TMC_BUFWM 0x034 28 #define TMC_RRPHI 0x038 29 #define TMC_RWPHI 0x03c 30 #define TMC_AXICTL 0x110 31 #define TMC_DBALO 0x118 32 #define TMC_DBAHI 0x11c 33 #define TMC_FFSR 0x300 34 #define TMC_FFCR 0x304 35 #define TMC_PSCR 0x308 36 #define TMC_ITMISCOP0 0xee0 37 #define TMC_ITTRFLIN 0xee8 38 #define TMC_ITATBDATA0 0xeec 39 #define TMC_ITATBCTR2 0xef0 40 #define TMC_ITATBCTR1 0xef4 41 #define TMC_ITATBCTR0 0xef8 42 #define TMC_AUTHSTATUS 0xfb8 43 44 /* register description */ 45 /* TMC_CTL - 0x020 */ 46 #define TMC_CTL_CAPT_EN BIT(0) 47 /* TMC_STS - 0x00C */ 48 #define TMC_STS_TMCREADY_BIT 2 49 #define TMC_STS_FULL BIT(0) 50 #define TMC_STS_TRIGGERED BIT(1) 51 #define TMC_STS_MEMERR BIT(5) 52 /* 53 * TMC_AXICTL - 0x110 54 * 55 * TMC AXICTL format for SoC-400 56 * Bits [0-1] : ProtCtrlBit0-1 57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE) 58 * Bit 6 : Reserved 59 * Bit 7 : ScatterGatherMode 60 * Bits [8-11] : WrBurstLen 61 * Bits [12-31] : Reserved. 62 * TMC AXICTL format for SoC-600, as above except: 63 * Bits [2-5] : AXI WCACHE 64 * Bits [16-19] : AXI RCACHE 65 * Bits [20-31] : Reserved 66 */ 67 #define TMC_AXICTL_CLEAR_MASK 0xfbf 68 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16) 69 70 #define TMC_AXICTL_PROT_CTL_B0 BIT(0) 71 #define TMC_AXICTL_PROT_CTL_B1 BIT(1) 72 #define TMC_AXICTL_SCT_GAT_MODE BIT(7) 73 #define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8) 74 #define TMC_AXICTL_WR_BURST_16 0xf 75 /* Write-back Read and Write-allocate */ 76 #define TMC_AXICTL_AXCACHE_OS (0xf << 2) 77 #define TMC_AXICTL_ARCACHE_OS (0xf << 16) 78 79 /* TMC_FFCR - 0x304 */ 80 #define TMC_FFCR_FLUSHMAN_BIT 6 81 #define TMC_FFCR_EN_FMT BIT(0) 82 #define TMC_FFCR_EN_TI BIT(1) 83 #define TMC_FFCR_FON_FLIN BIT(4) 84 #define TMC_FFCR_FON_TRIG_EVT BIT(5) 85 #define TMC_FFCR_TRIGON_TRIGIN BIT(8) 86 #define TMC_FFCR_STOP_ON_FLUSH BIT(12) 87 88 89 #define TMC_DEVID_NOSCAT BIT(24) 90 91 #define TMC_DEVID_AXIAW_VALID BIT(16) 92 #define TMC_DEVID_AXIAW_SHIFT 17 93 #define TMC_DEVID_AXIAW_MASK 0x7f 94 95 #define TMC_AUTH_NSID_MASK GENMASK(1, 0) 96 97 enum tmc_config_type { 98 TMC_CONFIG_TYPE_ETB, 99 TMC_CONFIG_TYPE_ETR, 100 TMC_CONFIG_TYPE_ETF, 101 }; 102 103 enum tmc_mode { 104 TMC_MODE_CIRCULAR_BUFFER, 105 TMC_MODE_SOFTWARE_FIFO, 106 TMC_MODE_HARDWARE_FIFO, 107 }; 108 109 enum tmc_mem_intf_width { 110 TMC_MEM_INTF_WIDTH_32BITS = 1, 111 TMC_MEM_INTF_WIDTH_64BITS = 2, 112 TMC_MEM_INTF_WIDTH_128BITS = 4, 113 TMC_MEM_INTF_WIDTH_256BITS = 8, 114 }; 115 116 /* TMC ETR Capability bit definitions */ 117 #define TMC_ETR_SG (0x1U << 0) 118 /* ETR has separate read/write cache encodings */ 119 #define TMC_ETR_AXI_ARCACHE (0x1U << 1) 120 /* 121 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are 122 * retained when TMC leaves Disabled state, allowing us to continue 123 * the tracing from a point where we stopped. This also implies that 124 * the RRP/RWP/STS.Full should always be programmed to the correct 125 * value. Unfortunately this is not advertised by the hardware, 126 * so we have to rely on PID of the IP to detect the functionality. 127 */ 128 #define TMC_ETR_SAVE_RESTORE (0x1U << 2) 129 130 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */ 131 #define CORESIGHT_SOC_600_ETR_CAPS \ 132 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) 133 134 enum etr_mode { 135 ETR_MODE_FLAT, /* Uses contiguous flat buffer */ 136 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ 137 ETR_MODE_CATU, /* Use SG mechanism in CATU */ 138 }; 139 140 struct etr_buf_operations; 141 142 /** 143 * struct etr_buf - Details of the buffer used by ETR 144 * refcount ; Number of sources currently using this etr_buf. 145 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. 146 * @full : Trace data overflow 147 * @size : Size of the buffer. 148 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI} 149 * @offset : Offset of the trace data in the buffer for consumption. 150 * @len : Available trace data @buf (may round up to the beginning). 151 * @ops : ETR buffer operations for the mode. 152 * @private : Backend specific information for the buf 153 */ 154 struct etr_buf { 155 refcount_t refcount; 156 enum etr_mode mode; 157 bool full; 158 ssize_t size; 159 dma_addr_t hwaddr; 160 unsigned long offset; 161 s64 len; 162 const struct etr_buf_operations *ops; 163 void *private; 164 }; 165 166 /** 167 * struct tmc_drvdata - specifics associated to an TMC component 168 * @base: memory mapped base address for this component. 169 * @csdev: component vitals needed by the framework. 170 * @miscdev: specifics to handle "/dev/xyz.tmc" entry. 171 * @spinlock: only one at a time pls. 172 * @pid: Process ID of the process being monitored by the session 173 * that is using this component. 174 * @buf: Snapshot of the trace data for ETF/ETB. 175 * @etr_buf: details of buffer used in TMC-ETR 176 * @len: size of the available trace for ETF/ETB. 177 * @size: trace buffer size for this TMC (common for all modes). 178 * @max_burst_size: The maximum burst size that can be initiated by 179 * TMC-ETR on AXI bus. 180 * @mode: how this TMC is being used. 181 * @config_type: TMC variant, must be of type @tmc_config_type. 182 * @memwidth: width of the memory interface databus, in bytes. 183 * @trigger_cntr: amount of words to store after a trigger. 184 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the 185 * device configuration register (DEVID) 186 * @idr: Holds etr_bufs allocated for this ETR. 187 * @idr_mutex: Access serialisation for idr. 188 * @sysfs_buf: SYSFS buffer for ETR. 189 * @perf_buf: PERF buffer for ETR. 190 */ 191 struct tmc_drvdata { 192 void __iomem *base; 193 struct coresight_device *csdev; 194 struct miscdevice miscdev; 195 spinlock_t spinlock; 196 pid_t pid; 197 bool reading; 198 union { 199 char *buf; /* TMC ETB */ 200 struct etr_buf *etr_buf; /* TMC ETR */ 201 }; 202 u32 len; 203 u32 size; 204 u32 max_burst_size; 205 u32 mode; 206 enum tmc_config_type config_type; 207 enum tmc_mem_intf_width memwidth; 208 u32 trigger_cntr; 209 u32 etr_caps; 210 struct idr idr; 211 struct mutex idr_mutex; 212 struct etr_buf *sysfs_buf; 213 struct etr_buf *perf_buf; 214 }; 215 216 struct etr_buf_operations { 217 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf, 218 int node, void **pages); 219 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp); 220 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len, 221 char **bufpp); 222 void (*free)(struct etr_buf *etr_buf); 223 }; 224 225 /** 226 * struct tmc_pages - Collection of pages used for SG. 227 * @nr_pages: Number of pages in the list. 228 * @daddrs: Array of DMA'able page address. 229 * @pages: Array pages for the buffer. 230 */ 231 struct tmc_pages { 232 int nr_pages; 233 dma_addr_t *daddrs; 234 struct page **pages; 235 }; 236 237 /* 238 * struct tmc_sg_table - Generic SG table for TMC 239 * @dev: Device for DMA allocations 240 * @table_vaddr: Contiguous Virtual address for PageTable 241 * @data_vaddr: Contiguous Virtual address for Data Buffer 242 * @table_daddr: DMA address of the PageTable base 243 * @node: Node for Page allocations 244 * @table_pages: List of pages & dma address for Table 245 * @data_pages: List of pages & dma address for Data 246 */ 247 struct tmc_sg_table { 248 struct device *dev; 249 void *table_vaddr; 250 void *data_vaddr; 251 dma_addr_t table_daddr; 252 int node; 253 struct tmc_pages table_pages; 254 struct tmc_pages data_pages; 255 }; 256 257 /* Generic functions */ 258 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 259 void tmc_flush_and_stop(struct tmc_drvdata *drvdata); 260 void tmc_enable_hw(struct tmc_drvdata *drvdata); 261 void tmc_disable_hw(struct tmc_drvdata *drvdata); 262 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); 263 264 /* ETB/ETF functions */ 265 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); 266 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); 267 extern const struct coresight_ops tmc_etb_cs_ops; 268 extern const struct coresight_ops tmc_etf_cs_ops; 269 270 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata, 271 loff_t pos, size_t len, char **bufpp); 272 /* ETR functions */ 273 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); 274 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); 275 void tmc_etr_disable_hw(struct tmc_drvdata *drvdata); 276 extern const struct coresight_ops tmc_etr_cs_ops; 277 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, 278 loff_t pos, size_t len, char **bufpp); 279 280 281 #define TMC_REG_PAIR(name, lo_off, hi_off) \ 282 static inline u64 \ 283 tmc_read_##name(struct tmc_drvdata *drvdata) \ 284 { \ 285 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \ 286 } \ 287 static inline void \ 288 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ 289 { \ 290 csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \ 291 } 292 293 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) 294 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) 295 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) 296 297 /* Initialise the caps from unadvertised static capabilities of the device */ 298 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) 299 { 300 WARN_ON(drvdata->etr_caps); 301 drvdata->etr_caps = dev_caps; 302 } 303 304 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap) 305 { 306 drvdata->etr_caps |= cap; 307 } 308 309 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap) 310 { 311 return !!(drvdata->etr_caps & cap); 312 } 313 314 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev, 315 int node, 316 int nr_tpages, 317 int nr_dpages, 318 void **pages); 319 void tmc_free_sg_table(struct tmc_sg_table *sg_table); 320 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table); 321 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table, 322 u64 offset, u64 size); 323 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, 324 u64 offset, size_t len, char **bufpp); 325 static inline unsigned long 326 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) 327 { 328 return sg_table->data_pages.nr_pages << PAGE_SHIFT; 329 } 330 331 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); 332 333 void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); 334 void tmc_etr_remove_catu_ops(void); 335 336 #endif 337