1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_TMC_H 8 #define _CORESIGHT_TMC_H 9 10 #include <linux/miscdevice.h> 11 12 #define TMC_RSZ 0x004 13 #define TMC_STS 0x00c 14 #define TMC_RRD 0x010 15 #define TMC_RRP 0x014 16 #define TMC_RWP 0x018 17 #define TMC_TRG 0x01c 18 #define TMC_CTL 0x020 19 #define TMC_RWD 0x024 20 #define TMC_MODE 0x028 21 #define TMC_LBUFLEVEL 0x02c 22 #define TMC_CBUFLEVEL 0x030 23 #define TMC_BUFWM 0x034 24 #define TMC_RRPHI 0x038 25 #define TMC_RWPHI 0x03c 26 #define TMC_AXICTL 0x110 27 #define TMC_DBALO 0x118 28 #define TMC_DBAHI 0x11c 29 #define TMC_FFSR 0x300 30 #define TMC_FFCR 0x304 31 #define TMC_PSCR 0x308 32 #define TMC_ITMISCOP0 0xee0 33 #define TMC_ITTRFLIN 0xee8 34 #define TMC_ITATBDATA0 0xeec 35 #define TMC_ITATBCTR2 0xef0 36 #define TMC_ITATBCTR1 0xef4 37 #define TMC_ITATBCTR0 0xef8 38 39 /* register description */ 40 /* TMC_CTL - 0x020 */ 41 #define TMC_CTL_CAPT_EN BIT(0) 42 /* TMC_STS - 0x00C */ 43 #define TMC_STS_TMCREADY_BIT 2 44 #define TMC_STS_FULL BIT(0) 45 #define TMC_STS_TRIGGERED BIT(1) 46 /* 47 * TMC_AXICTL - 0x110 48 * 49 * TMC AXICTL format for SoC-400 50 * Bits [0-1] : ProtCtrlBit0-1 51 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE) 52 * Bit 6 : Reserved 53 * Bit 7 : ScatterGatherMode 54 * Bits [8-11] : WrBurstLen 55 * Bits [12-31] : Reserved. 56 * TMC AXICTL format for SoC-600, as above except: 57 * Bits [2-5] : AXI WCACHE 58 * Bits [16-19] : AXI RCACHE 59 * Bits [20-31] : Reserved 60 */ 61 #define TMC_AXICTL_CLEAR_MASK 0xfbf 62 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16) 63 64 #define TMC_AXICTL_PROT_CTL_B0 BIT(0) 65 #define TMC_AXICTL_PROT_CTL_B1 BIT(1) 66 #define TMC_AXICTL_SCT_GAT_MODE BIT(7) 67 #define TMC_AXICTL_WR_BURST_16 0xF00 68 /* Write-back Read and Write-allocate */ 69 #define TMC_AXICTL_AXCACHE_OS (0xf << 2) 70 #define TMC_AXICTL_ARCACHE_OS (0xf << 16) 71 72 /* TMC_FFCR - 0x304 */ 73 #define TMC_FFCR_FLUSHMAN_BIT 6 74 #define TMC_FFCR_EN_FMT BIT(0) 75 #define TMC_FFCR_EN_TI BIT(1) 76 #define TMC_FFCR_FON_FLIN BIT(4) 77 #define TMC_FFCR_FON_TRIG_EVT BIT(5) 78 #define TMC_FFCR_TRIGON_TRIGIN BIT(8) 79 #define TMC_FFCR_STOP_ON_FLUSH BIT(12) 80 81 82 #define TMC_DEVID_NOSCAT BIT(24) 83 84 #define TMC_DEVID_AXIAW_VALID BIT(16) 85 #define TMC_DEVID_AXIAW_SHIFT 17 86 #define TMC_DEVID_AXIAW_MASK 0x7f 87 88 enum tmc_config_type { 89 TMC_CONFIG_TYPE_ETB, 90 TMC_CONFIG_TYPE_ETR, 91 TMC_CONFIG_TYPE_ETF, 92 }; 93 94 enum tmc_mode { 95 TMC_MODE_CIRCULAR_BUFFER, 96 TMC_MODE_SOFTWARE_FIFO, 97 TMC_MODE_HARDWARE_FIFO, 98 }; 99 100 enum tmc_mem_intf_width { 101 TMC_MEM_INTF_WIDTH_32BITS = 1, 102 TMC_MEM_INTF_WIDTH_64BITS = 2, 103 TMC_MEM_INTF_WIDTH_128BITS = 4, 104 TMC_MEM_INTF_WIDTH_256BITS = 8, 105 }; 106 107 /* TMC ETR Capability bit definitions */ 108 #define TMC_ETR_SG (0x1U << 0) 109 /* ETR has separate read/write cache encodings */ 110 #define TMC_ETR_AXI_ARCACHE (0x1U << 1) 111 /* 112 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are 113 * retained when TMC leaves Disabled state, allowing us to continue 114 * the tracing from a point where we stopped. This also implies that 115 * the RRP/RWP/STS.Full should always be programmed to the correct 116 * value. Unfortunately this is not advertised by the hardware, 117 * so we have to rely on PID of the IP to detect the functionality. 118 */ 119 #define TMC_ETR_SAVE_RESTORE (0x1U << 2) 120 121 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */ 122 #define CORESIGHT_SOC_600_ETR_CAPS \ 123 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) 124 125 /** 126 * struct tmc_drvdata - specifics associated to an TMC component 127 * @base: memory mapped base address for this component. 128 * @dev: the device entity associated to this component. 129 * @csdev: component vitals needed by the framework. 130 * @miscdev: specifics to handle "/dev/xyz.tmc" entry. 131 * @spinlock: only one at a time pls. 132 * @buf: area of memory where trace data get sent. 133 * @paddr: DMA start location in RAM. 134 * @vaddr: virtual representation of @paddr. 135 * @size: trace buffer size. 136 * @len: size of the available trace. 137 * @mode: how this TMC is being used. 138 * @config_type: TMC variant, must be of type @tmc_config_type. 139 * @memwidth: width of the memory interface databus, in bytes. 140 * @trigger_cntr: amount of words to store after a trigger. 141 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the 142 * device configuration register (DEVID) 143 */ 144 struct tmc_drvdata { 145 void __iomem *base; 146 struct device *dev; 147 struct coresight_device *csdev; 148 struct miscdevice miscdev; 149 spinlock_t spinlock; 150 bool reading; 151 char *buf; 152 dma_addr_t paddr; 153 void __iomem *vaddr; 154 u32 size; 155 u32 len; 156 u32 mode; 157 enum tmc_config_type config_type; 158 enum tmc_mem_intf_width memwidth; 159 u32 trigger_cntr; 160 u32 etr_caps; 161 }; 162 163 /* Generic functions */ 164 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 165 void tmc_flush_and_stop(struct tmc_drvdata *drvdata); 166 void tmc_enable_hw(struct tmc_drvdata *drvdata); 167 void tmc_disable_hw(struct tmc_drvdata *drvdata); 168 169 /* ETB/ETF functions */ 170 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); 171 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); 172 extern const struct coresight_ops tmc_etb_cs_ops; 173 extern const struct coresight_ops tmc_etf_cs_ops; 174 175 /* ETR functions */ 176 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); 177 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); 178 extern const struct coresight_ops tmc_etr_cs_ops; 179 180 181 #define TMC_REG_PAIR(name, lo_off, hi_off) \ 182 static inline u64 \ 183 tmc_read_##name(struct tmc_drvdata *drvdata) \ 184 { \ 185 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ 186 } \ 187 static inline void \ 188 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ 189 { \ 190 coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ 191 } 192 193 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) 194 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) 195 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) 196 197 /* Initialise the caps from unadvertised static capabilities of the device */ 198 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) 199 { 200 WARN_ON(drvdata->etr_caps); 201 drvdata->etr_caps = dev_caps; 202 } 203 204 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap) 205 { 206 drvdata->etr_caps |= cap; 207 } 208 209 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap) 210 { 211 return !!(drvdata->etr_caps & cap); 212 } 213 214 #endif 215