1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_TMC_H 8 #define _CORESIGHT_TMC_H 9 10 #include <linux/dma-mapping.h> 11 #include <linux/miscdevice.h> 12 #include <linux/refcount.h> 13 14 #define TMC_RSZ 0x004 15 #define TMC_STS 0x00c 16 #define TMC_RRD 0x010 17 #define TMC_RRP 0x014 18 #define TMC_RWP 0x018 19 #define TMC_TRG 0x01c 20 #define TMC_CTL 0x020 21 #define TMC_RWD 0x024 22 #define TMC_MODE 0x028 23 #define TMC_LBUFLEVEL 0x02c 24 #define TMC_CBUFLEVEL 0x030 25 #define TMC_BUFWM 0x034 26 #define TMC_RRPHI 0x038 27 #define TMC_RWPHI 0x03c 28 #define TMC_AXICTL 0x110 29 #define TMC_DBALO 0x118 30 #define TMC_DBAHI 0x11c 31 #define TMC_FFSR 0x300 32 #define TMC_FFCR 0x304 33 #define TMC_PSCR 0x308 34 #define TMC_ITMISCOP0 0xee0 35 #define TMC_ITTRFLIN 0xee8 36 #define TMC_ITATBDATA0 0xeec 37 #define TMC_ITATBCTR2 0xef0 38 #define TMC_ITATBCTR1 0xef4 39 #define TMC_ITATBCTR0 0xef8 40 41 /* register description */ 42 /* TMC_CTL - 0x020 */ 43 #define TMC_CTL_CAPT_EN BIT(0) 44 /* TMC_STS - 0x00C */ 45 #define TMC_STS_TMCREADY_BIT 2 46 #define TMC_STS_FULL BIT(0) 47 #define TMC_STS_TRIGGERED BIT(1) 48 /* 49 * TMC_AXICTL - 0x110 50 * 51 * TMC AXICTL format for SoC-400 52 * Bits [0-1] : ProtCtrlBit0-1 53 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE) 54 * Bit 6 : Reserved 55 * Bit 7 : ScatterGatherMode 56 * Bits [8-11] : WrBurstLen 57 * Bits [12-31] : Reserved. 58 * TMC AXICTL format for SoC-600, as above except: 59 * Bits [2-5] : AXI WCACHE 60 * Bits [16-19] : AXI RCACHE 61 * Bits [20-31] : Reserved 62 */ 63 #define TMC_AXICTL_CLEAR_MASK 0xfbf 64 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16) 65 66 #define TMC_AXICTL_PROT_CTL_B0 BIT(0) 67 #define TMC_AXICTL_PROT_CTL_B1 BIT(1) 68 #define TMC_AXICTL_SCT_GAT_MODE BIT(7) 69 #define TMC_AXICTL_WR_BURST_16 0xF00 70 /* Write-back Read and Write-allocate */ 71 #define TMC_AXICTL_AXCACHE_OS (0xf << 2) 72 #define TMC_AXICTL_ARCACHE_OS (0xf << 16) 73 74 /* TMC_FFCR - 0x304 */ 75 #define TMC_FFCR_FLUSHMAN_BIT 6 76 #define TMC_FFCR_EN_FMT BIT(0) 77 #define TMC_FFCR_EN_TI BIT(1) 78 #define TMC_FFCR_FON_FLIN BIT(4) 79 #define TMC_FFCR_FON_TRIG_EVT BIT(5) 80 #define TMC_FFCR_TRIGON_TRIGIN BIT(8) 81 #define TMC_FFCR_STOP_ON_FLUSH BIT(12) 82 83 84 #define TMC_DEVID_NOSCAT BIT(24) 85 86 #define TMC_DEVID_AXIAW_VALID BIT(16) 87 #define TMC_DEVID_AXIAW_SHIFT 17 88 #define TMC_DEVID_AXIAW_MASK 0x7f 89 90 enum tmc_config_type { 91 TMC_CONFIG_TYPE_ETB, 92 TMC_CONFIG_TYPE_ETR, 93 TMC_CONFIG_TYPE_ETF, 94 }; 95 96 enum tmc_mode { 97 TMC_MODE_CIRCULAR_BUFFER, 98 TMC_MODE_SOFTWARE_FIFO, 99 TMC_MODE_HARDWARE_FIFO, 100 }; 101 102 enum tmc_mem_intf_width { 103 TMC_MEM_INTF_WIDTH_32BITS = 1, 104 TMC_MEM_INTF_WIDTH_64BITS = 2, 105 TMC_MEM_INTF_WIDTH_128BITS = 4, 106 TMC_MEM_INTF_WIDTH_256BITS = 8, 107 }; 108 109 /* TMC ETR Capability bit definitions */ 110 #define TMC_ETR_SG (0x1U << 0) 111 /* ETR has separate read/write cache encodings */ 112 #define TMC_ETR_AXI_ARCACHE (0x1U << 1) 113 /* 114 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are 115 * retained when TMC leaves Disabled state, allowing us to continue 116 * the tracing from a point where we stopped. This also implies that 117 * the RRP/RWP/STS.Full should always be programmed to the correct 118 * value. Unfortunately this is not advertised by the hardware, 119 * so we have to rely on PID of the IP to detect the functionality. 120 */ 121 #define TMC_ETR_SAVE_RESTORE (0x1U << 2) 122 123 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */ 124 #define CORESIGHT_SOC_600_ETR_CAPS \ 125 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) 126 127 enum etr_mode { 128 ETR_MODE_FLAT, /* Uses contiguous flat buffer */ 129 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ 130 ETR_MODE_CATU, /* Use SG mechanism in CATU */ 131 }; 132 133 struct etr_buf_operations; 134 135 /** 136 * struct etr_buf - Details of the buffer used by ETR 137 * refcount ; Number of sources currently using this etr_buf. 138 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. 139 * @full : Trace data overflow 140 * @size : Size of the buffer. 141 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI} 142 * @offset : Offset of the trace data in the buffer for consumption. 143 * @len : Available trace data @buf (may round up to the beginning). 144 * @ops : ETR buffer operations for the mode. 145 * @private : Backend specific information for the buf 146 */ 147 struct etr_buf { 148 refcount_t refcount; 149 enum etr_mode mode; 150 bool full; 151 ssize_t size; 152 dma_addr_t hwaddr; 153 unsigned long offset; 154 s64 len; 155 const struct etr_buf_operations *ops; 156 void *private; 157 }; 158 159 /** 160 * struct tmc_drvdata - specifics associated to an TMC component 161 * @base: memory mapped base address for this component. 162 * @dev: the device entity associated to this component. 163 * @csdev: component vitals needed by the framework. 164 * @miscdev: specifics to handle "/dev/xyz.tmc" entry. 165 * @spinlock: only one at a time pls. 166 * @buf: Snapshot of the trace data for ETF/ETB. 167 * @etr_buf: details of buffer used in TMC-ETR 168 * @len: size of the available trace for ETF/ETB. 169 * @size: trace buffer size for this TMC (common for all modes). 170 * @mode: how this TMC is being used. 171 * @config_type: TMC variant, must be of type @tmc_config_type. 172 * @memwidth: width of the memory interface databus, in bytes. 173 * @trigger_cntr: amount of words to store after a trigger. 174 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the 175 * device configuration register (DEVID) 176 * @perf_data: PERF buffer for ETR. 177 * @sysfs_data: SYSFS buffer for ETR. 178 */ 179 struct tmc_drvdata { 180 void __iomem *base; 181 struct device *dev; 182 struct coresight_device *csdev; 183 struct miscdevice miscdev; 184 spinlock_t spinlock; 185 bool reading; 186 union { 187 char *buf; /* TMC ETB */ 188 struct etr_buf *etr_buf; /* TMC ETR */ 189 }; 190 u32 len; 191 u32 size; 192 u32 mode; 193 enum tmc_config_type config_type; 194 enum tmc_mem_intf_width memwidth; 195 u32 trigger_cntr; 196 u32 etr_caps; 197 struct etr_buf *sysfs_buf; 198 void *perf_data; 199 }; 200 201 struct etr_buf_operations { 202 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf, 203 int node, void **pages); 204 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp); 205 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len, 206 char **bufpp); 207 void (*free)(struct etr_buf *etr_buf); 208 }; 209 210 /** 211 * struct tmc_pages - Collection of pages used for SG. 212 * @nr_pages: Number of pages in the list. 213 * @daddrs: Array of DMA'able page address. 214 * @pages: Array pages for the buffer. 215 */ 216 struct tmc_pages { 217 int nr_pages; 218 dma_addr_t *daddrs; 219 struct page **pages; 220 }; 221 222 /* 223 * struct tmc_sg_table - Generic SG table for TMC 224 * @dev: Device for DMA allocations 225 * @table_vaddr: Contiguous Virtual address for PageTable 226 * @data_vaddr: Contiguous Virtual address for Data Buffer 227 * @table_daddr: DMA address of the PageTable base 228 * @node: Node for Page allocations 229 * @table_pages: List of pages & dma address for Table 230 * @data_pages: List of pages & dma address for Data 231 */ 232 struct tmc_sg_table { 233 struct device *dev; 234 void *table_vaddr; 235 void *data_vaddr; 236 dma_addr_t table_daddr; 237 int node; 238 struct tmc_pages table_pages; 239 struct tmc_pages data_pages; 240 }; 241 242 /* Generic functions */ 243 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 244 void tmc_flush_and_stop(struct tmc_drvdata *drvdata); 245 void tmc_enable_hw(struct tmc_drvdata *drvdata); 246 void tmc_disable_hw(struct tmc_drvdata *drvdata); 247 248 /* ETB/ETF functions */ 249 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); 250 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); 251 extern const struct coresight_ops tmc_etb_cs_ops; 252 extern const struct coresight_ops tmc_etf_cs_ops; 253 254 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata, 255 loff_t pos, size_t len, char **bufpp); 256 /* ETR functions */ 257 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); 258 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); 259 extern const struct coresight_ops tmc_etr_cs_ops; 260 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, 261 loff_t pos, size_t len, char **bufpp); 262 263 264 #define TMC_REG_PAIR(name, lo_off, hi_off) \ 265 static inline u64 \ 266 tmc_read_##name(struct tmc_drvdata *drvdata) \ 267 { \ 268 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ 269 } \ 270 static inline void \ 271 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ 272 { \ 273 coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ 274 } 275 276 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) 277 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) 278 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) 279 280 /* Initialise the caps from unadvertised static capabilities of the device */ 281 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) 282 { 283 WARN_ON(drvdata->etr_caps); 284 drvdata->etr_caps = dev_caps; 285 } 286 287 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap) 288 { 289 drvdata->etr_caps |= cap; 290 } 291 292 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap) 293 { 294 return !!(drvdata->etr_caps & cap); 295 } 296 297 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev, 298 int node, 299 int nr_tpages, 300 int nr_dpages, 301 void **pages); 302 void tmc_free_sg_table(struct tmc_sg_table *sg_table); 303 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table); 304 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table, 305 u64 offset, u64 size); 306 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, 307 u64 offset, size_t len, char **bufpp); 308 static inline unsigned long 309 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) 310 { 311 return sg_table->data_pages.nr_pages << PAGE_SHIFT; 312 } 313 314 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); 315 316 #endif 317