1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_TMC_H 8 #define _CORESIGHT_TMC_H 9 10 #include <linux/dma-mapping.h> 11 #include <linux/idr.h> 12 #include <linux/miscdevice.h> 13 #include <linux/mutex.h> 14 #include <linux/refcount.h> 15 16 #define TMC_RSZ 0x004 17 #define TMC_STS 0x00c 18 #define TMC_RRD 0x010 19 #define TMC_RRP 0x014 20 #define TMC_RWP 0x018 21 #define TMC_TRG 0x01c 22 #define TMC_CTL 0x020 23 #define TMC_RWD 0x024 24 #define TMC_MODE 0x028 25 #define TMC_LBUFLEVEL 0x02c 26 #define TMC_CBUFLEVEL 0x030 27 #define TMC_BUFWM 0x034 28 #define TMC_RRPHI 0x038 29 #define TMC_RWPHI 0x03c 30 #define TMC_AXICTL 0x110 31 #define TMC_DBALO 0x118 32 #define TMC_DBAHI 0x11c 33 #define TMC_FFSR 0x300 34 #define TMC_FFCR 0x304 35 #define TMC_PSCR 0x308 36 #define TMC_ITMISCOP0 0xee0 37 #define TMC_ITTRFLIN 0xee8 38 #define TMC_ITATBDATA0 0xeec 39 #define TMC_ITATBCTR2 0xef0 40 #define TMC_ITATBCTR1 0xef4 41 #define TMC_ITATBCTR0 0xef8 42 #define TMC_AUTHSTATUS 0xfb8 43 44 /* register description */ 45 /* TMC_CTL - 0x020 */ 46 #define TMC_CTL_CAPT_EN BIT(0) 47 /* TMC_STS - 0x00C */ 48 #define TMC_STS_TMCREADY_BIT 2 49 #define TMC_STS_FULL BIT(0) 50 #define TMC_STS_TRIGGERED BIT(1) 51 #define TMC_STS_MEMERR BIT(5) 52 /* 53 * TMC_AXICTL - 0x110 54 * 55 * TMC AXICTL format for SoC-400 56 * Bits [0-1] : ProtCtrlBit0-1 57 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE) 58 * Bit 6 : Reserved 59 * Bit 7 : ScatterGatherMode 60 * Bits [8-11] : WrBurstLen 61 * Bits [12-31] : Reserved. 62 * TMC AXICTL format for SoC-600, as above except: 63 * Bits [2-5] : AXI WCACHE 64 * Bits [16-19] : AXI RCACHE 65 * Bits [20-31] : Reserved 66 */ 67 #define TMC_AXICTL_CLEAR_MASK 0xfbf 68 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16) 69 70 #define TMC_AXICTL_PROT_CTL_B0 BIT(0) 71 #define TMC_AXICTL_PROT_CTL_B1 BIT(1) 72 #define TMC_AXICTL_SCT_GAT_MODE BIT(7) 73 #define TMC_AXICTL_WR_BURST_16 0xF00 74 /* Write-back Read and Write-allocate */ 75 #define TMC_AXICTL_AXCACHE_OS (0xf << 2) 76 #define TMC_AXICTL_ARCACHE_OS (0xf << 16) 77 78 /* TMC_FFCR - 0x304 */ 79 #define TMC_FFCR_FLUSHMAN_BIT 6 80 #define TMC_FFCR_EN_FMT BIT(0) 81 #define TMC_FFCR_EN_TI BIT(1) 82 #define TMC_FFCR_FON_FLIN BIT(4) 83 #define TMC_FFCR_FON_TRIG_EVT BIT(5) 84 #define TMC_FFCR_TRIGON_TRIGIN BIT(8) 85 #define TMC_FFCR_STOP_ON_FLUSH BIT(12) 86 87 88 #define TMC_DEVID_NOSCAT BIT(24) 89 90 #define TMC_DEVID_AXIAW_VALID BIT(16) 91 #define TMC_DEVID_AXIAW_SHIFT 17 92 #define TMC_DEVID_AXIAW_MASK 0x7f 93 94 #define TMC_AUTH_NSID_MASK GENMASK(1, 0) 95 96 enum tmc_config_type { 97 TMC_CONFIG_TYPE_ETB, 98 TMC_CONFIG_TYPE_ETR, 99 TMC_CONFIG_TYPE_ETF, 100 }; 101 102 enum tmc_mode { 103 TMC_MODE_CIRCULAR_BUFFER, 104 TMC_MODE_SOFTWARE_FIFO, 105 TMC_MODE_HARDWARE_FIFO, 106 }; 107 108 enum tmc_mem_intf_width { 109 TMC_MEM_INTF_WIDTH_32BITS = 1, 110 TMC_MEM_INTF_WIDTH_64BITS = 2, 111 TMC_MEM_INTF_WIDTH_128BITS = 4, 112 TMC_MEM_INTF_WIDTH_256BITS = 8, 113 }; 114 115 /* TMC ETR Capability bit definitions */ 116 #define TMC_ETR_SG (0x1U << 0) 117 /* ETR has separate read/write cache encodings */ 118 #define TMC_ETR_AXI_ARCACHE (0x1U << 1) 119 /* 120 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are 121 * retained when TMC leaves Disabled state, allowing us to continue 122 * the tracing from a point where we stopped. This also implies that 123 * the RRP/RWP/STS.Full should always be programmed to the correct 124 * value. Unfortunately this is not advertised by the hardware, 125 * so we have to rely on PID of the IP to detect the functionality. 126 */ 127 #define TMC_ETR_SAVE_RESTORE (0x1U << 2) 128 129 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */ 130 #define CORESIGHT_SOC_600_ETR_CAPS \ 131 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) 132 133 enum etr_mode { 134 ETR_MODE_FLAT, /* Uses contiguous flat buffer */ 135 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ 136 ETR_MODE_CATU, /* Use SG mechanism in CATU */ 137 }; 138 139 struct etr_buf_operations; 140 141 /** 142 * struct etr_buf - Details of the buffer used by ETR 143 * refcount ; Number of sources currently using this etr_buf. 144 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. 145 * @full : Trace data overflow 146 * @size : Size of the buffer. 147 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI} 148 * @offset : Offset of the trace data in the buffer for consumption. 149 * @len : Available trace data @buf (may round up to the beginning). 150 * @ops : ETR buffer operations for the mode. 151 * @private : Backend specific information for the buf 152 */ 153 struct etr_buf { 154 refcount_t refcount; 155 enum etr_mode mode; 156 bool full; 157 ssize_t size; 158 dma_addr_t hwaddr; 159 unsigned long offset; 160 s64 len; 161 const struct etr_buf_operations *ops; 162 void *private; 163 }; 164 165 /** 166 * struct tmc_drvdata - specifics associated to an TMC component 167 * @base: memory mapped base address for this component. 168 * @csdev: component vitals needed by the framework. 169 * @miscdev: specifics to handle "/dev/xyz.tmc" entry. 170 * @spinlock: only one at a time pls. 171 * @pid: Process ID of the process being monitored by the session 172 * that is using this component. 173 * @buf: Snapshot of the trace data for ETF/ETB. 174 * @etr_buf: details of buffer used in TMC-ETR 175 * @len: size of the available trace for ETF/ETB. 176 * @size: trace buffer size for this TMC (common for all modes). 177 * @mode: how this TMC is being used. 178 * @config_type: TMC variant, must be of type @tmc_config_type. 179 * @memwidth: width of the memory interface databus, in bytes. 180 * @trigger_cntr: amount of words to store after a trigger. 181 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the 182 * device configuration register (DEVID) 183 * @idr: Holds etr_bufs allocated for this ETR. 184 * @idr_mutex: Access serialisation for idr. 185 * @sysfs_buf: SYSFS buffer for ETR. 186 * @perf_buf: PERF buffer for ETR. 187 */ 188 struct tmc_drvdata { 189 void __iomem *base; 190 struct coresight_device *csdev; 191 struct miscdevice miscdev; 192 spinlock_t spinlock; 193 pid_t pid; 194 bool reading; 195 union { 196 char *buf; /* TMC ETB */ 197 struct etr_buf *etr_buf; /* TMC ETR */ 198 }; 199 u32 len; 200 u32 size; 201 u32 mode; 202 enum tmc_config_type config_type; 203 enum tmc_mem_intf_width memwidth; 204 u32 trigger_cntr; 205 u32 etr_caps; 206 struct idr idr; 207 struct mutex idr_mutex; 208 struct etr_buf *sysfs_buf; 209 struct etr_buf *perf_buf; 210 }; 211 212 struct etr_buf_operations { 213 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf, 214 int node, void **pages); 215 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp); 216 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len, 217 char **bufpp); 218 void (*free)(struct etr_buf *etr_buf); 219 }; 220 221 /** 222 * struct tmc_pages - Collection of pages used for SG. 223 * @nr_pages: Number of pages in the list. 224 * @daddrs: Array of DMA'able page address. 225 * @pages: Array pages for the buffer. 226 */ 227 struct tmc_pages { 228 int nr_pages; 229 dma_addr_t *daddrs; 230 struct page **pages; 231 }; 232 233 /* 234 * struct tmc_sg_table - Generic SG table for TMC 235 * @dev: Device for DMA allocations 236 * @table_vaddr: Contiguous Virtual address for PageTable 237 * @data_vaddr: Contiguous Virtual address for Data Buffer 238 * @table_daddr: DMA address of the PageTable base 239 * @node: Node for Page allocations 240 * @table_pages: List of pages & dma address for Table 241 * @data_pages: List of pages & dma address for Data 242 */ 243 struct tmc_sg_table { 244 struct device *dev; 245 void *table_vaddr; 246 void *data_vaddr; 247 dma_addr_t table_daddr; 248 int node; 249 struct tmc_pages table_pages; 250 struct tmc_pages data_pages; 251 }; 252 253 /* Generic functions */ 254 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 255 void tmc_flush_and_stop(struct tmc_drvdata *drvdata); 256 void tmc_enable_hw(struct tmc_drvdata *drvdata); 257 void tmc_disable_hw(struct tmc_drvdata *drvdata); 258 u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata); 259 260 /* ETB/ETF functions */ 261 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); 262 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); 263 extern const struct coresight_ops tmc_etb_cs_ops; 264 extern const struct coresight_ops tmc_etf_cs_ops; 265 266 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata, 267 loff_t pos, size_t len, char **bufpp); 268 /* ETR functions */ 269 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); 270 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); 271 extern const struct coresight_ops tmc_etr_cs_ops; 272 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, 273 loff_t pos, size_t len, char **bufpp); 274 275 276 #define TMC_REG_PAIR(name, lo_off, hi_off) \ 277 static inline u64 \ 278 tmc_read_##name(struct tmc_drvdata *drvdata) \ 279 { \ 280 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ 281 } \ 282 static inline void \ 283 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ 284 { \ 285 coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ 286 } 287 288 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) 289 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) 290 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) 291 292 /* Initialise the caps from unadvertised static capabilities of the device */ 293 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) 294 { 295 WARN_ON(drvdata->etr_caps); 296 drvdata->etr_caps = dev_caps; 297 } 298 299 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap) 300 { 301 drvdata->etr_caps |= cap; 302 } 303 304 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap) 305 { 306 return !!(drvdata->etr_caps & cap); 307 } 308 309 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev, 310 int node, 311 int nr_tpages, 312 int nr_dpages, 313 void **pages); 314 void tmc_free_sg_table(struct tmc_sg_table *sg_table); 315 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table); 316 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table, 317 u64 offset, u64 size); 318 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, 319 u64 offset, size_t len, char **bufpp); 320 static inline unsigned long 321 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) 322 { 323 return sg_table->data_pages.nr_pages << PAGE_SHIFT; 324 } 325 326 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); 327 328 #endif 329