1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(C) 2015 Linaro Limited. All rights reserved. 4 * Author: Mathieu Poirier <mathieu.poirier@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_TMC_H 8 #define _CORESIGHT_TMC_H 9 10 #include <linux/dma-mapping.h> 11 #include <linux/miscdevice.h> 12 13 #define TMC_RSZ 0x004 14 #define TMC_STS 0x00c 15 #define TMC_RRD 0x010 16 #define TMC_RRP 0x014 17 #define TMC_RWP 0x018 18 #define TMC_TRG 0x01c 19 #define TMC_CTL 0x020 20 #define TMC_RWD 0x024 21 #define TMC_MODE 0x028 22 #define TMC_LBUFLEVEL 0x02c 23 #define TMC_CBUFLEVEL 0x030 24 #define TMC_BUFWM 0x034 25 #define TMC_RRPHI 0x038 26 #define TMC_RWPHI 0x03c 27 #define TMC_AXICTL 0x110 28 #define TMC_DBALO 0x118 29 #define TMC_DBAHI 0x11c 30 #define TMC_FFSR 0x300 31 #define TMC_FFCR 0x304 32 #define TMC_PSCR 0x308 33 #define TMC_ITMISCOP0 0xee0 34 #define TMC_ITTRFLIN 0xee8 35 #define TMC_ITATBDATA0 0xeec 36 #define TMC_ITATBCTR2 0xef0 37 #define TMC_ITATBCTR1 0xef4 38 #define TMC_ITATBCTR0 0xef8 39 40 /* register description */ 41 /* TMC_CTL - 0x020 */ 42 #define TMC_CTL_CAPT_EN BIT(0) 43 /* TMC_STS - 0x00C */ 44 #define TMC_STS_TMCREADY_BIT 2 45 #define TMC_STS_FULL BIT(0) 46 #define TMC_STS_TRIGGERED BIT(1) 47 /* 48 * TMC_AXICTL - 0x110 49 * 50 * TMC AXICTL format for SoC-400 51 * Bits [0-1] : ProtCtrlBit0-1 52 * Bits [2-5] : CacheCtrlBits 0-3 (AXCACHE) 53 * Bit 6 : Reserved 54 * Bit 7 : ScatterGatherMode 55 * Bits [8-11] : WrBurstLen 56 * Bits [12-31] : Reserved. 57 * TMC AXICTL format for SoC-600, as above except: 58 * Bits [2-5] : AXI WCACHE 59 * Bits [16-19] : AXI RCACHE 60 * Bits [20-31] : Reserved 61 */ 62 #define TMC_AXICTL_CLEAR_MASK 0xfbf 63 #define TMC_AXICTL_ARCACHE_MASK (0xf << 16) 64 65 #define TMC_AXICTL_PROT_CTL_B0 BIT(0) 66 #define TMC_AXICTL_PROT_CTL_B1 BIT(1) 67 #define TMC_AXICTL_SCT_GAT_MODE BIT(7) 68 #define TMC_AXICTL_WR_BURST_16 0xF00 69 /* Write-back Read and Write-allocate */ 70 #define TMC_AXICTL_AXCACHE_OS (0xf << 2) 71 #define TMC_AXICTL_ARCACHE_OS (0xf << 16) 72 73 /* TMC_FFCR - 0x304 */ 74 #define TMC_FFCR_FLUSHMAN_BIT 6 75 #define TMC_FFCR_EN_FMT BIT(0) 76 #define TMC_FFCR_EN_TI BIT(1) 77 #define TMC_FFCR_FON_FLIN BIT(4) 78 #define TMC_FFCR_FON_TRIG_EVT BIT(5) 79 #define TMC_FFCR_TRIGON_TRIGIN BIT(8) 80 #define TMC_FFCR_STOP_ON_FLUSH BIT(12) 81 82 83 #define TMC_DEVID_NOSCAT BIT(24) 84 85 #define TMC_DEVID_AXIAW_VALID BIT(16) 86 #define TMC_DEVID_AXIAW_SHIFT 17 87 #define TMC_DEVID_AXIAW_MASK 0x7f 88 89 enum tmc_config_type { 90 TMC_CONFIG_TYPE_ETB, 91 TMC_CONFIG_TYPE_ETR, 92 TMC_CONFIG_TYPE_ETF, 93 }; 94 95 enum tmc_mode { 96 TMC_MODE_CIRCULAR_BUFFER, 97 TMC_MODE_SOFTWARE_FIFO, 98 TMC_MODE_HARDWARE_FIFO, 99 }; 100 101 enum tmc_mem_intf_width { 102 TMC_MEM_INTF_WIDTH_32BITS = 1, 103 TMC_MEM_INTF_WIDTH_64BITS = 2, 104 TMC_MEM_INTF_WIDTH_128BITS = 4, 105 TMC_MEM_INTF_WIDTH_256BITS = 8, 106 }; 107 108 /* TMC ETR Capability bit definitions */ 109 #define TMC_ETR_SG (0x1U << 0) 110 /* ETR has separate read/write cache encodings */ 111 #define TMC_ETR_AXI_ARCACHE (0x1U << 1) 112 /* 113 * TMC_ETR_SAVE_RESTORE - Values of RRP/RWP/STS.Full are 114 * retained when TMC leaves Disabled state, allowing us to continue 115 * the tracing from a point where we stopped. This also implies that 116 * the RRP/RWP/STS.Full should always be programmed to the correct 117 * value. Unfortunately this is not advertised by the hardware, 118 * so we have to rely on PID of the IP to detect the functionality. 119 */ 120 #define TMC_ETR_SAVE_RESTORE (0x1U << 2) 121 122 /* Coresight SoC-600 TMC-ETR unadvertised capabilities */ 123 #define CORESIGHT_SOC_600_ETR_CAPS \ 124 (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE) 125 126 enum etr_mode { 127 ETR_MODE_FLAT, /* Uses contiguous flat buffer */ 128 ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */ 129 ETR_MODE_CATU, /* Use SG mechanism in CATU */ 130 }; 131 132 struct etr_buf_operations; 133 134 /** 135 * struct etr_buf - Details of the buffer used by ETR 136 * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc. 137 * @full : Trace data overflow 138 * @size : Size of the buffer. 139 * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI} 140 * @offset : Offset of the trace data in the buffer for consumption. 141 * @len : Available trace data @buf (may round up to the beginning). 142 * @ops : ETR buffer operations for the mode. 143 * @private : Backend specific information for the buf 144 */ 145 struct etr_buf { 146 enum etr_mode mode; 147 bool full; 148 ssize_t size; 149 dma_addr_t hwaddr; 150 unsigned long offset; 151 s64 len; 152 const struct etr_buf_operations *ops; 153 void *private; 154 }; 155 156 /** 157 * struct tmc_drvdata - specifics associated to an TMC component 158 * @base: memory mapped base address for this component. 159 * @dev: the device entity associated to this component. 160 * @csdev: component vitals needed by the framework. 161 * @miscdev: specifics to handle "/dev/xyz.tmc" entry. 162 * @spinlock: only one at a time pls. 163 * @buf: Snapshot of the trace data for ETF/ETB. 164 * @etr_buf: details of buffer used in TMC-ETR 165 * @len: size of the available trace for ETF/ETB. 166 * @size: trace buffer size for this TMC (common for all modes). 167 * @mode: how this TMC is being used. 168 * @config_type: TMC variant, must be of type @tmc_config_type. 169 * @memwidth: width of the memory interface databus, in bytes. 170 * @trigger_cntr: amount of words to store after a trigger. 171 * @etr_caps: Bitmask of capabilities of the TMC ETR, inferred from the 172 * device configuration register (DEVID) 173 */ 174 struct tmc_drvdata { 175 void __iomem *base; 176 struct device *dev; 177 struct coresight_device *csdev; 178 struct miscdevice miscdev; 179 spinlock_t spinlock; 180 bool reading; 181 union { 182 char *buf; /* TMC ETB */ 183 struct etr_buf *etr_buf; /* TMC ETR */ 184 }; 185 u32 len; 186 u32 size; 187 u32 mode; 188 enum tmc_config_type config_type; 189 enum tmc_mem_intf_width memwidth; 190 u32 trigger_cntr; 191 u32 etr_caps; 192 }; 193 194 struct etr_buf_operations { 195 int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf, 196 int node, void **pages); 197 void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp); 198 ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len, 199 char **bufpp); 200 void (*free)(struct etr_buf *etr_buf); 201 }; 202 203 /** 204 * struct tmc_pages - Collection of pages used for SG. 205 * @nr_pages: Number of pages in the list. 206 * @daddrs: Array of DMA'able page address. 207 * @pages: Array pages for the buffer. 208 */ 209 struct tmc_pages { 210 int nr_pages; 211 dma_addr_t *daddrs; 212 struct page **pages; 213 }; 214 215 /* 216 * struct tmc_sg_table - Generic SG table for TMC 217 * @dev: Device for DMA allocations 218 * @table_vaddr: Contiguous Virtual address for PageTable 219 * @data_vaddr: Contiguous Virtual address for Data Buffer 220 * @table_daddr: DMA address of the PageTable base 221 * @node: Node for Page allocations 222 * @table_pages: List of pages & dma address for Table 223 * @data_pages: List of pages & dma address for Data 224 */ 225 struct tmc_sg_table { 226 struct device *dev; 227 void *table_vaddr; 228 void *data_vaddr; 229 dma_addr_t table_daddr; 230 int node; 231 struct tmc_pages table_pages; 232 struct tmc_pages data_pages; 233 }; 234 235 /* Generic functions */ 236 void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); 237 void tmc_flush_and_stop(struct tmc_drvdata *drvdata); 238 void tmc_enable_hw(struct tmc_drvdata *drvdata); 239 void tmc_disable_hw(struct tmc_drvdata *drvdata); 240 241 /* ETB/ETF functions */ 242 int tmc_read_prepare_etb(struct tmc_drvdata *drvdata); 243 int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata); 244 extern const struct coresight_ops tmc_etb_cs_ops; 245 extern const struct coresight_ops tmc_etf_cs_ops; 246 247 ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *drvdata, 248 loff_t pos, size_t len, char **bufpp); 249 /* ETR functions */ 250 int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); 251 int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); 252 extern const struct coresight_ops tmc_etr_cs_ops; 253 ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, 254 loff_t pos, size_t len, char **bufpp); 255 256 257 #define TMC_REG_PAIR(name, lo_off, hi_off) \ 258 static inline u64 \ 259 tmc_read_##name(struct tmc_drvdata *drvdata) \ 260 { \ 261 return coresight_read_reg_pair(drvdata->base, lo_off, hi_off); \ 262 } \ 263 static inline void \ 264 tmc_write_##name(struct tmc_drvdata *drvdata, u64 val) \ 265 { \ 266 coresight_write_reg_pair(drvdata->base, val, lo_off, hi_off); \ 267 } 268 269 TMC_REG_PAIR(rrp, TMC_RRP, TMC_RRPHI) 270 TMC_REG_PAIR(rwp, TMC_RWP, TMC_RWPHI) 271 TMC_REG_PAIR(dba, TMC_DBALO, TMC_DBAHI) 272 273 /* Initialise the caps from unadvertised static capabilities of the device */ 274 static inline void tmc_etr_init_caps(struct tmc_drvdata *drvdata, u32 dev_caps) 275 { 276 WARN_ON(drvdata->etr_caps); 277 drvdata->etr_caps = dev_caps; 278 } 279 280 static inline void tmc_etr_set_cap(struct tmc_drvdata *drvdata, u32 cap) 281 { 282 drvdata->etr_caps |= cap; 283 } 284 285 static inline bool tmc_etr_has_cap(struct tmc_drvdata *drvdata, u32 cap) 286 { 287 return !!(drvdata->etr_caps & cap); 288 } 289 290 struct tmc_sg_table *tmc_alloc_sg_table(struct device *dev, 291 int node, 292 int nr_tpages, 293 int nr_dpages, 294 void **pages); 295 void tmc_free_sg_table(struct tmc_sg_table *sg_table); 296 void tmc_sg_table_sync_table(struct tmc_sg_table *sg_table); 297 void tmc_sg_table_sync_data_range(struct tmc_sg_table *table, 298 u64 offset, u64 size); 299 ssize_t tmc_sg_table_get_data(struct tmc_sg_table *sg_table, 300 u64 offset, size_t len, char **bufpp); 301 static inline unsigned long 302 tmc_sg_table_buf_size(struct tmc_sg_table *sg_table) 303 { 304 return sg_table->data_pages.nr_pages << PAGE_SHIFT; 305 } 306 307 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata); 308 309 #endif 310