1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 2 * 3 * Description: CoreSight System Trace Macrocell driver 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * Initial implementation by Pratik Patel 15 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org> 16 * 17 * Serious refactoring, code cleanup and upgrading to the Coresight upstream 18 * framework by Mathieu Poirier 19 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org> 20 * 21 * Guaranteed timing and support for various packet type coming from the 22 * generic STM API by Chunyan Zhang 23 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org> 24 */ 25 #include <asm/local.h> 26 #include <linux/amba/bus.h> 27 #include <linux/bitmap.h> 28 #include <linux/clk.h> 29 #include <linux/coresight.h> 30 #include <linux/coresight-stm.h> 31 #include <linux/err.h> 32 #include <linux/kernel.h> 33 #include <linux/moduleparam.h> 34 #include <linux/of_address.h> 35 #include <linux/perf_event.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/stm.h> 38 39 #include "coresight-priv.h" 40 41 #define STMDMASTARTR 0xc04 42 #define STMDMASTOPR 0xc08 43 #define STMDMASTATR 0xc0c 44 #define STMDMACTLR 0xc10 45 #define STMDMAIDR 0xcfc 46 #define STMHEER 0xd00 47 #define STMHETER 0xd20 48 #define STMHEBSR 0xd60 49 #define STMHEMCR 0xd64 50 #define STMHEMASTR 0xdf4 51 #define STMHEFEAT1R 0xdf8 52 #define STMHEIDR 0xdfc 53 #define STMSPER 0xe00 54 #define STMSPTER 0xe20 55 #define STMPRIVMASKR 0xe40 56 #define STMSPSCR 0xe60 57 #define STMSPMSCR 0xe64 58 #define STMSPOVERRIDER 0xe68 59 #define STMSPMOVERRIDER 0xe6c 60 #define STMSPTRIGCSR 0xe70 61 #define STMTCSR 0xe80 62 #define STMTSSTIMR 0xe84 63 #define STMTSFREQR 0xe8c 64 #define STMSYNCR 0xe90 65 #define STMAUXCR 0xe94 66 #define STMSPFEAT1R 0xea0 67 #define STMSPFEAT2R 0xea4 68 #define STMSPFEAT3R 0xea8 69 #define STMITTRIGGER 0xee8 70 #define STMITATBDATA0 0xeec 71 #define STMITATBCTR2 0xef0 72 #define STMITATBID 0xef4 73 #define STMITATBCTR0 0xef8 74 75 #define STM_32_CHANNEL 32 76 #define BYTES_PER_CHANNEL 256 77 #define STM_TRACE_BUF_SIZE 4096 78 #define STM_SW_MASTER_END 127 79 80 /* Register bit definition */ 81 #define STMTCSR_BUSY_BIT 23 82 /* Reserve the first 10 channels for kernel usage */ 83 #define STM_CHANNEL_OFFSET 0 84 85 enum stm_pkt_type { 86 STM_PKT_TYPE_DATA = 0x98, 87 STM_PKT_TYPE_FLAG = 0xE8, 88 STM_PKT_TYPE_TRIG = 0xF8, 89 }; 90 91 #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \ 92 (ch * BYTES_PER_CHANNEL)) 93 #define stm_channel_off(type, opts) (type & ~opts) 94 95 static int boot_nr_channel; 96 97 /* 98 * Not really modular but using module_param is the easiest way to 99 * remain consistent with existing use cases for now. 100 */ 101 module_param_named( 102 boot_nr_channel, boot_nr_channel, int, S_IRUGO 103 ); 104 105 /** 106 * struct channel_space - central management entity for extended ports 107 * @base: memory mapped base address where channels start. 108 * @phys: physical base address of channel region. 109 * @guaraneed: is the channel delivery guaranteed. 110 */ 111 struct channel_space { 112 void __iomem *base; 113 phys_addr_t phys; 114 unsigned long *guaranteed; 115 }; 116 117 /** 118 * struct stm_drvdata - specifics associated to an STM component 119 * @base: memory mapped base address for this component. 120 * @dev: the device entity associated to this component. 121 * @atclk: optional clock for the core parts of the STM. 122 * @csdev: component vitals needed by the framework. 123 * @spinlock: only one at a time pls. 124 * @chs: the channels accociated to this STM. 125 * @stm: structure associated to the generic STM interface. 126 * @mode: this tracer's mode, i.e sysFS, or disabled. 127 * @traceid: value of the current ID for this component. 128 * @write_bytes: Maximus bytes this STM can write at a time. 129 * @stmsper: settings for register STMSPER. 130 * @stmspscr: settings for register STMSPSCR. 131 * @numsp: the total number of stimulus port support by this STM. 132 * @stmheer: settings for register STMHEER. 133 * @stmheter: settings for register STMHETER. 134 * @stmhebsr: settings for register STMHEBSR. 135 */ 136 struct stm_drvdata { 137 void __iomem *base; 138 struct device *dev; 139 struct clk *atclk; 140 struct coresight_device *csdev; 141 spinlock_t spinlock; 142 struct channel_space chs; 143 struct stm_data stm; 144 local_t mode; 145 u8 traceid; 146 u32 write_bytes; 147 u32 stmsper; 148 u32 stmspscr; 149 u32 numsp; 150 u32 stmheer; 151 u32 stmheter; 152 u32 stmhebsr; 153 }; 154 155 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata) 156 { 157 CS_UNLOCK(drvdata->base); 158 159 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR); 160 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER); 161 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER); 162 writel_relaxed(0x01 | /* Enable HW event tracing */ 163 0x04, /* Error detection on event tracing */ 164 drvdata->base + STMHEMCR); 165 166 CS_LOCK(drvdata->base); 167 } 168 169 static void stm_port_enable_hw(struct stm_drvdata *drvdata) 170 { 171 CS_UNLOCK(drvdata->base); 172 /* ATB trigger enable on direct writes to TRIG locations */ 173 writel_relaxed(0x10, 174 drvdata->base + STMSPTRIGCSR); 175 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 176 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 177 178 CS_LOCK(drvdata->base); 179 } 180 181 static void stm_enable_hw(struct stm_drvdata *drvdata) 182 { 183 if (drvdata->stmheer) 184 stm_hwevent_enable_hw(drvdata); 185 186 stm_port_enable_hw(drvdata); 187 188 CS_UNLOCK(drvdata->base); 189 190 /* 4096 byte between synchronisation packets */ 191 writel_relaxed(0xFFF, drvdata->base + STMSYNCR); 192 writel_relaxed((drvdata->traceid << 16 | /* trace id */ 193 0x02 | /* timestamp enable */ 194 0x01), /* global STM enable */ 195 drvdata->base + STMTCSR); 196 197 CS_LOCK(drvdata->base); 198 } 199 200 static int stm_enable(struct coresight_device *csdev, 201 struct perf_event *event, u32 mode) 202 { 203 u32 val; 204 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 205 206 if (mode != CS_MODE_SYSFS) 207 return -EINVAL; 208 209 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); 210 211 /* Someone is already using the tracer */ 212 if (val) 213 return -EBUSY; 214 215 pm_runtime_get_sync(drvdata->dev); 216 217 spin_lock(&drvdata->spinlock); 218 stm_enable_hw(drvdata); 219 spin_unlock(&drvdata->spinlock); 220 221 dev_info(drvdata->dev, "STM tracing enabled\n"); 222 return 0; 223 } 224 225 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata) 226 { 227 CS_UNLOCK(drvdata->base); 228 229 writel_relaxed(0x0, drvdata->base + STMHEMCR); 230 writel_relaxed(0x0, drvdata->base + STMHEER); 231 writel_relaxed(0x0, drvdata->base + STMHETER); 232 233 CS_LOCK(drvdata->base); 234 } 235 236 static void stm_port_disable_hw(struct stm_drvdata *drvdata) 237 { 238 CS_UNLOCK(drvdata->base); 239 240 writel_relaxed(0x0, drvdata->base + STMSPER); 241 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR); 242 243 CS_LOCK(drvdata->base); 244 } 245 246 static void stm_disable_hw(struct stm_drvdata *drvdata) 247 { 248 u32 val; 249 250 CS_UNLOCK(drvdata->base); 251 252 val = readl_relaxed(drvdata->base + STMTCSR); 253 val &= ~0x1; /* clear global STM enable [0] */ 254 writel_relaxed(val, drvdata->base + STMTCSR); 255 256 CS_LOCK(drvdata->base); 257 258 stm_port_disable_hw(drvdata); 259 if (drvdata->stmheer) 260 stm_hwevent_disable_hw(drvdata); 261 } 262 263 static void stm_disable(struct coresight_device *csdev, 264 struct perf_event *event) 265 { 266 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 267 268 /* 269 * For as long as the tracer isn't disabled another entity can't 270 * change its status. As such we can read the status here without 271 * fearing it will change under us. 272 */ 273 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { 274 spin_lock(&drvdata->spinlock); 275 stm_disable_hw(drvdata); 276 spin_unlock(&drvdata->spinlock); 277 278 /* Wait until the engine has completely stopped */ 279 coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0); 280 281 pm_runtime_put(drvdata->dev); 282 283 local_set(&drvdata->mode, CS_MODE_DISABLED); 284 dev_info(drvdata->dev, "STM tracing disabled\n"); 285 } 286 } 287 288 static int stm_trace_id(struct coresight_device *csdev) 289 { 290 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 291 292 return drvdata->traceid; 293 } 294 295 static const struct coresight_ops_source stm_source_ops = { 296 .trace_id = stm_trace_id, 297 .enable = stm_enable, 298 .disable = stm_disable, 299 }; 300 301 static const struct coresight_ops stm_cs_ops = { 302 .source_ops = &stm_source_ops, 303 }; 304 305 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes) 306 { 307 return ((unsigned long)addr & (write_bytes - 1)); 308 } 309 310 static void stm_send(void __iomem *addr, const void *data, 311 u32 size, u8 write_bytes) 312 { 313 u8 paload[8]; 314 315 if (stm_addr_unaligned(data, write_bytes)) { 316 memcpy(paload, data, size); 317 data = paload; 318 } 319 320 /* now we are 64bit/32bit aligned */ 321 switch (size) { 322 #ifdef CONFIG_64BIT 323 case 8: 324 writeq_relaxed(*(u64 *)data, addr); 325 break; 326 #endif 327 case 4: 328 writel_relaxed(*(u32 *)data, addr); 329 break; 330 case 2: 331 writew_relaxed(*(u16 *)data, addr); 332 break; 333 case 1: 334 writeb_relaxed(*(u8 *)data, addr); 335 break; 336 default: 337 break; 338 } 339 } 340 341 static int stm_generic_link(struct stm_data *stm_data, 342 unsigned int master, unsigned int channel) 343 { 344 struct stm_drvdata *drvdata = container_of(stm_data, 345 struct stm_drvdata, stm); 346 if (!drvdata || !drvdata->csdev) 347 return -EINVAL; 348 349 return coresight_enable(drvdata->csdev); 350 } 351 352 static void stm_generic_unlink(struct stm_data *stm_data, 353 unsigned int master, unsigned int channel) 354 { 355 struct stm_drvdata *drvdata = container_of(stm_data, 356 struct stm_drvdata, stm); 357 if (!drvdata || !drvdata->csdev) 358 return; 359 360 coresight_disable(drvdata->csdev); 361 } 362 363 static phys_addr_t 364 stm_mmio_addr(struct stm_data *stm_data, unsigned int master, 365 unsigned int channel, unsigned int nr_chans) 366 { 367 struct stm_drvdata *drvdata = container_of(stm_data, 368 struct stm_drvdata, stm); 369 phys_addr_t addr; 370 371 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL; 372 373 if (offset_in_page(addr) || 374 offset_in_page(nr_chans * BYTES_PER_CHANNEL)) 375 return 0; 376 377 return addr; 378 } 379 380 static long stm_generic_set_options(struct stm_data *stm_data, 381 unsigned int master, 382 unsigned int channel, 383 unsigned int nr_chans, 384 unsigned long options) 385 { 386 struct stm_drvdata *drvdata = container_of(stm_data, 387 struct stm_drvdata, stm); 388 if (!(drvdata && local_read(&drvdata->mode))) 389 return -EINVAL; 390 391 if (channel >= drvdata->numsp) 392 return -EINVAL; 393 394 switch (options) { 395 case STM_OPTION_GUARANTEED: 396 set_bit(channel, drvdata->chs.guaranteed); 397 break; 398 399 case STM_OPTION_INVARIANT: 400 clear_bit(channel, drvdata->chs.guaranteed); 401 break; 402 403 default: 404 return -EINVAL; 405 } 406 407 return 0; 408 } 409 410 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, 411 unsigned int master, 412 unsigned int channel, 413 unsigned int packet, 414 unsigned int flags, 415 unsigned int size, 416 const unsigned char *payload) 417 { 418 void __iomem *ch_addr; 419 struct stm_drvdata *drvdata = container_of(stm_data, 420 struct stm_drvdata, stm); 421 422 if (!(drvdata && local_read(&drvdata->mode))) 423 return -EACCES; 424 425 if (channel >= drvdata->numsp) 426 return -EINVAL; 427 428 ch_addr = stm_channel_addr(drvdata, channel); 429 430 flags = (flags == STP_PACKET_TIMESTAMPED) ? STM_FLAG_TIMESTAMPED : 0; 431 flags |= test_bit(channel, drvdata->chs.guaranteed) ? 432 STM_FLAG_GUARANTEED : 0; 433 434 if (size > drvdata->write_bytes) 435 size = drvdata->write_bytes; 436 else 437 size = rounddown_pow_of_two(size); 438 439 switch (packet) { 440 case STP_PACKET_FLAG: 441 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, flags); 442 443 /* 444 * The generic STM core sets a size of '0' on flag packets. 445 * As such send a flag packet of size '1' and tell the 446 * core we did so. 447 */ 448 stm_send(ch_addr, payload, 1, drvdata->write_bytes); 449 size = 1; 450 break; 451 452 case STP_PACKET_DATA: 453 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, flags); 454 stm_send(ch_addr, payload, size, 455 drvdata->write_bytes); 456 break; 457 458 default: 459 return -ENOTSUPP; 460 } 461 462 return size; 463 } 464 465 static ssize_t hwevent_enable_show(struct device *dev, 466 struct device_attribute *attr, char *buf) 467 { 468 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 469 unsigned long val = drvdata->stmheer; 470 471 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 472 } 473 474 static ssize_t hwevent_enable_store(struct device *dev, 475 struct device_attribute *attr, 476 const char *buf, size_t size) 477 { 478 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 479 unsigned long val; 480 int ret = 0; 481 482 ret = kstrtoul(buf, 16, &val); 483 if (ret) 484 return -EINVAL; 485 486 drvdata->stmheer = val; 487 /* HW event enable and trigger go hand in hand */ 488 drvdata->stmheter = val; 489 490 return size; 491 } 492 static DEVICE_ATTR_RW(hwevent_enable); 493 494 static ssize_t hwevent_select_show(struct device *dev, 495 struct device_attribute *attr, char *buf) 496 { 497 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 498 unsigned long val = drvdata->stmhebsr; 499 500 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 501 } 502 503 static ssize_t hwevent_select_store(struct device *dev, 504 struct device_attribute *attr, 505 const char *buf, size_t size) 506 { 507 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 508 unsigned long val; 509 int ret = 0; 510 511 ret = kstrtoul(buf, 16, &val); 512 if (ret) 513 return -EINVAL; 514 515 drvdata->stmhebsr = val; 516 517 return size; 518 } 519 static DEVICE_ATTR_RW(hwevent_select); 520 521 static ssize_t port_select_show(struct device *dev, 522 struct device_attribute *attr, char *buf) 523 { 524 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 525 unsigned long val; 526 527 if (!local_read(&drvdata->mode)) { 528 val = drvdata->stmspscr; 529 } else { 530 spin_lock(&drvdata->spinlock); 531 val = readl_relaxed(drvdata->base + STMSPSCR); 532 spin_unlock(&drvdata->spinlock); 533 } 534 535 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 536 } 537 538 static ssize_t port_select_store(struct device *dev, 539 struct device_attribute *attr, 540 const char *buf, size_t size) 541 { 542 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 543 unsigned long val, stmsper; 544 int ret = 0; 545 546 ret = kstrtoul(buf, 16, &val); 547 if (ret) 548 return ret; 549 550 spin_lock(&drvdata->spinlock); 551 drvdata->stmspscr = val; 552 553 if (local_read(&drvdata->mode)) { 554 CS_UNLOCK(drvdata->base); 555 /* Process as per ARM's TRM recommendation */ 556 stmsper = readl_relaxed(drvdata->base + STMSPER); 557 writel_relaxed(0x0, drvdata->base + STMSPER); 558 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 559 writel_relaxed(stmsper, drvdata->base + STMSPER); 560 CS_LOCK(drvdata->base); 561 } 562 spin_unlock(&drvdata->spinlock); 563 564 return size; 565 } 566 static DEVICE_ATTR_RW(port_select); 567 568 static ssize_t port_enable_show(struct device *dev, 569 struct device_attribute *attr, char *buf) 570 { 571 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 572 unsigned long val; 573 574 if (!local_read(&drvdata->mode)) { 575 val = drvdata->stmsper; 576 } else { 577 spin_lock(&drvdata->spinlock); 578 val = readl_relaxed(drvdata->base + STMSPER); 579 spin_unlock(&drvdata->spinlock); 580 } 581 582 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 583 } 584 585 static ssize_t port_enable_store(struct device *dev, 586 struct device_attribute *attr, 587 const char *buf, size_t size) 588 { 589 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 590 unsigned long val; 591 int ret = 0; 592 593 ret = kstrtoul(buf, 16, &val); 594 if (ret) 595 return ret; 596 597 spin_lock(&drvdata->spinlock); 598 drvdata->stmsper = val; 599 600 if (local_read(&drvdata->mode)) { 601 CS_UNLOCK(drvdata->base); 602 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 603 CS_LOCK(drvdata->base); 604 } 605 spin_unlock(&drvdata->spinlock); 606 607 return size; 608 } 609 static DEVICE_ATTR_RW(port_enable); 610 611 static ssize_t traceid_show(struct device *dev, 612 struct device_attribute *attr, char *buf) 613 { 614 unsigned long val; 615 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 616 617 val = drvdata->traceid; 618 return sprintf(buf, "%#lx\n", val); 619 } 620 621 static ssize_t traceid_store(struct device *dev, 622 struct device_attribute *attr, 623 const char *buf, size_t size) 624 { 625 int ret; 626 unsigned long val; 627 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 628 629 ret = kstrtoul(buf, 16, &val); 630 if (ret) 631 return ret; 632 633 /* traceid field is 7bit wide on STM32 */ 634 drvdata->traceid = val & 0x7f; 635 return size; 636 } 637 static DEVICE_ATTR_RW(traceid); 638 639 #define coresight_stm_reg(name, offset) \ 640 coresight_simple_reg32(struct stm_drvdata, name, offset) 641 642 coresight_stm_reg(tcsr, STMTCSR); 643 coresight_stm_reg(tsfreqr, STMTSFREQR); 644 coresight_stm_reg(syncr, STMSYNCR); 645 coresight_stm_reg(sper, STMSPER); 646 coresight_stm_reg(spter, STMSPTER); 647 coresight_stm_reg(privmaskr, STMPRIVMASKR); 648 coresight_stm_reg(spscr, STMSPSCR); 649 coresight_stm_reg(spmscr, STMSPMSCR); 650 coresight_stm_reg(spfeat1r, STMSPFEAT1R); 651 coresight_stm_reg(spfeat2r, STMSPFEAT2R); 652 coresight_stm_reg(spfeat3r, STMSPFEAT3R); 653 coresight_stm_reg(devid, CORESIGHT_DEVID); 654 655 static struct attribute *coresight_stm_attrs[] = { 656 &dev_attr_hwevent_enable.attr, 657 &dev_attr_hwevent_select.attr, 658 &dev_attr_port_enable.attr, 659 &dev_attr_port_select.attr, 660 &dev_attr_traceid.attr, 661 NULL, 662 }; 663 664 static struct attribute *coresight_stm_mgmt_attrs[] = { 665 &dev_attr_tcsr.attr, 666 &dev_attr_tsfreqr.attr, 667 &dev_attr_syncr.attr, 668 &dev_attr_sper.attr, 669 &dev_attr_spter.attr, 670 &dev_attr_privmaskr.attr, 671 &dev_attr_spscr.attr, 672 &dev_attr_spmscr.attr, 673 &dev_attr_spfeat1r.attr, 674 &dev_attr_spfeat2r.attr, 675 &dev_attr_spfeat3r.attr, 676 &dev_attr_devid.attr, 677 NULL, 678 }; 679 680 static const struct attribute_group coresight_stm_group = { 681 .attrs = coresight_stm_attrs, 682 }; 683 684 static const struct attribute_group coresight_stm_mgmt_group = { 685 .attrs = coresight_stm_mgmt_attrs, 686 .name = "mgmt", 687 }; 688 689 static const struct attribute_group *coresight_stm_groups[] = { 690 &coresight_stm_group, 691 &coresight_stm_mgmt_group, 692 NULL, 693 }; 694 695 static int stm_get_resource_byname(struct device_node *np, 696 char *ch_base, struct resource *res) 697 { 698 const char *name = NULL; 699 int index = 0, found = 0; 700 701 while (!of_property_read_string_index(np, "reg-names", index, &name)) { 702 if (strcmp(ch_base, name)) { 703 index++; 704 continue; 705 } 706 707 /* We have a match and @index is where it's at */ 708 found = 1; 709 break; 710 } 711 712 if (!found) 713 return -EINVAL; 714 715 return of_address_to_resource(np, index, res); 716 } 717 718 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata) 719 { 720 u32 stmspfeat2r; 721 722 if (!IS_ENABLED(CONFIG_64BIT)) 723 return 4; 724 725 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R); 726 727 /* 728 * bit[15:12] represents the fundamental data size 729 * 0 - 32-bit data 730 * 1 - 64-bit data 731 */ 732 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4; 733 } 734 735 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata) 736 { 737 u32 numsp; 738 739 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID); 740 /* 741 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0, 742 * 32 stimulus ports are supported. 743 */ 744 numsp &= 0x1ffff; 745 if (!numsp) 746 numsp = STM_32_CHANNEL; 747 return numsp; 748 } 749 750 static void stm_init_default_data(struct stm_drvdata *drvdata) 751 { 752 /* Don't use port selection */ 753 drvdata->stmspscr = 0x0; 754 /* 755 * Enable all channel regardless of their number. When port 756 * selection isn't used (see above) STMSPER applies to all 757 * 32 channel group available, hence setting all 32 bits to 1 758 */ 759 drvdata->stmsper = ~0x0; 760 761 /* 762 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and 763 * anything equal to or higher than 0x70 is reserved. Since 0x00 is 764 * also reserved the STM trace ID needs to be higher than 0x00 and 765 * lowner than 0x10. 766 */ 767 drvdata->traceid = 0x1; 768 769 /* Set invariant transaction timing on all channels */ 770 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); 771 } 772 773 static void stm_init_generic_data(struct stm_drvdata *drvdata) 774 { 775 drvdata->stm.name = dev_name(drvdata->dev); 776 777 /* 778 * MasterIDs are assigned at HW design phase. As such the core is 779 * using a single master for interaction with this device. 780 */ 781 drvdata->stm.sw_start = 1; 782 drvdata->stm.sw_end = 1; 783 drvdata->stm.hw_override = true; 784 drvdata->stm.sw_nchannels = drvdata->numsp; 785 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL; 786 drvdata->stm.packet = stm_generic_packet; 787 drvdata->stm.mmio_addr = stm_mmio_addr; 788 drvdata->stm.link = stm_generic_link; 789 drvdata->stm.unlink = stm_generic_unlink; 790 drvdata->stm.set_options = stm_generic_set_options; 791 } 792 793 static int stm_probe(struct amba_device *adev, const struct amba_id *id) 794 { 795 int ret; 796 void __iomem *base; 797 unsigned long *guaranteed; 798 struct device *dev = &adev->dev; 799 struct coresight_platform_data *pdata = NULL; 800 struct stm_drvdata *drvdata; 801 struct resource *res = &adev->res; 802 struct resource ch_res; 803 size_t res_size, bitmap_size; 804 struct coresight_desc desc = { 0 }; 805 struct device_node *np = adev->dev.of_node; 806 807 if (np) { 808 pdata = of_get_coresight_platform_data(dev, np); 809 if (IS_ERR(pdata)) 810 return PTR_ERR(pdata); 811 adev->dev.platform_data = pdata; 812 } 813 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 814 if (!drvdata) 815 return -ENOMEM; 816 817 drvdata->dev = &adev->dev; 818 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 819 if (!IS_ERR(drvdata->atclk)) { 820 ret = clk_prepare_enable(drvdata->atclk); 821 if (ret) 822 return ret; 823 } 824 dev_set_drvdata(dev, drvdata); 825 826 base = devm_ioremap_resource(dev, res); 827 if (IS_ERR(base)) 828 return PTR_ERR(base); 829 drvdata->base = base; 830 831 ret = stm_get_resource_byname(np, "stm-stimulus-base", &ch_res); 832 if (ret) 833 return ret; 834 drvdata->chs.phys = ch_res.start; 835 836 base = devm_ioremap_resource(dev, &ch_res); 837 if (IS_ERR(base)) 838 return PTR_ERR(base); 839 drvdata->chs.base = base; 840 841 drvdata->write_bytes = stm_fundamental_data_size(drvdata); 842 843 if (boot_nr_channel) { 844 drvdata->numsp = boot_nr_channel; 845 res_size = min((resource_size_t)(boot_nr_channel * 846 BYTES_PER_CHANNEL), resource_size(res)); 847 } else { 848 drvdata->numsp = stm_num_stimulus_port(drvdata); 849 res_size = min((resource_size_t)(drvdata->numsp * 850 BYTES_PER_CHANNEL), resource_size(res)); 851 } 852 bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long); 853 854 guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); 855 if (!guaranteed) 856 return -ENOMEM; 857 drvdata->chs.guaranteed = guaranteed; 858 859 spin_lock_init(&drvdata->spinlock); 860 861 stm_init_default_data(drvdata); 862 stm_init_generic_data(drvdata); 863 864 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) { 865 dev_info(dev, 866 "stm_register_device failed, probing deffered\n"); 867 return -EPROBE_DEFER; 868 } 869 870 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 871 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE; 872 desc.ops = &stm_cs_ops; 873 desc.pdata = pdata; 874 desc.dev = dev; 875 desc.groups = coresight_stm_groups; 876 drvdata->csdev = coresight_register(&desc); 877 if (IS_ERR(drvdata->csdev)) { 878 ret = PTR_ERR(drvdata->csdev); 879 goto stm_unregister; 880 } 881 882 pm_runtime_put(&adev->dev); 883 884 dev_info(dev, "%s initialized\n", (char *)id->data); 885 return 0; 886 887 stm_unregister: 888 stm_unregister_device(&drvdata->stm); 889 return ret; 890 } 891 892 #ifdef CONFIG_PM 893 static int stm_runtime_suspend(struct device *dev) 894 { 895 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 896 897 if (drvdata && !IS_ERR(drvdata->atclk)) 898 clk_disable_unprepare(drvdata->atclk); 899 900 return 0; 901 } 902 903 static int stm_runtime_resume(struct device *dev) 904 { 905 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 906 907 if (drvdata && !IS_ERR(drvdata->atclk)) 908 clk_prepare_enable(drvdata->atclk); 909 910 return 0; 911 } 912 #endif 913 914 static const struct dev_pm_ops stm_dev_pm_ops = { 915 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL) 916 }; 917 918 static const struct amba_id stm_ids[] = { 919 { 920 .id = 0x000bb962, 921 .mask = 0x000fffff, 922 .data = "STM32", 923 }, 924 { 925 .id = 0x000bb963, 926 .mask = 0x000fffff, 927 .data = "STM500", 928 }, 929 { 0, 0}, 930 }; 931 932 static struct amba_driver stm_driver = { 933 .drv = { 934 .name = "coresight-stm", 935 .owner = THIS_MODULE, 936 .pm = &stm_dev_pm_ops, 937 .suppress_bind_attrs = true, 938 }, 939 .probe = stm_probe, 940 .id_table = stm_ids, 941 }; 942 943 builtin_amba_driver(stm_driver); 944