1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight System Trace Macrocell driver 6 * 7 * Initial implementation by Pratik Patel 8 * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org> 9 * 10 * Serious refactoring, code cleanup and upgrading to the Coresight upstream 11 * framework by Mathieu Poirier 12 * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org> 13 * 14 * Guaranteed timing and support for various packet type coming from the 15 * generic STM API by Chunyan Zhang 16 * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org> 17 */ 18 #include <asm/local.h> 19 #include <linux/amba/bus.h> 20 #include <linux/bitmap.h> 21 #include <linux/clk.h> 22 #include <linux/coresight.h> 23 #include <linux/coresight-stm.h> 24 #include <linux/err.h> 25 #include <linux/kernel.h> 26 #include <linux/moduleparam.h> 27 #include <linux/of_address.h> 28 #include <linux/perf_event.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/stm.h> 31 32 #include "coresight-priv.h" 33 34 #define STMDMASTARTR 0xc04 35 #define STMDMASTOPR 0xc08 36 #define STMDMASTATR 0xc0c 37 #define STMDMACTLR 0xc10 38 #define STMDMAIDR 0xcfc 39 #define STMHEER 0xd00 40 #define STMHETER 0xd20 41 #define STMHEBSR 0xd60 42 #define STMHEMCR 0xd64 43 #define STMHEMASTR 0xdf4 44 #define STMHEFEAT1R 0xdf8 45 #define STMHEIDR 0xdfc 46 #define STMSPER 0xe00 47 #define STMSPTER 0xe20 48 #define STMPRIVMASKR 0xe40 49 #define STMSPSCR 0xe60 50 #define STMSPMSCR 0xe64 51 #define STMSPOVERRIDER 0xe68 52 #define STMSPMOVERRIDER 0xe6c 53 #define STMSPTRIGCSR 0xe70 54 #define STMTCSR 0xe80 55 #define STMTSSTIMR 0xe84 56 #define STMTSFREQR 0xe8c 57 #define STMSYNCR 0xe90 58 #define STMAUXCR 0xe94 59 #define STMSPFEAT1R 0xea0 60 #define STMSPFEAT2R 0xea4 61 #define STMSPFEAT3R 0xea8 62 #define STMITTRIGGER 0xee8 63 #define STMITATBDATA0 0xeec 64 #define STMITATBCTR2 0xef0 65 #define STMITATBID 0xef4 66 #define STMITATBCTR0 0xef8 67 68 #define STM_32_CHANNEL 32 69 #define BYTES_PER_CHANNEL 256 70 #define STM_TRACE_BUF_SIZE 4096 71 #define STM_SW_MASTER_END 127 72 73 /* Register bit definition */ 74 #define STMTCSR_BUSY_BIT 23 75 /* Reserve the first 10 channels for kernel usage */ 76 #define STM_CHANNEL_OFFSET 0 77 78 enum stm_pkt_type { 79 STM_PKT_TYPE_DATA = 0x98, 80 STM_PKT_TYPE_FLAG = 0xE8, 81 STM_PKT_TYPE_TRIG = 0xF8, 82 }; 83 84 #define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \ 85 (ch * BYTES_PER_CHANNEL)) 86 #define stm_channel_off(type, opts) (type & ~opts) 87 88 static int boot_nr_channel; 89 90 /* 91 * Not really modular but using module_param is the easiest way to 92 * remain consistent with existing use cases for now. 93 */ 94 module_param_named( 95 boot_nr_channel, boot_nr_channel, int, S_IRUGO 96 ); 97 98 /** 99 * struct channel_space - central management entity for extended ports 100 * @base: memory mapped base address where channels start. 101 * @phys: physical base address of channel region. 102 * @guaraneed: is the channel delivery guaranteed. 103 */ 104 struct channel_space { 105 void __iomem *base; 106 phys_addr_t phys; 107 unsigned long *guaranteed; 108 }; 109 110 /** 111 * struct stm_drvdata - specifics associated to an STM component 112 * @base: memory mapped base address for this component. 113 * @dev: the device entity associated to this component. 114 * @atclk: optional clock for the core parts of the STM. 115 * @csdev: component vitals needed by the framework. 116 * @spinlock: only one at a time pls. 117 * @chs: the channels accociated to this STM. 118 * @stm: structure associated to the generic STM interface. 119 * @mode: this tracer's mode, i.e sysFS, or disabled. 120 * @traceid: value of the current ID for this component. 121 * @write_bytes: Maximus bytes this STM can write at a time. 122 * @stmsper: settings for register STMSPER. 123 * @stmspscr: settings for register STMSPSCR. 124 * @numsp: the total number of stimulus port support by this STM. 125 * @stmheer: settings for register STMHEER. 126 * @stmheter: settings for register STMHETER. 127 * @stmhebsr: settings for register STMHEBSR. 128 */ 129 struct stm_drvdata { 130 void __iomem *base; 131 struct device *dev; 132 struct clk *atclk; 133 struct coresight_device *csdev; 134 spinlock_t spinlock; 135 struct channel_space chs; 136 struct stm_data stm; 137 local_t mode; 138 u8 traceid; 139 u32 write_bytes; 140 u32 stmsper; 141 u32 stmspscr; 142 u32 numsp; 143 u32 stmheer; 144 u32 stmheter; 145 u32 stmhebsr; 146 }; 147 148 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata) 149 { 150 CS_UNLOCK(drvdata->base); 151 152 writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR); 153 writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER); 154 writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER); 155 writel_relaxed(0x01 | /* Enable HW event tracing */ 156 0x04, /* Error detection on event tracing */ 157 drvdata->base + STMHEMCR); 158 159 CS_LOCK(drvdata->base); 160 } 161 162 static void stm_port_enable_hw(struct stm_drvdata *drvdata) 163 { 164 CS_UNLOCK(drvdata->base); 165 /* ATB trigger enable on direct writes to TRIG locations */ 166 writel_relaxed(0x10, 167 drvdata->base + STMSPTRIGCSR); 168 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 169 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 170 171 CS_LOCK(drvdata->base); 172 } 173 174 static void stm_enable_hw(struct stm_drvdata *drvdata) 175 { 176 if (drvdata->stmheer) 177 stm_hwevent_enable_hw(drvdata); 178 179 stm_port_enable_hw(drvdata); 180 181 CS_UNLOCK(drvdata->base); 182 183 /* 4096 byte between synchronisation packets */ 184 writel_relaxed(0xFFF, drvdata->base + STMSYNCR); 185 writel_relaxed((drvdata->traceid << 16 | /* trace id */ 186 0x02 | /* timestamp enable */ 187 0x01), /* global STM enable */ 188 drvdata->base + STMTCSR); 189 190 CS_LOCK(drvdata->base); 191 } 192 193 static int stm_enable(struct coresight_device *csdev, 194 struct perf_event *event, u32 mode) 195 { 196 u32 val; 197 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 198 199 if (mode != CS_MODE_SYSFS) 200 return -EINVAL; 201 202 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); 203 204 /* Someone is already using the tracer */ 205 if (val) 206 return -EBUSY; 207 208 pm_runtime_get_sync(drvdata->dev); 209 210 spin_lock(&drvdata->spinlock); 211 stm_enable_hw(drvdata); 212 spin_unlock(&drvdata->spinlock); 213 214 dev_info(drvdata->dev, "STM tracing enabled\n"); 215 return 0; 216 } 217 218 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata) 219 { 220 CS_UNLOCK(drvdata->base); 221 222 writel_relaxed(0x0, drvdata->base + STMHEMCR); 223 writel_relaxed(0x0, drvdata->base + STMHEER); 224 writel_relaxed(0x0, drvdata->base + STMHETER); 225 226 CS_LOCK(drvdata->base); 227 } 228 229 static void stm_port_disable_hw(struct stm_drvdata *drvdata) 230 { 231 CS_UNLOCK(drvdata->base); 232 233 writel_relaxed(0x0, drvdata->base + STMSPER); 234 writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR); 235 236 CS_LOCK(drvdata->base); 237 } 238 239 static void stm_disable_hw(struct stm_drvdata *drvdata) 240 { 241 u32 val; 242 243 CS_UNLOCK(drvdata->base); 244 245 val = readl_relaxed(drvdata->base + STMTCSR); 246 val &= ~0x1; /* clear global STM enable [0] */ 247 writel_relaxed(val, drvdata->base + STMTCSR); 248 249 CS_LOCK(drvdata->base); 250 251 stm_port_disable_hw(drvdata); 252 if (drvdata->stmheer) 253 stm_hwevent_disable_hw(drvdata); 254 } 255 256 static void stm_disable(struct coresight_device *csdev, 257 struct perf_event *event) 258 { 259 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 260 261 /* 262 * For as long as the tracer isn't disabled another entity can't 263 * change its status. As such we can read the status here without 264 * fearing it will change under us. 265 */ 266 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { 267 spin_lock(&drvdata->spinlock); 268 stm_disable_hw(drvdata); 269 spin_unlock(&drvdata->spinlock); 270 271 /* Wait until the engine has completely stopped */ 272 coresight_timeout(drvdata->base, STMTCSR, STMTCSR_BUSY_BIT, 0); 273 274 pm_runtime_put(drvdata->dev); 275 276 local_set(&drvdata->mode, CS_MODE_DISABLED); 277 dev_info(drvdata->dev, "STM tracing disabled\n"); 278 } 279 } 280 281 static int stm_trace_id(struct coresight_device *csdev) 282 { 283 struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 284 285 return drvdata->traceid; 286 } 287 288 static const struct coresight_ops_source stm_source_ops = { 289 .trace_id = stm_trace_id, 290 .enable = stm_enable, 291 .disable = stm_disable, 292 }; 293 294 static const struct coresight_ops stm_cs_ops = { 295 .source_ops = &stm_source_ops, 296 }; 297 298 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes) 299 { 300 return ((unsigned long)addr & (write_bytes - 1)); 301 } 302 303 static void stm_send(void __iomem *addr, const void *data, 304 u32 size, u8 write_bytes) 305 { 306 u8 paload[8]; 307 308 if (stm_addr_unaligned(data, write_bytes)) { 309 memcpy(paload, data, size); 310 data = paload; 311 } 312 313 /* now we are 64bit/32bit aligned */ 314 switch (size) { 315 #ifdef CONFIG_64BIT 316 case 8: 317 writeq_relaxed(*(u64 *)data, addr); 318 break; 319 #endif 320 case 4: 321 writel_relaxed(*(u32 *)data, addr); 322 break; 323 case 2: 324 writew_relaxed(*(u16 *)data, addr); 325 break; 326 case 1: 327 writeb_relaxed(*(u8 *)data, addr); 328 break; 329 default: 330 break; 331 } 332 } 333 334 static int stm_generic_link(struct stm_data *stm_data, 335 unsigned int master, unsigned int channel) 336 { 337 struct stm_drvdata *drvdata = container_of(stm_data, 338 struct stm_drvdata, stm); 339 if (!drvdata || !drvdata->csdev) 340 return -EINVAL; 341 342 return coresight_enable(drvdata->csdev); 343 } 344 345 static void stm_generic_unlink(struct stm_data *stm_data, 346 unsigned int master, unsigned int channel) 347 { 348 struct stm_drvdata *drvdata = container_of(stm_data, 349 struct stm_drvdata, stm); 350 if (!drvdata || !drvdata->csdev) 351 return; 352 353 coresight_disable(drvdata->csdev); 354 } 355 356 static phys_addr_t 357 stm_mmio_addr(struct stm_data *stm_data, unsigned int master, 358 unsigned int channel, unsigned int nr_chans) 359 { 360 struct stm_drvdata *drvdata = container_of(stm_data, 361 struct stm_drvdata, stm); 362 phys_addr_t addr; 363 364 addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL; 365 366 if (offset_in_page(addr) || 367 offset_in_page(nr_chans * BYTES_PER_CHANNEL)) 368 return 0; 369 370 return addr; 371 } 372 373 static long stm_generic_set_options(struct stm_data *stm_data, 374 unsigned int master, 375 unsigned int channel, 376 unsigned int nr_chans, 377 unsigned long options) 378 { 379 struct stm_drvdata *drvdata = container_of(stm_data, 380 struct stm_drvdata, stm); 381 if (!(drvdata && local_read(&drvdata->mode))) 382 return -EINVAL; 383 384 if (channel >= drvdata->numsp) 385 return -EINVAL; 386 387 switch (options) { 388 case STM_OPTION_GUARANTEED: 389 set_bit(channel, drvdata->chs.guaranteed); 390 break; 391 392 case STM_OPTION_INVARIANT: 393 clear_bit(channel, drvdata->chs.guaranteed); 394 break; 395 396 default: 397 return -EINVAL; 398 } 399 400 return 0; 401 } 402 403 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data, 404 unsigned int master, 405 unsigned int channel, 406 unsigned int packet, 407 unsigned int flags, 408 unsigned int size, 409 const unsigned char *payload) 410 { 411 void __iomem *ch_addr; 412 struct stm_drvdata *drvdata = container_of(stm_data, 413 struct stm_drvdata, stm); 414 415 if (!(drvdata && local_read(&drvdata->mode))) 416 return -EACCES; 417 418 if (channel >= drvdata->numsp) 419 return -EINVAL; 420 421 ch_addr = stm_channel_addr(drvdata, channel); 422 423 flags = (flags == STP_PACKET_TIMESTAMPED) ? STM_FLAG_TIMESTAMPED : 0; 424 flags |= test_bit(channel, drvdata->chs.guaranteed) ? 425 STM_FLAG_GUARANTEED : 0; 426 427 if (size > drvdata->write_bytes) 428 size = drvdata->write_bytes; 429 else 430 size = rounddown_pow_of_two(size); 431 432 switch (packet) { 433 case STP_PACKET_FLAG: 434 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, flags); 435 436 /* 437 * The generic STM core sets a size of '0' on flag packets. 438 * As such send a flag packet of size '1' and tell the 439 * core we did so. 440 */ 441 stm_send(ch_addr, payload, 1, drvdata->write_bytes); 442 size = 1; 443 break; 444 445 case STP_PACKET_DATA: 446 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, flags); 447 stm_send(ch_addr, payload, size, 448 drvdata->write_bytes); 449 break; 450 451 default: 452 return -ENOTSUPP; 453 } 454 455 return size; 456 } 457 458 static ssize_t hwevent_enable_show(struct device *dev, 459 struct device_attribute *attr, char *buf) 460 { 461 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 462 unsigned long val = drvdata->stmheer; 463 464 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 465 } 466 467 static ssize_t hwevent_enable_store(struct device *dev, 468 struct device_attribute *attr, 469 const char *buf, size_t size) 470 { 471 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 472 unsigned long val; 473 int ret = 0; 474 475 ret = kstrtoul(buf, 16, &val); 476 if (ret) 477 return -EINVAL; 478 479 drvdata->stmheer = val; 480 /* HW event enable and trigger go hand in hand */ 481 drvdata->stmheter = val; 482 483 return size; 484 } 485 static DEVICE_ATTR_RW(hwevent_enable); 486 487 static ssize_t hwevent_select_show(struct device *dev, 488 struct device_attribute *attr, char *buf) 489 { 490 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 491 unsigned long val = drvdata->stmhebsr; 492 493 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 494 } 495 496 static ssize_t hwevent_select_store(struct device *dev, 497 struct device_attribute *attr, 498 const char *buf, size_t size) 499 { 500 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 501 unsigned long val; 502 int ret = 0; 503 504 ret = kstrtoul(buf, 16, &val); 505 if (ret) 506 return -EINVAL; 507 508 drvdata->stmhebsr = val; 509 510 return size; 511 } 512 static DEVICE_ATTR_RW(hwevent_select); 513 514 static ssize_t port_select_show(struct device *dev, 515 struct device_attribute *attr, char *buf) 516 { 517 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 518 unsigned long val; 519 520 if (!local_read(&drvdata->mode)) { 521 val = drvdata->stmspscr; 522 } else { 523 spin_lock(&drvdata->spinlock); 524 val = readl_relaxed(drvdata->base + STMSPSCR); 525 spin_unlock(&drvdata->spinlock); 526 } 527 528 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 529 } 530 531 static ssize_t port_select_store(struct device *dev, 532 struct device_attribute *attr, 533 const char *buf, size_t size) 534 { 535 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 536 unsigned long val, stmsper; 537 int ret = 0; 538 539 ret = kstrtoul(buf, 16, &val); 540 if (ret) 541 return ret; 542 543 spin_lock(&drvdata->spinlock); 544 drvdata->stmspscr = val; 545 546 if (local_read(&drvdata->mode)) { 547 CS_UNLOCK(drvdata->base); 548 /* Process as per ARM's TRM recommendation */ 549 stmsper = readl_relaxed(drvdata->base + STMSPER); 550 writel_relaxed(0x0, drvdata->base + STMSPER); 551 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR); 552 writel_relaxed(stmsper, drvdata->base + STMSPER); 553 CS_LOCK(drvdata->base); 554 } 555 spin_unlock(&drvdata->spinlock); 556 557 return size; 558 } 559 static DEVICE_ATTR_RW(port_select); 560 561 static ssize_t port_enable_show(struct device *dev, 562 struct device_attribute *attr, char *buf) 563 { 564 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 565 unsigned long val; 566 567 if (!local_read(&drvdata->mode)) { 568 val = drvdata->stmsper; 569 } else { 570 spin_lock(&drvdata->spinlock); 571 val = readl_relaxed(drvdata->base + STMSPER); 572 spin_unlock(&drvdata->spinlock); 573 } 574 575 return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); 576 } 577 578 static ssize_t port_enable_store(struct device *dev, 579 struct device_attribute *attr, 580 const char *buf, size_t size) 581 { 582 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 583 unsigned long val; 584 int ret = 0; 585 586 ret = kstrtoul(buf, 16, &val); 587 if (ret) 588 return ret; 589 590 spin_lock(&drvdata->spinlock); 591 drvdata->stmsper = val; 592 593 if (local_read(&drvdata->mode)) { 594 CS_UNLOCK(drvdata->base); 595 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER); 596 CS_LOCK(drvdata->base); 597 } 598 spin_unlock(&drvdata->spinlock); 599 600 return size; 601 } 602 static DEVICE_ATTR_RW(port_enable); 603 604 static ssize_t traceid_show(struct device *dev, 605 struct device_attribute *attr, char *buf) 606 { 607 unsigned long val; 608 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 609 610 val = drvdata->traceid; 611 return sprintf(buf, "%#lx\n", val); 612 } 613 614 static ssize_t traceid_store(struct device *dev, 615 struct device_attribute *attr, 616 const char *buf, size_t size) 617 { 618 int ret; 619 unsigned long val; 620 struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); 621 622 ret = kstrtoul(buf, 16, &val); 623 if (ret) 624 return ret; 625 626 /* traceid field is 7bit wide on STM32 */ 627 drvdata->traceid = val & 0x7f; 628 return size; 629 } 630 static DEVICE_ATTR_RW(traceid); 631 632 #define coresight_stm_reg(name, offset) \ 633 coresight_simple_reg32(struct stm_drvdata, name, offset) 634 635 coresight_stm_reg(tcsr, STMTCSR); 636 coresight_stm_reg(tsfreqr, STMTSFREQR); 637 coresight_stm_reg(syncr, STMSYNCR); 638 coresight_stm_reg(sper, STMSPER); 639 coresight_stm_reg(spter, STMSPTER); 640 coresight_stm_reg(privmaskr, STMPRIVMASKR); 641 coresight_stm_reg(spscr, STMSPSCR); 642 coresight_stm_reg(spmscr, STMSPMSCR); 643 coresight_stm_reg(spfeat1r, STMSPFEAT1R); 644 coresight_stm_reg(spfeat2r, STMSPFEAT2R); 645 coresight_stm_reg(spfeat3r, STMSPFEAT3R); 646 coresight_stm_reg(devid, CORESIGHT_DEVID); 647 648 static struct attribute *coresight_stm_attrs[] = { 649 &dev_attr_hwevent_enable.attr, 650 &dev_attr_hwevent_select.attr, 651 &dev_attr_port_enable.attr, 652 &dev_attr_port_select.attr, 653 &dev_attr_traceid.attr, 654 NULL, 655 }; 656 657 static struct attribute *coresight_stm_mgmt_attrs[] = { 658 &dev_attr_tcsr.attr, 659 &dev_attr_tsfreqr.attr, 660 &dev_attr_syncr.attr, 661 &dev_attr_sper.attr, 662 &dev_attr_spter.attr, 663 &dev_attr_privmaskr.attr, 664 &dev_attr_spscr.attr, 665 &dev_attr_spmscr.attr, 666 &dev_attr_spfeat1r.attr, 667 &dev_attr_spfeat2r.attr, 668 &dev_attr_spfeat3r.attr, 669 &dev_attr_devid.attr, 670 NULL, 671 }; 672 673 static const struct attribute_group coresight_stm_group = { 674 .attrs = coresight_stm_attrs, 675 }; 676 677 static const struct attribute_group coresight_stm_mgmt_group = { 678 .attrs = coresight_stm_mgmt_attrs, 679 .name = "mgmt", 680 }; 681 682 static const struct attribute_group *coresight_stm_groups[] = { 683 &coresight_stm_group, 684 &coresight_stm_mgmt_group, 685 NULL, 686 }; 687 688 static int stm_get_resource_byname(struct device_node *np, 689 char *ch_base, struct resource *res) 690 { 691 const char *name = NULL; 692 int index = 0, found = 0; 693 694 while (!of_property_read_string_index(np, "reg-names", index, &name)) { 695 if (strcmp(ch_base, name)) { 696 index++; 697 continue; 698 } 699 700 /* We have a match and @index is where it's at */ 701 found = 1; 702 break; 703 } 704 705 if (!found) 706 return -EINVAL; 707 708 return of_address_to_resource(np, index, res); 709 } 710 711 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata) 712 { 713 u32 stmspfeat2r; 714 715 if (!IS_ENABLED(CONFIG_64BIT)) 716 return 4; 717 718 stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R); 719 720 /* 721 * bit[15:12] represents the fundamental data size 722 * 0 - 32-bit data 723 * 1 - 64-bit data 724 */ 725 return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4; 726 } 727 728 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata) 729 { 730 u32 numsp; 731 732 numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID); 733 /* 734 * NUMPS in STMDEVID is 17 bit long and if equal to 0x0, 735 * 32 stimulus ports are supported. 736 */ 737 numsp &= 0x1ffff; 738 if (!numsp) 739 numsp = STM_32_CHANNEL; 740 return numsp; 741 } 742 743 static void stm_init_default_data(struct stm_drvdata *drvdata) 744 { 745 /* Don't use port selection */ 746 drvdata->stmspscr = 0x0; 747 /* 748 * Enable all channel regardless of their number. When port 749 * selection isn't used (see above) STMSPER applies to all 750 * 32 channel group available, hence setting all 32 bits to 1 751 */ 752 drvdata->stmsper = ~0x0; 753 754 /* 755 * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and 756 * anything equal to or higher than 0x70 is reserved. Since 0x00 is 757 * also reserved the STM trace ID needs to be higher than 0x00 and 758 * lowner than 0x10. 759 */ 760 drvdata->traceid = 0x1; 761 762 /* Set invariant transaction timing on all channels */ 763 bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp); 764 } 765 766 static void stm_init_generic_data(struct stm_drvdata *drvdata) 767 { 768 drvdata->stm.name = dev_name(drvdata->dev); 769 770 /* 771 * MasterIDs are assigned at HW design phase. As such the core is 772 * using a single master for interaction with this device. 773 */ 774 drvdata->stm.sw_start = 1; 775 drvdata->stm.sw_end = 1; 776 drvdata->stm.hw_override = true; 777 drvdata->stm.sw_nchannels = drvdata->numsp; 778 drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL; 779 drvdata->stm.packet = stm_generic_packet; 780 drvdata->stm.mmio_addr = stm_mmio_addr; 781 drvdata->stm.link = stm_generic_link; 782 drvdata->stm.unlink = stm_generic_unlink; 783 drvdata->stm.set_options = stm_generic_set_options; 784 } 785 786 static int stm_probe(struct amba_device *adev, const struct amba_id *id) 787 { 788 int ret; 789 void __iomem *base; 790 unsigned long *guaranteed; 791 struct device *dev = &adev->dev; 792 struct coresight_platform_data *pdata = NULL; 793 struct stm_drvdata *drvdata; 794 struct resource *res = &adev->res; 795 struct resource ch_res; 796 size_t res_size, bitmap_size; 797 struct coresight_desc desc = { 0 }; 798 struct device_node *np = adev->dev.of_node; 799 800 if (np) { 801 pdata = of_get_coresight_platform_data(dev, np); 802 if (IS_ERR(pdata)) 803 return PTR_ERR(pdata); 804 adev->dev.platform_data = pdata; 805 } 806 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 807 if (!drvdata) 808 return -ENOMEM; 809 810 drvdata->dev = &adev->dev; 811 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 812 if (!IS_ERR(drvdata->atclk)) { 813 ret = clk_prepare_enable(drvdata->atclk); 814 if (ret) 815 return ret; 816 } 817 dev_set_drvdata(dev, drvdata); 818 819 base = devm_ioremap_resource(dev, res); 820 if (IS_ERR(base)) 821 return PTR_ERR(base); 822 drvdata->base = base; 823 824 ret = stm_get_resource_byname(np, "stm-stimulus-base", &ch_res); 825 if (ret) 826 return ret; 827 drvdata->chs.phys = ch_res.start; 828 829 base = devm_ioremap_resource(dev, &ch_res); 830 if (IS_ERR(base)) 831 return PTR_ERR(base); 832 drvdata->chs.base = base; 833 834 drvdata->write_bytes = stm_fundamental_data_size(drvdata); 835 836 if (boot_nr_channel) { 837 drvdata->numsp = boot_nr_channel; 838 res_size = min((resource_size_t)(boot_nr_channel * 839 BYTES_PER_CHANNEL), resource_size(res)); 840 } else { 841 drvdata->numsp = stm_num_stimulus_port(drvdata); 842 res_size = min((resource_size_t)(drvdata->numsp * 843 BYTES_PER_CHANNEL), resource_size(res)); 844 } 845 bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long); 846 847 guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); 848 if (!guaranteed) 849 return -ENOMEM; 850 drvdata->chs.guaranteed = guaranteed; 851 852 spin_lock_init(&drvdata->spinlock); 853 854 stm_init_default_data(drvdata); 855 stm_init_generic_data(drvdata); 856 857 if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) { 858 dev_info(dev, 859 "stm_register_device failed, probing deffered\n"); 860 return -EPROBE_DEFER; 861 } 862 863 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 864 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE; 865 desc.ops = &stm_cs_ops; 866 desc.pdata = pdata; 867 desc.dev = dev; 868 desc.groups = coresight_stm_groups; 869 drvdata->csdev = coresight_register(&desc); 870 if (IS_ERR(drvdata->csdev)) { 871 ret = PTR_ERR(drvdata->csdev); 872 goto stm_unregister; 873 } 874 875 pm_runtime_put(&adev->dev); 876 877 dev_info(dev, "%s initialized\n", (char *)id->data); 878 return 0; 879 880 stm_unregister: 881 stm_unregister_device(&drvdata->stm); 882 return ret; 883 } 884 885 #ifdef CONFIG_PM 886 static int stm_runtime_suspend(struct device *dev) 887 { 888 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 889 890 if (drvdata && !IS_ERR(drvdata->atclk)) 891 clk_disable_unprepare(drvdata->atclk); 892 893 return 0; 894 } 895 896 static int stm_runtime_resume(struct device *dev) 897 { 898 struct stm_drvdata *drvdata = dev_get_drvdata(dev); 899 900 if (drvdata && !IS_ERR(drvdata->atclk)) 901 clk_prepare_enable(drvdata->atclk); 902 903 return 0; 904 } 905 #endif 906 907 static const struct dev_pm_ops stm_dev_pm_ops = { 908 SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL) 909 }; 910 911 static const struct amba_id stm_ids[] = { 912 { 913 .id = 0x000bb962, 914 .mask = 0x000fffff, 915 .data = "STM32", 916 }, 917 { 918 .id = 0x000bb963, 919 .mask = 0x000fffff, 920 .data = "STM500", 921 }, 922 { 0, 0}, 923 }; 924 925 static struct amba_driver stm_driver = { 926 .drv = { 927 .name = "coresight-stm", 928 .owner = THIS_MODULE, 929 .pm = &stm_dev_pm_ops, 930 .suppress_bind_attrs = true, 931 }, 932 .probe = stm_probe, 933 .id_table = stm_ids, 934 }; 935 936 builtin_amba_driver(stm_driver); 937