1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_PRIV_H 7 #define _CORESIGHT_PRIV_H 8 9 #include <linux/amba/bus.h> 10 #include <linux/bitops.h> 11 #include <linux/io.h> 12 #include <linux/coresight.h> 13 #include <linux/pm_runtime.h> 14 15 /* 16 * Coresight management registers (0xf00-0xfcc) 17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0 18 * Trace registers in PFTv1.1 19 */ 20 #define CORESIGHT_ITCTRL 0xf00 21 #define CORESIGHT_CLAIMSET 0xfa0 22 #define CORESIGHT_CLAIMCLR 0xfa4 23 #define CORESIGHT_LAR 0xfb0 24 #define CORESIGHT_LSR 0xfb4 25 #define CORESIGHT_DEVARCH 0xfbc 26 #define CORESIGHT_AUTHSTATUS 0xfb8 27 #define CORESIGHT_DEVID 0xfc8 28 #define CORESIGHT_DEVTYPE 0xfcc 29 30 31 /* 32 * Coresight device CLAIM protocol. 33 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore. 34 */ 35 #define CORESIGHT_CLAIM_SELF_HOSTED BIT(1) 36 37 #define TIMEOUT_US 100 38 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) 39 40 #define ETM_MODE_EXCL_KERN BIT(30) 41 #define ETM_MODE_EXCL_USER BIT(31) 42 struct cs_pair_attribute { 43 struct device_attribute attr; 44 u32 lo_off; 45 u32 hi_off; 46 }; 47 48 struct cs_off_attribute { 49 struct device_attribute attr; 50 u32 off; 51 }; 52 53 extern ssize_t coresight_simple_show32(struct device *_dev, 54 struct device_attribute *attr, char *buf); 55 extern ssize_t coresight_simple_show_pair(struct device *_dev, 56 struct device_attribute *attr, char *buf); 57 58 #define coresight_simple_reg32(name, offset) \ 59 (&((struct cs_off_attribute[]) { \ 60 { \ 61 __ATTR(name, 0444, coresight_simple_show32, NULL), \ 62 offset \ 63 } \ 64 })[0].attr.attr) 65 66 #define coresight_simple_reg64(name, lo_off, hi_off) \ 67 (&((struct cs_pair_attribute[]) { \ 68 { \ 69 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \ 70 lo_off, hi_off \ 71 } \ 72 })[0].attr.attr) 73 74 extern const u32 coresight_barrier_pkt[4]; 75 #define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt)) 76 77 enum etm_addr_type { 78 ETM_ADDR_TYPE_NONE, 79 ETM_ADDR_TYPE_SINGLE, 80 ETM_ADDR_TYPE_RANGE, 81 ETM_ADDR_TYPE_START, 82 ETM_ADDR_TYPE_STOP, 83 }; 84 85 /** 86 * struct cs_buffer - keep track of a recording session' specifics 87 * @cur: index of the current buffer 88 * @nr_pages: max number of pages granted to us 89 * @pid: PID this cs_buffer belongs to 90 * @offset: offset within the current buffer 91 * @data_size: how much we collected in this run 92 * @snapshot: is this run in snapshot mode 93 * @data_pages: a handle the ring buffer 94 */ 95 struct cs_buffers { 96 unsigned int cur; 97 unsigned int nr_pages; 98 pid_t pid; 99 unsigned long offset; 100 local_t data_size; 101 bool snapshot; 102 void **data_pages; 103 }; 104 105 static inline void coresight_insert_barrier_packet(void *buf) 106 { 107 if (buf) 108 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE); 109 } 110 111 static inline void CS_LOCK(void __iomem *addr) 112 { 113 do { 114 /* Wait for things to settle */ 115 mb(); 116 writel_relaxed(0x0, addr + CORESIGHT_LAR); 117 } while (0); 118 } 119 120 static inline void CS_UNLOCK(void __iomem *addr) 121 { 122 do { 123 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR); 124 /* Make sure everyone has seen this */ 125 mb(); 126 } while (0); 127 } 128 129 void coresight_disable_path(struct list_head *path); 130 int coresight_enable_path(struct list_head *path, enum cs_mode mode, 131 void *sink_data); 132 struct coresight_device *coresight_get_sink(struct list_head *path); 133 struct coresight_device * 134 coresight_get_enabled_sink(struct coresight_device *source); 135 struct coresight_device *coresight_get_sink_by_id(u32 id); 136 struct coresight_device * 137 coresight_find_default_sink(struct coresight_device *csdev); 138 struct list_head *coresight_build_path(struct coresight_device *csdev, 139 struct coresight_device *sink); 140 void coresight_release_path(struct list_head *path); 141 int coresight_add_sysfs_link(struct coresight_sysfs_link *info); 142 void coresight_remove_sysfs_link(struct coresight_sysfs_link *info); 143 int coresight_create_conns_sysfs_group(struct coresight_device *csdev); 144 void coresight_remove_conns_sysfs_group(struct coresight_device *csdev); 145 int coresight_make_links(struct coresight_device *orig, 146 struct coresight_connection *conn, 147 struct coresight_device *target); 148 void coresight_remove_links(struct coresight_device *orig, 149 struct coresight_connection *conn); 150 151 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) 152 extern int etm_readl_cp14(u32 off, unsigned int *val); 153 extern int etm_writel_cp14(u32 off, u32 val); 154 #else 155 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } 156 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } 157 #endif 158 159 struct cti_assoc_op { 160 void (*add)(struct coresight_device *csdev); 161 void (*remove)(struct coresight_device *csdev); 162 }; 163 164 extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op); 165 extern void coresight_remove_cti_ops(void); 166 167 /* 168 * Macros and inline functions to handle CoreSight UCI data and driver 169 * private data in AMBA ID table entries, and extract data values. 170 */ 171 172 /* coresight AMBA ID, no UCI, no driver data: id table entry */ 173 #define CS_AMBA_ID(pid) \ 174 { \ 175 .id = pid, \ 176 .mask = 0x000fffff, \ 177 } 178 179 /* coresight AMBA ID, UCI with driver data only: id table entry. */ 180 #define CS_AMBA_ID_DATA(pid, dval) \ 181 { \ 182 .id = pid, \ 183 .mask = 0x000fffff, \ 184 .data = (void *)&(struct amba_cs_uci_id) \ 185 { \ 186 .data = (void *)dval, \ 187 } \ 188 } 189 190 /* coresight AMBA ID, full UCI structure: id table entry. */ 191 #define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \ 192 { \ 193 .id = pid, \ 194 .mask = m, \ 195 .data = (void *)uci_ptr \ 196 } 197 #define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci) 198 /* 199 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the 200 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that 201 * as a match value for blanket matching all devices in the given CoreSight 202 * device type and architecture. 203 */ 204 #define PIDR2_JEDEC BIT(3) 205 #define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16) 206 /* 207 * Match all PIDs in a given CoreSight device type and architecture, defined 208 * by the uci. 209 */ 210 #define CS_AMBA_MATCH_ALL_UCI(uci) \ 211 __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci) 212 213 /* extract the data value from a UCI structure given amba_id pointer. */ 214 static inline void *coresight_get_uci_data(const struct amba_id *id) 215 { 216 struct amba_cs_uci_id *uci_id = id->data; 217 218 if (!uci_id) 219 return NULL; 220 221 return uci_id->data; 222 } 223 224 void coresight_release_platform_data(struct coresight_device *csdev, 225 struct device *dev, 226 struct coresight_platform_data *pdata); 227 struct coresight_device * 228 coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode); 229 void coresight_add_helper(struct coresight_device *csdev, 230 struct coresight_device *helper); 231 232 void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev); 233 struct coresight_device *coresight_get_percpu_sink(int cpu); 234 int coresight_enable_source(struct coresight_device *csdev, enum cs_mode mode, 235 void *data); 236 void coresight_disable_source(struct coresight_device *csdev, void *data); 237 238 #endif 239