1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_CORESIGHT_ETM_H 7 #define _CORESIGHT_CORESIGHT_ETM_H 8 9 #include <asm/local.h> 10 #include <linux/spinlock.h> 11 #include <linux/types.h> 12 #include "coresight-priv.h" 13 14 /* 15 * Device registers: 16 * 0x000 - 0x2FC: Trace registers 17 * 0x300 - 0x314: Management registers 18 * 0x318 - 0xEFC: Trace registers 19 * 0xF00: Management registers 20 * 0xFA0 - 0xFA4: Trace registers 21 * 0xFA8 - 0xFFC: Management registers 22 */ 23 /* Trace registers (0x000-0x2FC) */ 24 /* Main control and configuration registers */ 25 #define TRCPRGCTLR 0x004 26 #define TRCPROCSELR 0x008 27 #define TRCSTATR 0x00C 28 #define TRCCONFIGR 0x010 29 #define TRCAUXCTLR 0x018 30 #define TRCEVENTCTL0R 0x020 31 #define TRCEVENTCTL1R 0x024 32 #define TRCRSR 0x028 33 #define TRCSTALLCTLR 0x02C 34 #define TRCTSCTLR 0x030 35 #define TRCSYNCPR 0x034 36 #define TRCCCCTLR 0x038 37 #define TRCBBCTLR 0x03C 38 #define TRCTRACEIDR 0x040 39 #define TRCQCTLR 0x044 40 /* Filtering control registers */ 41 #define TRCVICTLR 0x080 42 #define TRCVIIECTLR 0x084 43 #define TRCVISSCTLR 0x088 44 #define TRCVIPCSSCTLR 0x08C 45 #define TRCVDCTLR 0x0A0 46 #define TRCVDSACCTLR 0x0A4 47 #define TRCVDARCCTLR 0x0A8 48 /* Derived resources registers */ 49 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ 50 #define TRCSEQRSTEVR 0x118 51 #define TRCSEQSTR 0x11C 52 #define TRCEXTINSELR 0x120 53 #define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */ 54 #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ 55 #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ 56 #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ 57 /* ID registers */ 58 #define TRCIDR8 0x180 59 #define TRCIDR9 0x184 60 #define TRCIDR10 0x188 61 #define TRCIDR11 0x18C 62 #define TRCIDR12 0x190 63 #define TRCIDR13 0x194 64 #define TRCIMSPEC0 0x1C0 65 #define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ 66 #define TRCIDR0 0x1E0 67 #define TRCIDR1 0x1E4 68 #define TRCIDR2 0x1E8 69 #define TRCIDR3 0x1EC 70 #define TRCIDR4 0x1F0 71 #define TRCIDR5 0x1F4 72 #define TRCIDR6 0x1F8 73 #define TRCIDR7 0x1FC 74 /* 75 * Resource selection registers, n = 2-31. 76 * First pair (regs 0, 1) is always present and is reserved. 77 */ 78 #define TRCRSCTLRn(n) (0x200 + (n * 4)) 79 /* Single-shot comparator registers, n = 0-7 */ 80 #define TRCSSCCRn(n) (0x280 + (n * 4)) 81 #define TRCSSCSRn(n) (0x2A0 + (n * 4)) 82 #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) 83 /* Management registers (0x300-0x314) */ 84 #define TRCOSLAR 0x300 85 #define TRCOSLSR 0x304 86 #define TRCPDCR 0x310 87 #define TRCPDSR 0x314 88 /* Trace registers (0x318-0xEFC) */ 89 /* Address Comparator registers n = 0-15 */ 90 #define TRCACVRn(n) (0x400 + (n * 8)) 91 #define TRCACATRn(n) (0x480 + (n * 8)) 92 /* Data Value Comparator Value registers, n = 0-7 */ 93 #define TRCDVCVRn(n) (0x500 + (n * 16)) 94 #define TRCDVCMRn(n) (0x580 + (n * 16)) 95 /* ContextID/Virtual ContextID comparators, n = 0-7 */ 96 #define TRCCIDCVRn(n) (0x600 + (n * 8)) 97 #define TRCVMIDCVRn(n) (0x640 + (n * 8)) 98 #define TRCCIDCCTLR0 0x680 99 #define TRCCIDCCTLR1 0x684 100 #define TRCVMIDCCTLR0 0x688 101 #define TRCVMIDCCTLR1 0x68C 102 /* Management register (0xF00) */ 103 /* Integration control registers */ 104 #define TRCITCTRL 0xF00 105 /* Trace registers (0xFA0-0xFA4) */ 106 /* Claim tag registers */ 107 #define TRCCLAIMSET 0xFA0 108 #define TRCCLAIMCLR 0xFA4 109 /* Management registers (0xFA8-0xFFC) */ 110 #define TRCDEVAFF0 0xFA8 111 #define TRCDEVAFF1 0xFAC 112 #define TRCLAR 0xFB0 113 #define TRCLSR 0xFB4 114 #define TRCAUTHSTATUS 0xFB8 115 #define TRCDEVARCH 0xFBC 116 #define TRCDEVID 0xFC8 117 #define TRCDEVTYPE 0xFCC 118 #define TRCPIDR4 0xFD0 119 #define TRCPIDR5 0xFD4 120 #define TRCPIDR6 0xFD8 121 #define TRCPIDR7 0xFDC 122 #define TRCPIDR0 0xFE0 123 #define TRCPIDR1 0xFE4 124 #define TRCPIDR2 0xFE8 125 #define TRCPIDR3 0xFEC 126 #define TRCCIDR0 0xFF0 127 #define TRCCIDR1 0xFF4 128 #define TRCCIDR2 0xFF8 129 #define TRCCIDR3 0xFFC 130 131 #define TRCRSR_TA BIT(12) 132 133 /* 134 * Bit positions of registers that are defined above, in the sysreg.h style 135 * of _MASK for multi bit fields and BIT() for single bits. 136 */ 137 #define TRCIDR0_INSTP0_MASK GENMASK(2, 1) 138 #define TRCIDR0_TRCBB BIT(5) 139 #define TRCIDR0_TRCCOND BIT(6) 140 #define TRCIDR0_TRCCCI BIT(7) 141 #define TRCIDR0_RETSTACK BIT(9) 142 #define TRCIDR0_NUMEVENT_MASK GENMASK(11, 10) 143 #define TRCIDR0_QSUPP_MASK GENMASK(16, 15) 144 #define TRCIDR0_TSSIZE_MASK GENMASK(28, 24) 145 146 #define TRCIDR2_CIDSIZE_MASK GENMASK(9, 5) 147 #define TRCIDR2_VMIDSIZE_MASK GENMASK(14, 10) 148 #define TRCIDR2_CCSIZE_MASK GENMASK(28, 25) 149 150 #define TRCIDR3_CCITMIN_MASK GENMASK(11, 0) 151 #define TRCIDR3_EXLEVEL_S_MASK GENMASK(19, 16) 152 #define TRCIDR3_EXLEVEL_NS_MASK GENMASK(23, 20) 153 #define TRCIDR3_TRCERR BIT(24) 154 #define TRCIDR3_SYNCPR BIT(25) 155 #define TRCIDR3_STALLCTL BIT(26) 156 #define TRCIDR3_SYSSTALL BIT(27) 157 #define TRCIDR3_NUMPROC_LO_MASK GENMASK(30, 28) 158 #define TRCIDR3_NUMPROC_HI_MASK GENMASK(13, 12) 159 #define TRCIDR3_NOOVERFLOW BIT(31) 160 161 #define TRCIDR4_NUMACPAIRS_MASK GENMASK(3, 0) 162 #define TRCIDR4_NUMPC_MASK GENMASK(15, 12) 163 #define TRCIDR4_NUMRSPAIR_MASK GENMASK(19, 16) 164 #define TRCIDR4_NUMSSCC_MASK GENMASK(23, 20) 165 #define TRCIDR4_NUMCIDC_MASK GENMASK(27, 24) 166 #define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28) 167 168 #define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0) 169 #define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16) 170 #define TRCIDR5_ATBTRIG BIT(22) 171 #define TRCIDR5_LPOVERRIDE BIT(23) 172 #define TRCIDR5_NUMSEQSTATE_MASK GENMASK(27, 25) 173 #define TRCIDR5_NUMCNTR_MASK GENMASK(30, 28) 174 175 #define TRCCONFIGR_INSTP0_LOAD BIT(1) 176 #define TRCCONFIGR_INSTP0_STORE BIT(2) 177 #define TRCCONFIGR_INSTP0_LOAD_STORE (TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE) 178 #define TRCCONFIGR_BB BIT(3) 179 #define TRCCONFIGR_CCI BIT(4) 180 #define TRCCONFIGR_CID BIT(6) 181 #define TRCCONFIGR_VMID BIT(7) 182 #define TRCCONFIGR_COND_MASK GENMASK(10, 8) 183 #define TRCCONFIGR_TS BIT(11) 184 #define TRCCONFIGR_RS BIT(12) 185 #define TRCCONFIGR_QE_W_COUNTS BIT(13) 186 #define TRCCONFIGR_QE_WO_COUNTS BIT(14) 187 #define TRCCONFIGR_VMIDOPT BIT(15) 188 #define TRCCONFIGR_DA BIT(16) 189 #define TRCCONFIGR_DV BIT(17) 190 191 #define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0) 192 #define TRCEVENTCTL1R_INSTEN_0 BIT(0) 193 #define TRCEVENTCTL1R_INSTEN_1 BIT(1) 194 #define TRCEVENTCTL1R_INSTEN_2 BIT(2) 195 #define TRCEVENTCTL1R_INSTEN_3 BIT(3) 196 #define TRCEVENTCTL1R_ATB BIT(11) 197 #define TRCEVENTCTL1R_LPOVERRIDE BIT(12) 198 199 #define TRCSTALLCTLR_ISTALL BIT(8) 200 #define TRCSTALLCTLR_INSTPRIORITY BIT(10) 201 #define TRCSTALLCTLR_NOOVERFLOW BIT(13) 202 203 #define TRCVICTLR_EVENT_MASK GENMASK(7, 0) 204 #define TRCVICTLR_SSSTATUS BIT(9) 205 #define TRCVICTLR_TRCRESET BIT(10) 206 #define TRCVICTLR_TRCERR BIT(11) 207 #define TRCVICTLR_EXLEVEL_MASK GENMASK(22, 16) 208 #define TRCVICTLR_EXLEVEL_S_MASK GENMASK(19, 16) 209 #define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(22, 20) 210 211 #define TRCACATRn_TYPE_MASK GENMASK(1, 0) 212 #define TRCACATRn_CONTEXTTYPE_MASK GENMASK(3, 2) 213 #define TRCACATRn_CONTEXTTYPE_CTXID BIT(2) 214 #define TRCACATRn_CONTEXTTYPE_VMID BIT(3) 215 #define TRCACATRn_CONTEXT_MASK GENMASK(6, 4) 216 #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) 217 218 #define TRCSSCSRn_STATUS BIT(31) 219 #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) 220 221 #define TRCSSPCICRn_PC_MASK GENMASK(7, 0) 222 223 #define TRCBBCTLR_MODE BIT(8) 224 #define TRCBBCTLR_RANGE_MASK GENMASK(7, 0) 225 226 #define TRCRSCTLRn_PAIRINV BIT(21) 227 #define TRCRSCTLRn_INV BIT(20) 228 #define TRCRSCTLRn_GROUP_MASK GENMASK(19, 16) 229 #define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0) 230 231 /* 232 * System instructions to access ETM registers. 233 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions 234 */ 235 #define ETM4x_OFFSET_TO_REG(x) ((x) >> 2) 236 237 #define ETM4x_CRn(n) (((n) >> 7) & 0x7) 238 #define ETM4x_Op2(n) (((n) >> 4) & 0x7) 239 #define ETM4x_CRm(n) ((n) & 0xf) 240 241 #include <asm/sysreg.h> 242 #define ETM4x_REG_NUM_TO_SYSREG(n) \ 243 sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n)) 244 245 #define READ_ETM4x_REG(reg) \ 246 read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) 247 #define WRITE_ETM4x_REG(val, reg) \ 248 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg))) 249 250 #define read_etm4x_sysreg_const_offset(offset) \ 251 READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) 252 253 #define write_etm4x_sysreg_const_offset(val, offset) \ 254 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset)) 255 256 #define CASE_READ(res, x) \ 257 case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; } 258 259 #define CASE_WRITE(val, x) \ 260 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; } 261 262 #define CASE_NOP(__unused, x) \ 263 case (x): /* fall through */ 264 265 #define ETE_ONLY_SYSREG_LIST(op, val) \ 266 CASE_##op((val), TRCRSR) \ 267 CASE_##op((val), TRCEXTINSELRn(1)) \ 268 CASE_##op((val), TRCEXTINSELRn(2)) \ 269 CASE_##op((val), TRCEXTINSELRn(3)) 270 271 /* List of registers accessible via System instructions */ 272 #define ETM4x_ONLY_SYSREG_LIST(op, val) \ 273 CASE_##op((val), TRCPROCSELR) \ 274 CASE_##op((val), TRCVDCTLR) \ 275 CASE_##op((val), TRCVDSACCTLR) \ 276 CASE_##op((val), TRCVDARCCTLR) \ 277 CASE_##op((val), TRCOSLAR) 278 279 #define ETM_COMMON_SYSREG_LIST(op, val) \ 280 CASE_##op((val), TRCPRGCTLR) \ 281 CASE_##op((val), TRCSTATR) \ 282 CASE_##op((val), TRCCONFIGR) \ 283 CASE_##op((val), TRCAUXCTLR) \ 284 CASE_##op((val), TRCEVENTCTL0R) \ 285 CASE_##op((val), TRCEVENTCTL1R) \ 286 CASE_##op((val), TRCSTALLCTLR) \ 287 CASE_##op((val), TRCTSCTLR) \ 288 CASE_##op((val), TRCSYNCPR) \ 289 CASE_##op((val), TRCCCCTLR) \ 290 CASE_##op((val), TRCBBCTLR) \ 291 CASE_##op((val), TRCTRACEIDR) \ 292 CASE_##op((val), TRCQCTLR) \ 293 CASE_##op((val), TRCVICTLR) \ 294 CASE_##op((val), TRCVIIECTLR) \ 295 CASE_##op((val), TRCVISSCTLR) \ 296 CASE_##op((val), TRCVIPCSSCTLR) \ 297 CASE_##op((val), TRCSEQEVRn(0)) \ 298 CASE_##op((val), TRCSEQEVRn(1)) \ 299 CASE_##op((val), TRCSEQEVRn(2)) \ 300 CASE_##op((val), TRCSEQRSTEVR) \ 301 CASE_##op((val), TRCSEQSTR) \ 302 CASE_##op((val), TRCEXTINSELR) \ 303 CASE_##op((val), TRCCNTRLDVRn(0)) \ 304 CASE_##op((val), TRCCNTRLDVRn(1)) \ 305 CASE_##op((val), TRCCNTRLDVRn(2)) \ 306 CASE_##op((val), TRCCNTRLDVRn(3)) \ 307 CASE_##op((val), TRCCNTCTLRn(0)) \ 308 CASE_##op((val), TRCCNTCTLRn(1)) \ 309 CASE_##op((val), TRCCNTCTLRn(2)) \ 310 CASE_##op((val), TRCCNTCTLRn(3)) \ 311 CASE_##op((val), TRCCNTVRn(0)) \ 312 CASE_##op((val), TRCCNTVRn(1)) \ 313 CASE_##op((val), TRCCNTVRn(2)) \ 314 CASE_##op((val), TRCCNTVRn(3)) \ 315 CASE_##op((val), TRCIDR8) \ 316 CASE_##op((val), TRCIDR9) \ 317 CASE_##op((val), TRCIDR10) \ 318 CASE_##op((val), TRCIDR11) \ 319 CASE_##op((val), TRCIDR12) \ 320 CASE_##op((val), TRCIDR13) \ 321 CASE_##op((val), TRCIMSPECn(0)) \ 322 CASE_##op((val), TRCIMSPECn(1)) \ 323 CASE_##op((val), TRCIMSPECn(2)) \ 324 CASE_##op((val), TRCIMSPECn(3)) \ 325 CASE_##op((val), TRCIMSPECn(4)) \ 326 CASE_##op((val), TRCIMSPECn(5)) \ 327 CASE_##op((val), TRCIMSPECn(6)) \ 328 CASE_##op((val), TRCIMSPECn(7)) \ 329 CASE_##op((val), TRCIDR0) \ 330 CASE_##op((val), TRCIDR1) \ 331 CASE_##op((val), TRCIDR2) \ 332 CASE_##op((val), TRCIDR3) \ 333 CASE_##op((val), TRCIDR4) \ 334 CASE_##op((val), TRCIDR5) \ 335 CASE_##op((val), TRCIDR6) \ 336 CASE_##op((val), TRCIDR7) \ 337 CASE_##op((val), TRCRSCTLRn(2)) \ 338 CASE_##op((val), TRCRSCTLRn(3)) \ 339 CASE_##op((val), TRCRSCTLRn(4)) \ 340 CASE_##op((val), TRCRSCTLRn(5)) \ 341 CASE_##op((val), TRCRSCTLRn(6)) \ 342 CASE_##op((val), TRCRSCTLRn(7)) \ 343 CASE_##op((val), TRCRSCTLRn(8)) \ 344 CASE_##op((val), TRCRSCTLRn(9)) \ 345 CASE_##op((val), TRCRSCTLRn(10)) \ 346 CASE_##op((val), TRCRSCTLRn(11)) \ 347 CASE_##op((val), TRCRSCTLRn(12)) \ 348 CASE_##op((val), TRCRSCTLRn(13)) \ 349 CASE_##op((val), TRCRSCTLRn(14)) \ 350 CASE_##op((val), TRCRSCTLRn(15)) \ 351 CASE_##op((val), TRCRSCTLRn(16)) \ 352 CASE_##op((val), TRCRSCTLRn(17)) \ 353 CASE_##op((val), TRCRSCTLRn(18)) \ 354 CASE_##op((val), TRCRSCTLRn(19)) \ 355 CASE_##op((val), TRCRSCTLRn(20)) \ 356 CASE_##op((val), TRCRSCTLRn(21)) \ 357 CASE_##op((val), TRCRSCTLRn(22)) \ 358 CASE_##op((val), TRCRSCTLRn(23)) \ 359 CASE_##op((val), TRCRSCTLRn(24)) \ 360 CASE_##op((val), TRCRSCTLRn(25)) \ 361 CASE_##op((val), TRCRSCTLRn(26)) \ 362 CASE_##op((val), TRCRSCTLRn(27)) \ 363 CASE_##op((val), TRCRSCTLRn(28)) \ 364 CASE_##op((val), TRCRSCTLRn(29)) \ 365 CASE_##op((val), TRCRSCTLRn(30)) \ 366 CASE_##op((val), TRCRSCTLRn(31)) \ 367 CASE_##op((val), TRCSSCCRn(0)) \ 368 CASE_##op((val), TRCSSCCRn(1)) \ 369 CASE_##op((val), TRCSSCCRn(2)) \ 370 CASE_##op((val), TRCSSCCRn(3)) \ 371 CASE_##op((val), TRCSSCCRn(4)) \ 372 CASE_##op((val), TRCSSCCRn(5)) \ 373 CASE_##op((val), TRCSSCCRn(6)) \ 374 CASE_##op((val), TRCSSCCRn(7)) \ 375 CASE_##op((val), TRCSSCSRn(0)) \ 376 CASE_##op((val), TRCSSCSRn(1)) \ 377 CASE_##op((val), TRCSSCSRn(2)) \ 378 CASE_##op((val), TRCSSCSRn(3)) \ 379 CASE_##op((val), TRCSSCSRn(4)) \ 380 CASE_##op((val), TRCSSCSRn(5)) \ 381 CASE_##op((val), TRCSSCSRn(6)) \ 382 CASE_##op((val), TRCSSCSRn(7)) \ 383 CASE_##op((val), TRCSSPCICRn(0)) \ 384 CASE_##op((val), TRCSSPCICRn(1)) \ 385 CASE_##op((val), TRCSSPCICRn(2)) \ 386 CASE_##op((val), TRCSSPCICRn(3)) \ 387 CASE_##op((val), TRCSSPCICRn(4)) \ 388 CASE_##op((val), TRCSSPCICRn(5)) \ 389 CASE_##op((val), TRCSSPCICRn(6)) \ 390 CASE_##op((val), TRCSSPCICRn(7)) \ 391 CASE_##op((val), TRCOSLSR) \ 392 CASE_##op((val), TRCACVRn(0)) \ 393 CASE_##op((val), TRCACVRn(1)) \ 394 CASE_##op((val), TRCACVRn(2)) \ 395 CASE_##op((val), TRCACVRn(3)) \ 396 CASE_##op((val), TRCACVRn(4)) \ 397 CASE_##op((val), TRCACVRn(5)) \ 398 CASE_##op((val), TRCACVRn(6)) \ 399 CASE_##op((val), TRCACVRn(7)) \ 400 CASE_##op((val), TRCACVRn(8)) \ 401 CASE_##op((val), TRCACVRn(9)) \ 402 CASE_##op((val), TRCACVRn(10)) \ 403 CASE_##op((val), TRCACVRn(11)) \ 404 CASE_##op((val), TRCACVRn(12)) \ 405 CASE_##op((val), TRCACVRn(13)) \ 406 CASE_##op((val), TRCACVRn(14)) \ 407 CASE_##op((val), TRCACVRn(15)) \ 408 CASE_##op((val), TRCACATRn(0)) \ 409 CASE_##op((val), TRCACATRn(1)) \ 410 CASE_##op((val), TRCACATRn(2)) \ 411 CASE_##op((val), TRCACATRn(3)) \ 412 CASE_##op((val), TRCACATRn(4)) \ 413 CASE_##op((val), TRCACATRn(5)) \ 414 CASE_##op((val), TRCACATRn(6)) \ 415 CASE_##op((val), TRCACATRn(7)) \ 416 CASE_##op((val), TRCACATRn(8)) \ 417 CASE_##op((val), TRCACATRn(9)) \ 418 CASE_##op((val), TRCACATRn(10)) \ 419 CASE_##op((val), TRCACATRn(11)) \ 420 CASE_##op((val), TRCACATRn(12)) \ 421 CASE_##op((val), TRCACATRn(13)) \ 422 CASE_##op((val), TRCACATRn(14)) \ 423 CASE_##op((val), TRCACATRn(15)) \ 424 CASE_##op((val), TRCDVCVRn(0)) \ 425 CASE_##op((val), TRCDVCVRn(1)) \ 426 CASE_##op((val), TRCDVCVRn(2)) \ 427 CASE_##op((val), TRCDVCVRn(3)) \ 428 CASE_##op((val), TRCDVCVRn(4)) \ 429 CASE_##op((val), TRCDVCVRn(5)) \ 430 CASE_##op((val), TRCDVCVRn(6)) \ 431 CASE_##op((val), TRCDVCVRn(7)) \ 432 CASE_##op((val), TRCDVCMRn(0)) \ 433 CASE_##op((val), TRCDVCMRn(1)) \ 434 CASE_##op((val), TRCDVCMRn(2)) \ 435 CASE_##op((val), TRCDVCMRn(3)) \ 436 CASE_##op((val), TRCDVCMRn(4)) \ 437 CASE_##op((val), TRCDVCMRn(5)) \ 438 CASE_##op((val), TRCDVCMRn(6)) \ 439 CASE_##op((val), TRCDVCMRn(7)) \ 440 CASE_##op((val), TRCCIDCVRn(0)) \ 441 CASE_##op((val), TRCCIDCVRn(1)) \ 442 CASE_##op((val), TRCCIDCVRn(2)) \ 443 CASE_##op((val), TRCCIDCVRn(3)) \ 444 CASE_##op((val), TRCCIDCVRn(4)) \ 445 CASE_##op((val), TRCCIDCVRn(5)) \ 446 CASE_##op((val), TRCCIDCVRn(6)) \ 447 CASE_##op((val), TRCCIDCVRn(7)) \ 448 CASE_##op((val), TRCVMIDCVRn(0)) \ 449 CASE_##op((val), TRCVMIDCVRn(1)) \ 450 CASE_##op((val), TRCVMIDCVRn(2)) \ 451 CASE_##op((val), TRCVMIDCVRn(3)) \ 452 CASE_##op((val), TRCVMIDCVRn(4)) \ 453 CASE_##op((val), TRCVMIDCVRn(5)) \ 454 CASE_##op((val), TRCVMIDCVRn(6)) \ 455 CASE_##op((val), TRCVMIDCVRn(7)) \ 456 CASE_##op((val), TRCCIDCCTLR0) \ 457 CASE_##op((val), TRCCIDCCTLR1) \ 458 CASE_##op((val), TRCVMIDCCTLR0) \ 459 CASE_##op((val), TRCVMIDCCTLR1) \ 460 CASE_##op((val), TRCCLAIMSET) \ 461 CASE_##op((val), TRCCLAIMCLR) \ 462 CASE_##op((val), TRCAUTHSTATUS) \ 463 CASE_##op((val), TRCDEVARCH) \ 464 CASE_##op((val), TRCDEVID) 465 466 /* List of registers only accessible via memory-mapped interface */ 467 #define ETM_MMAP_LIST(op, val) \ 468 CASE_##op((val), TRCDEVTYPE) \ 469 CASE_##op((val), TRCPDCR) \ 470 CASE_##op((val), TRCPDSR) \ 471 CASE_##op((val), TRCDEVAFF0) \ 472 CASE_##op((val), TRCDEVAFF1) \ 473 CASE_##op((val), TRCLAR) \ 474 CASE_##op((val), TRCLSR) \ 475 CASE_##op((val), TRCITCTRL) \ 476 CASE_##op((val), TRCPIDR4) \ 477 CASE_##op((val), TRCPIDR0) \ 478 CASE_##op((val), TRCPIDR1) \ 479 CASE_##op((val), TRCPIDR2) \ 480 CASE_##op((val), TRCPIDR3) 481 482 #define ETM4x_READ_SYSREG_CASES(res) \ 483 ETM_COMMON_SYSREG_LIST(READ, (res)) \ 484 ETM4x_ONLY_SYSREG_LIST(READ, (res)) 485 486 #define ETM4x_WRITE_SYSREG_CASES(val) \ 487 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \ 488 ETM4x_ONLY_SYSREG_LIST(WRITE, (val)) 489 490 #define ETM_COMMON_SYSREG_LIST_CASES \ 491 ETM_COMMON_SYSREG_LIST(NOP, __unused) 492 493 #define ETM4x_ONLY_SYSREG_LIST_CASES \ 494 ETM4x_ONLY_SYSREG_LIST(NOP, __unused) 495 496 #define ETM4x_SYSREG_LIST_CASES \ 497 ETM_COMMON_SYSREG_LIST_CASES \ 498 ETM4x_ONLY_SYSREG_LIST(NOP, __unused) 499 500 #define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused) 501 502 /* ETE only supports system register access */ 503 #define ETE_READ_CASES(res) \ 504 ETM_COMMON_SYSREG_LIST(READ, (res)) \ 505 ETE_ONLY_SYSREG_LIST(READ, (res)) 506 507 #define ETE_WRITE_CASES(val) \ 508 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \ 509 ETE_ONLY_SYSREG_LIST(WRITE, (val)) 510 511 #define ETE_ONLY_SYSREG_LIST_CASES \ 512 ETE_ONLY_SYSREG_LIST(NOP, __unused) 513 514 #define read_etm4x_sysreg_offset(offset, _64bit) \ 515 ({ \ 516 u64 __val; \ 517 \ 518 if (__builtin_constant_p((offset))) \ 519 __val = read_etm4x_sysreg_const_offset((offset)); \ 520 else \ 521 __val = etm4x_sysreg_read((offset), true, (_64bit)); \ 522 __val; \ 523 }) 524 525 #define write_etm4x_sysreg_offset(val, offset, _64bit) \ 526 do { \ 527 if (__builtin_constant_p((offset))) \ 528 write_etm4x_sysreg_const_offset((val), \ 529 (offset)); \ 530 else \ 531 etm4x_sysreg_write((val), (offset), true, \ 532 (_64bit)); \ 533 } while (0) 534 535 536 #define etm4x_relaxed_read32(csa, offset) \ 537 ((u32)((csa)->io_mem ? \ 538 readl_relaxed((csa)->base + (offset)) : \ 539 read_etm4x_sysreg_offset((offset), false))) 540 541 #define etm4x_relaxed_read64(csa, offset) \ 542 ((u64)((csa)->io_mem ? \ 543 readq_relaxed((csa)->base + (offset)) : \ 544 read_etm4x_sysreg_offset((offset), true))) 545 546 #define etm4x_read32(csa, offset) \ 547 ({ \ 548 u32 __val = etm4x_relaxed_read32((csa), (offset)); \ 549 __iormb(__val); \ 550 __val; \ 551 }) 552 553 #define etm4x_read64(csa, offset) \ 554 ({ \ 555 u64 __val = etm4x_relaxed_read64((csa), (offset)); \ 556 __iormb(__val); \ 557 __val; \ 558 }) 559 560 #define etm4x_relaxed_write32(csa, val, offset) \ 561 do { \ 562 if ((csa)->io_mem) \ 563 writel_relaxed((val), (csa)->base + (offset)); \ 564 else \ 565 write_etm4x_sysreg_offset((val), (offset), \ 566 false); \ 567 } while (0) 568 569 #define etm4x_relaxed_write64(csa, val, offset) \ 570 do { \ 571 if ((csa)->io_mem) \ 572 writeq_relaxed((val), (csa)->base + (offset)); \ 573 else \ 574 write_etm4x_sysreg_offset((val), (offset), \ 575 true); \ 576 } while (0) 577 578 #define etm4x_write32(csa, val, offset) \ 579 do { \ 580 __iowmb(); \ 581 etm4x_relaxed_write32((csa), (val), (offset)); \ 582 } while (0) 583 584 #define etm4x_write64(csa, val, offset) \ 585 do { \ 586 __iowmb(); \ 587 etm4x_relaxed_write64((csa), (val), (offset)); \ 588 } while (0) 589 590 591 /* ETMv4 resources */ 592 #define ETM_MAX_NR_PE 8 593 #define ETMv4_MAX_CNTR 4 594 #define ETM_MAX_SEQ_STATES 4 595 #define ETM_MAX_EXT_INP_SEL 4 596 #define ETM_MAX_EXT_INP 256 597 #define ETM_MAX_EXT_OUT 4 598 #define ETM_MAX_SINGLE_ADDR_CMP 16 599 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) 600 #define ETM_MAX_DATA_VAL_CMP 8 601 #define ETMv4_MAX_CTXID_CMP 8 602 #define ETM_MAX_VMID_CMP 8 603 #define ETM_MAX_PE_CMP 8 604 #define ETM_MAX_RES_SEL 32 605 #define ETM_MAX_SS_CMP 8 606 607 #define ETMv4_SYNC_MASK 0x1F 608 #define ETM_CYC_THRESHOLD_MASK 0xFFF 609 #define ETM_CYC_THRESHOLD_DEFAULT 0x100 610 #define ETMv4_EVENT_MASK 0xFF 611 #define ETM_CNTR_MAX_VAL 0xFFFF 612 #define ETM_TRACEID_MASK 0x3f 613 614 /* ETMv4 programming modes */ 615 #define ETM_MODE_EXCLUDE BIT(0) 616 #define ETM_MODE_LOAD BIT(1) 617 #define ETM_MODE_STORE BIT(2) 618 #define ETM_MODE_LOAD_STORE BIT(3) 619 #define ETM_MODE_BB BIT(4) 620 #define ETMv4_MODE_CYCACC BIT(5) 621 #define ETMv4_MODE_CTXID BIT(6) 622 #define ETM_MODE_VMID BIT(7) 623 #define ETM_MODE_COND(val) BMVAL(val, 8, 10) 624 #define ETMv4_MODE_TIMESTAMP BIT(11) 625 #define ETM_MODE_RETURNSTACK BIT(12) 626 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) 627 #define ETM_MODE_DATA_TRACE_ADDR BIT(15) 628 #define ETM_MODE_DATA_TRACE_VAL BIT(16) 629 #define ETM_MODE_ISTALL BIT(17) 630 #define ETM_MODE_DSTALL BIT(18) 631 #define ETM_MODE_ATB_TRIGGER BIT(19) 632 #define ETM_MODE_LPOVERRIDE BIT(20) 633 #define ETM_MODE_ISTALL_EN BIT(21) 634 #define ETM_MODE_DSTALL_EN BIT(22) 635 #define ETM_MODE_INSTPRIO BIT(23) 636 #define ETM_MODE_NOOVERFLOW BIT(24) 637 #define ETM_MODE_TRACE_RESET BIT(25) 638 #define ETM_MODE_TRACE_ERR BIT(26) 639 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27) 640 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \ 641 ETM_MODE_EXCL_KERN | \ 642 ETM_MODE_EXCL_USER) 643 644 /* 645 * TRCOSLSR.OSLM advertises the OS Lock model. 646 * OSLM[2:0] = TRCOSLSR[4:3,0] 647 * 648 * 0b000 - Trace OS Lock is not implemented. 649 * 0b010 - Trace OS Lock is implemented. 650 * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock. 651 */ 652 #define ETM_OSLOCK_NI 0b000 653 #define ETM_OSLOCK_PRESENT 0b010 654 #define ETM_OSLOCK_PE 0b100 655 656 #define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1)) 657 658 /* 659 * TRCDEVARCH Bit field definitions 660 * Bits[31:21] - ARCHITECT = Always Arm Ltd. 661 * * Bits[31:28] = 0x4 662 * * Bits[27:21] = 0b0111011 663 * Bit[20] - PRESENT, Indicates the presence of this register. 664 * 665 * Bit[19:16] - REVISION, Revision of the architecture. 666 * 667 * Bit[15:0] - ARCHID, Identifies this component as an ETM 668 * * Bits[15:12] - architecture version of ETM 669 * * = 4 for ETMv4 670 * * Bits[11:0] = 0xA13, architecture part number for ETM. 671 */ 672 #define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) 673 #define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) 674 #define ETM_DEVARCH_PRESENT BIT(20) 675 #define ETM_DEVARCH_REVISION_SHIFT 16 676 #define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) 677 #define ETM_DEVARCH_REVISION(x) \ 678 (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT) 679 #define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) 680 #define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 681 #define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12) 682 #define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ 683 (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) 684 685 #define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \ 686 (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) 687 688 #define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) 689 690 #define ETM_DEVARCH_MAKE_ARCHID(major) \ 691 ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) 692 693 #define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) 694 #define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5) 695 696 #define ETM_DEVARCH_ID_MASK \ 697 (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) 698 #define ETM_DEVARCH_ETMv4x_ARCH \ 699 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT) 700 #define ETM_DEVARCH_ETE_ARCH \ 701 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT) 702 703 #define TRCSTATR_IDLE_BIT 0 704 #define TRCSTATR_PMSTABLE_BIT 1 705 #define ETM_DEFAULT_ADDR_COMP 0 706 707 #define TRCSSCSRn_PC BIT(3) 708 709 /* PowerDown Control Register bits */ 710 #define TRCPDCR_PU BIT(3) 711 712 #define TRCACATR_EXLEVEL_SHIFT 8 713 714 /* 715 * Exception level mask for Secure and Non-Secure ELs. 716 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). 717 * The Secure and Non-Secure ELs are always to gether. 718 * Non-secure EL3 is never implemented. 719 * We use the following generic mask as they appear in different 720 * registers and this can be shifted for the appropriate 721 * fields. 722 */ 723 #define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */ 724 #define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */ 725 #define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */ 726 #define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */ 727 #define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */ 728 #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ 729 #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ 730 731 /* access level controls in TRCACATRn */ 732 #define TRCACATR_EXLEVEL_SHIFT 8 733 734 #define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 735 #define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) 736 #define ETM_TRCIDR1_ARCH_MAJOR(x) \ 737 (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT) 738 #define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4 739 #define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT) 740 #define ETM_TRCIDR1_ARCH_MINOR(x) \ 741 (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT) 742 #define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT 743 #define ETM_TRCIDR1_ARCH_MASK \ 744 (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK) 745 746 #define ETM_TRCIDR1_ARCH_ETMv4 0x4 747 748 /* 749 * Driver representation of the ETM architecture. 750 * The version of an ETM component can be detected from 751 * 752 * TRCDEVARCH - CoreSight architected register 753 * - Bits[15:12] - Major version 754 * - Bits[19:16] - Minor version 755 * TRCIDR1 - ETM architected register 756 * - Bits[11:8] - Major version 757 * - Bits[7:4] - Minor version 758 * We must rely on TRCDEVARCH for the version information, 759 * however we don't want to break the support for potential 760 * old implementations which might not implement it. Thus 761 * we fall back to TRCIDR1 if TRCDEVARCH is not implemented 762 * for memory mapped components. 763 * Now to make certain decisions easier based on the version 764 * we use an internal representation of the version in the 765 * driver, as follows : 766 * 767 * ETM_ARCH_VERSION[7:0], where : 768 * Bits[7:4] - Major version 769 * Bits[3:0] - Minro version 770 */ 771 #define ETM_ARCH_VERSION(major, minor) \ 772 ((((major) & 0xfU) << 4) | (((minor) & 0xfU))) 773 #define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU) 774 #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) 775 776 #define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) 777 #define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0) 778 779 /* Interpretation of resource numbers change at ETM v4.3 architecture */ 780 #define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) 781 782 static inline u8 etm_devarch_to_arch(u32 devarch) 783 { 784 return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch), 785 ETM_DEVARCH_REVISION(devarch)); 786 } 787 788 static inline u8 etm_trcidr_to_arch(u32 trcidr1) 789 { 790 return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), 791 ETM_TRCIDR1_ARCH_MINOR(trcidr1)); 792 } 793 794 enum etm_impdef_type { 795 ETM4_IMPDEF_HISI_CORE_COMMIT, 796 ETM4_IMPDEF_FEATURE_MAX, 797 }; 798 799 /** 800 * struct etmv4_config - configuration information related to an ETMv4 801 * @mode: Controls various modes supported by this ETM. 802 * @pe_sel: Controls which PE to trace. 803 * @cfg: Controls the tracing options. 804 * @eventctrl0: Controls the tracing of arbitrary events. 805 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. 806 * @stallctl: If functionality that prevents trace unit buffer overflows 807 * is available. 808 * @ts_ctrl: Controls the insertion of global timestamps in the 809 * trace streams. 810 * @syncfreq: Controls how often trace synchronization requests occur. 811 * the TRCCCCTLR register. 812 * @ccctlr: Sets the threshold value for cycle counting. 813 * @vinst_ctrl: Controls instruction trace filtering. 814 * @viiectlr: Set or read, the address range comparators. 815 * @vissctlr: Set, or read, the single address comparators that control the 816 * ViewInst start-stop logic. 817 * @vipcssctlr: Set, or read, which PE comparator inputs can control the 818 * ViewInst start-stop logic. 819 * @seq_idx: Sequencor index selector. 820 * @seq_ctrl: Control for the sequencer state transition control register. 821 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. 822 * @seq_state: Set, or read the sequencer state. 823 * @cntr_idx: Counter index seletor. 824 * @cntrldvr: Sets or returns the reload count value for a counter. 825 * @cntr_ctrl: Controls the operation of a counter. 826 * @cntr_val: Sets or returns the value for a counter. 827 * @res_idx: Resource index selector. 828 * @res_ctrl: Controls the selection of the resources in the trace unit. 829 * @ss_idx: Single-shot index selector. 830 * @ss_ctrl: Controls the corresponding single-shot comparator resource. 831 * @ss_status: The status of the corresponding single-shot comparator. 832 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. 833 * @addr_idx: Address comparator index selector. 834 * @addr_val: Value for address comparator. 835 * @addr_acc: Address comparator access type. 836 * @addr_type: Current status of the comparator register. 837 * @ctxid_idx: Context ID index selector. 838 * @ctxid_pid: Value of the context ID comparator. 839 * @ctxid_mask0:Context ID comparator mask for comparator 0-3. 840 * @ctxid_mask1:Context ID comparator mask for comparator 4-7. 841 * @vmid_idx: VM ID index selector. 842 * @vmid_val: Value of the VM ID comparator. 843 * @vmid_mask0: VM ID comparator mask for comparator 0-3. 844 * @vmid_mask1: VM ID comparator mask for comparator 4-7. 845 * @ext_inp: External input selection. 846 * @s_ex_level: Secure ELs where tracing is supported. 847 */ 848 struct etmv4_config { 849 u32 mode; 850 u32 pe_sel; 851 u32 cfg; 852 u32 eventctrl0; 853 u32 eventctrl1; 854 u32 stall_ctrl; 855 u32 ts_ctrl; 856 u32 syncfreq; 857 u32 ccctlr; 858 u32 bb_ctrl; 859 u32 vinst_ctrl; 860 u32 viiectlr; 861 u32 vissctlr; 862 u32 vipcssctlr; 863 u8 seq_idx; 864 u32 seq_ctrl[ETM_MAX_SEQ_STATES]; 865 u32 seq_rst; 866 u32 seq_state; 867 u8 cntr_idx; 868 u32 cntrldvr[ETMv4_MAX_CNTR]; 869 u32 cntr_ctrl[ETMv4_MAX_CNTR]; 870 u32 cntr_val[ETMv4_MAX_CNTR]; 871 u8 res_idx; 872 u32 res_ctrl[ETM_MAX_RES_SEL]; 873 u8 ss_idx; 874 u32 ss_ctrl[ETM_MAX_SS_CMP]; 875 u32 ss_status[ETM_MAX_SS_CMP]; 876 u32 ss_pe_cmp[ETM_MAX_SS_CMP]; 877 u8 addr_idx; 878 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; 879 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; 880 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; 881 u8 ctxid_idx; 882 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP]; 883 u32 ctxid_mask0; 884 u32 ctxid_mask1; 885 u8 vmid_idx; 886 u64 vmid_val[ETM_MAX_VMID_CMP]; 887 u32 vmid_mask0; 888 u32 vmid_mask1; 889 u32 ext_inp; 890 u8 s_ex_level; 891 }; 892 893 /** 894 * struct etm4_save_state - state to be preserved when ETM is without power 895 */ 896 struct etmv4_save_state { 897 u32 trcprgctlr; 898 u32 trcprocselr; 899 u32 trcconfigr; 900 u32 trcauxctlr; 901 u32 trceventctl0r; 902 u32 trceventctl1r; 903 u32 trcstallctlr; 904 u32 trctsctlr; 905 u32 trcsyncpr; 906 u32 trcccctlr; 907 u32 trcbbctlr; 908 u32 trctraceidr; 909 u32 trcqctlr; 910 911 u32 trcvictlr; 912 u32 trcviiectlr; 913 u32 trcvissctlr; 914 u32 trcvipcssctlr; 915 u32 trcvdctlr; 916 u32 trcvdsacctlr; 917 u32 trcvdarcctlr; 918 919 u32 trcseqevr[ETM_MAX_SEQ_STATES]; 920 u32 trcseqrstevr; 921 u32 trcseqstr; 922 u32 trcextinselr; 923 u32 trccntrldvr[ETMv4_MAX_CNTR]; 924 u32 trccntctlr[ETMv4_MAX_CNTR]; 925 u32 trccntvr[ETMv4_MAX_CNTR]; 926 927 u32 trcrsctlr[ETM_MAX_RES_SEL]; 928 929 u32 trcssccr[ETM_MAX_SS_CMP]; 930 u32 trcsscsr[ETM_MAX_SS_CMP]; 931 u32 trcsspcicr[ETM_MAX_SS_CMP]; 932 933 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP]; 934 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP]; 935 u64 trccidcvr[ETMv4_MAX_CTXID_CMP]; 936 u64 trcvmidcvr[ETM_MAX_VMID_CMP]; 937 u32 trccidcctlr0; 938 u32 trccidcctlr1; 939 u32 trcvmidcctlr0; 940 u32 trcvmidcctlr1; 941 942 u32 trcclaimset; 943 944 u32 cntr_val[ETMv4_MAX_CNTR]; 945 u32 seq_state; 946 u32 vinst_ctrl; 947 u32 ss_status[ETM_MAX_SS_CMP]; 948 949 u32 trcpdcr; 950 }; 951 952 /** 953 * struct etm4_drvdata - specifics associated to an ETM component 954 * @base: Memory mapped base address for this component. 955 * @csdev: Component vitals needed by the framework. 956 * @spinlock: Only one at a time pls. 957 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. 958 * @cpu: The cpu this component is affined to. 959 * @arch: ETM architecture version. 960 * @nr_pe: The number of processing entity available for tracing. 961 * @nr_pe_cmp: The number of processing entity comparator inputs that are 962 * available for tracing. 963 * @nr_addr_cmp:Number of pairs of address comparators available 964 * as found in ETMIDR4 0-3. 965 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. 966 * @nr_ext_inp: Number of external input. 967 * @numcidc: Number of contextID comparators. 968 * @numvmidc: Number of VMID comparators. 969 * @nrseqstate: The number of sequencer states that are implemented. 970 * @nr_event: Indicates how many events the trace unit support. 971 * @nr_resource:The number of resource selection pairs available for tracing. 972 * @nr_ss_cmp: Number of single-shot comparator controls that are available. 973 * @trcid: value of the current ID for this component. 974 * @trcid_size: Indicates the trace ID width. 975 * @ts_size: Global timestamp size field. 976 * @ctxid_size: Size of the context ID field to consider. 977 * @vmid_size: Size of the VM ID comparator to consider. 978 * @ccsize: Indicates the size of the cycle counter in bits. 979 * @ccitmin: minimum value that can be programmed in 980 * @s_ex_level: In secure state, indicates whether instruction tracing is 981 * supported for the corresponding Exception level. 982 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is 983 * supported for the corresponding Exception level. 984 * @sticky_enable: true if ETM base configuration has been done. 985 * @boot_enable:True if we should start tracing at boot time. 986 * @os_unlock: True if access to management registers is allowed. 987 * @instrp0: Tracing of load and store instructions 988 * as P0 elements is supported. 989 * @trcbb: Indicates if the trace unit supports branch broadcast tracing. 990 * @trccond: If the trace unit supports conditional 991 * instruction tracing. 992 * @retstack: Indicates if the implementation supports a return stack. 993 * @trccci: Indicates if the trace unit supports cycle counting 994 * for instruction. 995 * @q_support: Q element support characteristics. 996 * @trc_error: Whether a trace unit can trace a system 997 * error exception. 998 * @syncpr: Indicates if an implementation has a fixed 999 * synchronization period. 1000 * @stall_ctrl: Enables trace unit functionality that prevents trace 1001 * unit buffer overflows. 1002 * @sysstall: Does the system support stall control of the PE? 1003 * @nooverflow: Indicate if overflow prevention is supported. 1004 * @atbtrig: If the implementation can support ATB triggers 1005 * @lpoverride: If the implementation can support low-power state over. 1006 * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that 1007 * allows tracing at all ELs. We don't want to compute this 1008 * at runtime, due to the additional setting of TRFCR_CX when 1009 * in EL2. Otherwise, 0. 1010 * @config: structure holding configuration parameters. 1011 * @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event. 1012 * @save_state: State to be preserved across power loss 1013 * @state_needs_restore: True when there is context to restore after PM exit 1014 * @skip_power_up: Indicates if an implementation can skip powering up 1015 * the trace unit. 1016 * @arch_features: Bitmap of arch features of etmv4 devices. 1017 */ 1018 struct etmv4_drvdata { 1019 void __iomem *base; 1020 struct coresight_device *csdev; 1021 spinlock_t spinlock; 1022 local_t mode; 1023 int cpu; 1024 u8 arch; 1025 u8 nr_pe; 1026 u8 nr_pe_cmp; 1027 u8 nr_addr_cmp; 1028 u8 nr_cntr; 1029 u8 nr_ext_inp; 1030 u8 numcidc; 1031 u8 numvmidc; 1032 u8 nrseqstate; 1033 u8 nr_event; 1034 u8 nr_resource; 1035 u8 nr_ss_cmp; 1036 u8 trcid; 1037 u8 trcid_size; 1038 u8 ts_size; 1039 u8 ctxid_size; 1040 u8 vmid_size; 1041 u8 ccsize; 1042 u8 ccitmin; 1043 u8 s_ex_level; 1044 u8 ns_ex_level; 1045 u8 q_support; 1046 u8 os_lock_model; 1047 bool sticky_enable; 1048 bool boot_enable; 1049 bool os_unlock; 1050 bool instrp0; 1051 bool trcbb; 1052 bool trccond; 1053 bool retstack; 1054 bool trccci; 1055 bool trc_error; 1056 bool syncpr; 1057 bool stallctl; 1058 bool sysstall; 1059 bool nooverflow; 1060 bool atbtrig; 1061 bool lpoverride; 1062 u64 trfcr; 1063 struct etmv4_config config; 1064 u64 save_trfcr; 1065 struct etmv4_save_state *save_state; 1066 bool state_needs_restore; 1067 bool skip_power_up; 1068 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); 1069 }; 1070 1071 /* Address comparator access types */ 1072 enum etm_addr_acctype { 1073 TRCACATRn_TYPE_ADDR, 1074 TRCACATRn_TYPE_DATA_LOAD_ADDR, 1075 TRCACATRn_TYPE_DATA_STORE_ADDR, 1076 TRCACATRn_TYPE_DATA_LOAD_STORE_ADDR, 1077 }; 1078 1079 /* Address comparator context types */ 1080 enum etm_addr_ctxtype { 1081 ETM_CTX_NONE, 1082 ETM_CTX_CTXID, 1083 ETM_CTX_VMID, 1084 ETM_CTX_CTXID_VMID, 1085 }; 1086 1087 extern const struct attribute_group *coresight_etmv4_groups[]; 1088 void etm4_config_trace_mode(struct etmv4_config *config); 1089 1090 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); 1091 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); 1092 1093 static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) 1094 { 1095 return drvdata->arch >= ETM_ARCH_ETE; 1096 } 1097 #endif 1098