1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _CORESIGHT_CORESIGHT_ETM_H
7 #define _CORESIGHT_CORESIGHT_ETM_H
8 
9 #include <asm/local.h>
10 #include <linux/spinlock.h>
11 #include "coresight-priv.h"
12 
13 /*
14  * Device registers:
15  * 0x000 - 0x2FC: Trace		registers
16  * 0x300 - 0x314: Management	registers
17  * 0x318 - 0xEFC: Trace		registers
18  * 0xF00: Management		registers
19  * 0xFA0 - 0xFA4: Trace		registers
20  * 0xFA8 - 0xFFC: Management	registers
21  */
22 /* Trace registers (0x000-0x2FC) */
23 /* Main control and configuration registers */
24 #define TRCPRGCTLR			0x004
25 #define TRCPROCSELR			0x008
26 #define TRCSTATR			0x00C
27 #define TRCCONFIGR			0x010
28 #define TRCAUXCTLR			0x018
29 #define TRCEVENTCTL0R			0x020
30 #define TRCEVENTCTL1R			0x024
31 #define TRCSTALLCTLR			0x02C
32 #define TRCTSCTLR			0x030
33 #define TRCSYNCPR			0x034
34 #define TRCCCCTLR			0x038
35 #define TRCBBCTLR			0x03C
36 #define TRCTRACEIDR			0x040
37 #define TRCQCTLR			0x044
38 /* Filtering control registers */
39 #define TRCVICTLR			0x080
40 #define TRCVIIECTLR			0x084
41 #define TRCVISSCTLR			0x088
42 #define TRCVIPCSSCTLR			0x08C
43 #define TRCVDCTLR			0x0A0
44 #define TRCVDSACCTLR			0x0A4
45 #define TRCVDARCCTLR			0x0A8
46 /* Derived resources registers */
47 #define TRCSEQEVRn(n)			(0x100 + (n * 4))
48 #define TRCSEQRSTEVR			0x118
49 #define TRCSEQSTR			0x11C
50 #define TRCEXTINSELR			0x120
51 #define TRCCNTRLDVRn(n)			(0x140 + (n * 4))
52 #define TRCCNTCTLRn(n)			(0x150 + (n * 4))
53 #define TRCCNTVRn(n)			(0x160 + (n * 4))
54 /* ID registers */
55 #define TRCIDR8				0x180
56 #define TRCIDR9				0x184
57 #define TRCIDR10			0x188
58 #define TRCIDR11			0x18C
59 #define TRCIDR12			0x190
60 #define TRCIDR13			0x194
61 #define TRCIMSPEC0			0x1C0
62 #define TRCIMSPECn(n)			(0x1C0 + (n * 4))
63 #define TRCIDR0				0x1E0
64 #define TRCIDR1				0x1E4
65 #define TRCIDR2				0x1E8
66 #define TRCIDR3				0x1EC
67 #define TRCIDR4				0x1F0
68 #define TRCIDR5				0x1F4
69 #define TRCIDR6				0x1F8
70 #define TRCIDR7				0x1FC
71 /* Resource selection registers */
72 #define TRCRSCTLRn(n)			(0x200 + (n * 4))
73 /* Single-shot comparator registers */
74 #define TRCSSCCRn(n)			(0x280 + (n * 4))
75 #define TRCSSCSRn(n)			(0x2A0 + (n * 4))
76 #define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
77 /* Management registers (0x300-0x314) */
78 #define TRCOSLAR			0x300
79 #define TRCOSLSR			0x304
80 #define TRCPDCR				0x310
81 #define TRCPDSR				0x314
82 /* Trace registers (0x318-0xEFC) */
83 /* Comparator registers */
84 #define TRCACVRn(n)			(0x400 + (n * 8))
85 #define TRCACATRn(n)			(0x480 + (n * 8))
86 #define TRCDVCVRn(n)			(0x500 + (n * 16))
87 #define TRCDVCMRn(n)			(0x580 + (n * 16))
88 #define TRCCIDCVRn(n)			(0x600 + (n * 8))
89 #define TRCVMIDCVRn(n)			(0x640 + (n * 8))
90 #define TRCCIDCCTLR0			0x680
91 #define TRCCIDCCTLR1			0x684
92 #define TRCVMIDCCTLR0			0x688
93 #define TRCVMIDCCTLR1			0x68C
94 /* Management register (0xF00) */
95 /* Integration control registers */
96 #define TRCITCTRL			0xF00
97 /* Trace registers (0xFA0-0xFA4) */
98 /* Claim tag registers */
99 #define TRCCLAIMSET			0xFA0
100 #define TRCCLAIMCLR			0xFA4
101 /* Management registers (0xFA8-0xFFC) */
102 #define TRCDEVAFF0			0xFA8
103 #define TRCDEVAFF1			0xFAC
104 #define TRCLAR				0xFB0
105 #define TRCLSR				0xFB4
106 #define TRCAUTHSTATUS			0xFB8
107 #define TRCDEVARCH			0xFBC
108 #define TRCDEVID			0xFC8
109 #define TRCDEVTYPE			0xFCC
110 #define TRCPIDR4			0xFD0
111 #define TRCPIDR5			0xFD4
112 #define TRCPIDR6			0xFD8
113 #define TRCPIDR7			0xFDC
114 #define TRCPIDR0			0xFE0
115 #define TRCPIDR1			0xFE4
116 #define TRCPIDR2			0xFE8
117 #define TRCPIDR3			0xFEC
118 #define TRCCIDR0			0xFF0
119 #define TRCCIDR1			0xFF4
120 #define TRCCIDR2			0xFF8
121 #define TRCCIDR3			0xFFC
122 
123 /* ETMv4 resources */
124 #define ETM_MAX_NR_PE			8
125 #define ETMv4_MAX_CNTR			4
126 #define ETM_MAX_SEQ_STATES		4
127 #define ETM_MAX_EXT_INP_SEL		4
128 #define ETM_MAX_EXT_INP			256
129 #define ETM_MAX_EXT_OUT			4
130 #define ETM_MAX_SINGLE_ADDR_CMP		16
131 #define ETM_MAX_ADDR_RANGE_CMP		(ETM_MAX_SINGLE_ADDR_CMP / 2)
132 #define ETM_MAX_DATA_VAL_CMP		8
133 #define ETMv4_MAX_CTXID_CMP		8
134 #define ETM_MAX_VMID_CMP		8
135 #define ETM_MAX_PE_CMP			8
136 #define ETM_MAX_RES_SEL			16
137 #define ETM_MAX_SS_CMP			8
138 
139 #define ETM_ARCH_V4			0x40
140 #define ETMv4_SYNC_MASK			0x1F
141 #define ETM_CYC_THRESHOLD_MASK		0xFFF
142 #define ETM_CYC_THRESHOLD_DEFAULT       0x100
143 #define ETMv4_EVENT_MASK		0xFF
144 #define ETM_CNTR_MAX_VAL		0xFFFF
145 #define ETM_TRACEID_MASK		0x3f
146 
147 /* ETMv4 programming modes */
148 #define ETM_MODE_EXCLUDE		BIT(0)
149 #define ETM_MODE_LOAD			BIT(1)
150 #define ETM_MODE_STORE			BIT(2)
151 #define ETM_MODE_LOAD_STORE		BIT(3)
152 #define ETM_MODE_BB			BIT(4)
153 #define ETMv4_MODE_CYCACC		BIT(5)
154 #define ETMv4_MODE_CTXID		BIT(6)
155 #define ETM_MODE_VMID			BIT(7)
156 #define ETM_MODE_COND(val)		BMVAL(val, 8, 10)
157 #define ETMv4_MODE_TIMESTAMP		BIT(11)
158 #define ETM_MODE_RETURNSTACK		BIT(12)
159 #define ETM_MODE_QELEM(val)		BMVAL(val, 13, 14)
160 #define ETM_MODE_DATA_TRACE_ADDR	BIT(15)
161 #define ETM_MODE_DATA_TRACE_VAL		BIT(16)
162 #define ETM_MODE_ISTALL			BIT(17)
163 #define ETM_MODE_DSTALL			BIT(18)
164 #define ETM_MODE_ATB_TRIGGER		BIT(19)
165 #define ETM_MODE_LPOVERRIDE		BIT(20)
166 #define ETM_MODE_ISTALL_EN		BIT(21)
167 #define ETM_MODE_DSTALL_EN		BIT(22)
168 #define ETM_MODE_INSTPRIO		BIT(23)
169 #define ETM_MODE_NOOVERFLOW		BIT(24)
170 #define ETM_MODE_TRACE_RESET		BIT(25)
171 #define ETM_MODE_TRACE_ERR		BIT(26)
172 #define ETM_MODE_VIEWINST_STARTSTOP	BIT(27)
173 #define ETMv4_MODE_ALL			(GENMASK(27, 0) | \
174 					 ETM_MODE_EXCL_KERN | \
175 					 ETM_MODE_EXCL_USER)
176 
177 #define TRCSTATR_IDLE_BIT		0
178 #define TRCSTATR_PMSTABLE_BIT		1
179 #define ETM_DEFAULT_ADDR_COMP		0
180 
181 /* PowerDown Control Register bits */
182 #define TRCPDCR_PU			BIT(3)
183 
184 /* secure state access levels - TRCACATRn */
185 #define ETM_EXLEVEL_S_APP		BIT(8)
186 #define ETM_EXLEVEL_S_OS		BIT(9)
187 #define ETM_EXLEVEL_S_HYP		BIT(10)
188 #define ETM_EXLEVEL_S_MON		BIT(11)
189 /* non-secure state access levels - TRCACATRn */
190 #define ETM_EXLEVEL_NS_APP		BIT(12)
191 #define ETM_EXLEVEL_NS_OS		BIT(13)
192 #define ETM_EXLEVEL_NS_HYP		BIT(14)
193 #define ETM_EXLEVEL_NS_NA		BIT(15)
194 
195 /* secure / non secure masks - TRCVICTLR, IDR3 */
196 #define ETM_EXLEVEL_S_VICTLR_MASK	GENMASK(19, 16)
197 /* NS MON (EL3) mode never implemented */
198 #define ETM_EXLEVEL_NS_VICTLR_MASK	GENMASK(22, 20)
199 
200 /**
201  * struct etmv4_config - configuration information related to an ETMv4
202  * @mode:	Controls various modes supported by this ETM.
203  * @pe_sel:	Controls which PE to trace.
204  * @cfg:	Controls the tracing options.
205  * @eventctrl0: Controls the tracing of arbitrary events.
206  * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
207  * @stallctl:	If functionality that prevents trace unit buffer overflows
208  *		is available.
209  * @ts_ctrl:	Controls the insertion of global timestamps in the
210  *		trace streams.
211  * @syncfreq:	Controls how often trace synchronization requests occur.
212  *		the TRCCCCTLR register.
213  * @ccctlr:	Sets the threshold value for cycle counting.
214  * @vinst_ctrl:	Controls instruction trace filtering.
215  * @viiectlr:	Set or read, the address range comparators.
216  * @vissctlr:	Set, or read, the single address comparators that control the
217  *		ViewInst start-stop logic.
218  * @vipcssctlr:	Set, or read, which PE comparator inputs can control the
219  *		ViewInst start-stop logic.
220  * @seq_idx:	Sequencor index selector.
221  * @seq_ctrl:	Control for the sequencer state transition control register.
222  * @seq_rst:	Moves the sequencer to state 0 when a programmed event occurs.
223  * @seq_state:	Set, or read the sequencer state.
224  * @cntr_idx:	Counter index seletor.
225  * @cntrldvr:	Sets or returns the reload count value for a counter.
226  * @cntr_ctrl:	Controls the operation of a counter.
227  * @cntr_val:	Sets or returns the value for a counter.
228  * @res_idx:	Resource index selector.
229  * @res_ctrl:	Controls the selection of the resources in the trace unit.
230  * @ss_idx:	Single-shot index selector.
231  * @ss_ctrl:	Controls the corresponding single-shot comparator resource.
232  * @ss_status:	The status of the corresponding single-shot comparator.
233  * @ss_pe_cmp:	Selects the PE comparator inputs for Single-shot control.
234  * @addr_idx:	Address comparator index selector.
235  * @addr_val:	Value for address comparator.
236  * @addr_acc:	Address comparator access type.
237  * @addr_type:	Current status of the comparator register.
238  * @ctxid_idx:	Context ID index selector.
239  * @ctxid_pid:	Value of the context ID comparator.
240  * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
241  * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
242  * @vmid_idx:	VM ID index selector.
243  * @vmid_val:	Value of the VM ID comparator.
244  * @vmid_mask0:	VM ID comparator mask for comparator 0-3.
245  * @vmid_mask1:	VM ID comparator mask for comparator 4-7.
246  * @ext_inp:	External input selection.
247  * @arch:	ETM architecture version (for arch dependent config).
248  */
249 struct etmv4_config {
250 	u32				mode;
251 	u32				pe_sel;
252 	u32				cfg;
253 	u32				eventctrl0;
254 	u32				eventctrl1;
255 	u32				stall_ctrl;
256 	u32				ts_ctrl;
257 	u32				syncfreq;
258 	u32				ccctlr;
259 	u32				bb_ctrl;
260 	u32				vinst_ctrl;
261 	u32				viiectlr;
262 	u32				vissctlr;
263 	u32				vipcssctlr;
264 	u8				seq_idx;
265 	u32				seq_ctrl[ETM_MAX_SEQ_STATES];
266 	u32				seq_rst;
267 	u32				seq_state;
268 	u8				cntr_idx;
269 	u32				cntrldvr[ETMv4_MAX_CNTR];
270 	u32				cntr_ctrl[ETMv4_MAX_CNTR];
271 	u32				cntr_val[ETMv4_MAX_CNTR];
272 	u8				res_idx;
273 	u32				res_ctrl[ETM_MAX_RES_SEL];
274 	u8				ss_idx;
275 	u32				ss_ctrl[ETM_MAX_SS_CMP];
276 	u32				ss_status[ETM_MAX_SS_CMP];
277 	u32				ss_pe_cmp[ETM_MAX_SS_CMP];
278 	u8				addr_idx;
279 	u64				addr_val[ETM_MAX_SINGLE_ADDR_CMP];
280 	u64				addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
281 	u8				addr_type[ETM_MAX_SINGLE_ADDR_CMP];
282 	u8				ctxid_idx;
283 	u64				ctxid_pid[ETMv4_MAX_CTXID_CMP];
284 	u32				ctxid_mask0;
285 	u32				ctxid_mask1;
286 	u8				vmid_idx;
287 	u64				vmid_val[ETM_MAX_VMID_CMP];
288 	u32				vmid_mask0;
289 	u32				vmid_mask1;
290 	u32				ext_inp;
291 	u8				arch;
292 };
293 
294 /**
295  * struct etm4_save_state - state to be preserved when ETM is without power
296  */
297 struct etmv4_save_state {
298 	u32	trcprgctlr;
299 	u32	trcprocselr;
300 	u32	trcconfigr;
301 	u32	trcauxctlr;
302 	u32	trceventctl0r;
303 	u32	trceventctl1r;
304 	u32	trcstallctlr;
305 	u32	trctsctlr;
306 	u32	trcsyncpr;
307 	u32	trcccctlr;
308 	u32	trcbbctlr;
309 	u32	trctraceidr;
310 	u32	trcqctlr;
311 
312 	u32	trcvictlr;
313 	u32	trcviiectlr;
314 	u32	trcvissctlr;
315 	u32	trcvipcssctlr;
316 	u32	trcvdctlr;
317 	u32	trcvdsacctlr;
318 	u32	trcvdarcctlr;
319 
320 	u32	trcseqevr[ETM_MAX_SEQ_STATES];
321 	u32	trcseqrstevr;
322 	u32	trcseqstr;
323 	u32	trcextinselr;
324 	u32	trccntrldvr[ETMv4_MAX_CNTR];
325 	u32	trccntctlr[ETMv4_MAX_CNTR];
326 	u32	trccntvr[ETMv4_MAX_CNTR];
327 
328 	u32	trcrsctlr[ETM_MAX_RES_SEL * 2];
329 
330 	u32	trcssccr[ETM_MAX_SS_CMP];
331 	u32	trcsscsr[ETM_MAX_SS_CMP];
332 	u32	trcsspcicr[ETM_MAX_SS_CMP];
333 
334 	u64	trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
335 	u64	trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
336 	u64	trccidcvr[ETMv4_MAX_CTXID_CMP];
337 	u32	trcvmidcvr[ETM_MAX_VMID_CMP];
338 	u32	trccidcctlr0;
339 	u32	trccidcctlr1;
340 	u32	trcvmidcctlr0;
341 	u32	trcvmidcctlr1;
342 
343 	u32	trcclaimset;
344 
345 	u32	cntr_val[ETMv4_MAX_CNTR];
346 	u32	seq_state;
347 	u32	vinst_ctrl;
348 	u32	ss_status[ETM_MAX_SS_CMP];
349 
350 	u32	trcpdcr;
351 };
352 
353 /**
354  * struct etm4_drvdata - specifics associated to an ETM component
355  * @base:       Memory mapped base address for this component.
356  * @csdev:      Component vitals needed by the framework.
357  * @spinlock:   Only one at a time pls.
358  * @mode:	This tracer's mode, i.e sysFS, Perf or disabled.
359  * @cpu:        The cpu this component is affined to.
360  * @arch:       ETM version number.
361  * @nr_pe:	The number of processing entity available for tracing.
362  * @nr_pe_cmp:	The number of processing entity comparator inputs that are
363  *		available for tracing.
364  * @nr_addr_cmp:Number of pairs of address comparators available
365  *		as found in ETMIDR4 0-3.
366  * @nr_cntr:    Number of counters as found in ETMIDR5 bit 28-30.
367  * @nr_ext_inp: Number of external input.
368  * @numcidc:	Number of contextID comparators.
369  * @numvmidc:	Number of VMID comparators.
370  * @nrseqstate: The number of sequencer states that are implemented.
371  * @nr_event:	Indicates how many events the trace unit support.
372  * @nr_resource:The number of resource selection pairs available for tracing.
373  * @nr_ss_cmp:	Number of single-shot comparator controls that are available.
374  * @trcid:	value of the current ID for this component.
375  * @trcid_size: Indicates the trace ID width.
376  * @ts_size:	Global timestamp size field.
377  * @ctxid_size:	Size of the context ID field to consider.
378  * @vmid_size:	Size of the VM ID comparator to consider.
379  * @ccsize:	Indicates the size of the cycle counter in bits.
380  * @ccitmin:	minimum value that can be programmed in
381  * @s_ex_level:	In secure state, indicates whether instruction tracing is
382  *		supported for the corresponding Exception level.
383  * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
384  *		supported for the corresponding Exception level.
385  * @sticky_enable: true if ETM base configuration has been done.
386  * @boot_enable:True if we should start tracing at boot time.
387  * @os_unlock:  True if access to management registers is allowed.
388  * @instrp0:	Tracing of load and store instructions
389  *		as P0 elements is supported.
390  * @trcbb:	Indicates if the trace unit supports branch broadcast tracing.
391  * @trccond:	If the trace unit supports conditional
392  *		instruction tracing.
393  * @retstack:	Indicates if the implementation supports a return stack.
394  * @trccci:	Indicates if the trace unit supports cycle counting
395  *		for instruction.
396  * @q_support:	Q element support characteristics.
397  * @trc_error:	Whether a trace unit can trace a system
398  *		error exception.
399  * @syncpr:	Indicates if an implementation has a fixed
400  *		synchronization period.
401  * @stall_ctrl:	Enables trace unit functionality that prevents trace
402  *		unit buffer overflows.
403  * @sysstall:	Does the system support stall control of the PE?
404  * @nooverflow:	Indicate if overflow prevention is supported.
405  * @atbtrig:	If the implementation can support ATB triggers
406  * @lpoverride:	If the implementation can support low-power state over.
407  * @config:	structure holding configuration parameters.
408  * @save_state:	State to be preserved across power loss
409  * @state_needs_restore: True when there is context to restore after PM exit
410  */
411 struct etmv4_drvdata {
412 	void __iomem			*base;
413 	struct coresight_device		*csdev;
414 	spinlock_t			spinlock;
415 	local_t				mode;
416 	int				cpu;
417 	u8				arch;
418 	u8				nr_pe;
419 	u8				nr_pe_cmp;
420 	u8				nr_addr_cmp;
421 	u8				nr_cntr;
422 	u8				nr_ext_inp;
423 	u8				numcidc;
424 	u8				numvmidc;
425 	u8				nrseqstate;
426 	u8				nr_event;
427 	u8				nr_resource;
428 	u8				nr_ss_cmp;
429 	u8				trcid;
430 	u8				trcid_size;
431 	u8				ts_size;
432 	u8				ctxid_size;
433 	u8				vmid_size;
434 	u8				ccsize;
435 	u8				ccitmin;
436 	u8				s_ex_level;
437 	u8				ns_ex_level;
438 	u8				q_support;
439 	bool				sticky_enable;
440 	bool				boot_enable;
441 	bool				os_unlock;
442 	bool				instrp0;
443 	bool				trcbb;
444 	bool				trccond;
445 	bool				retstack;
446 	bool				trccci;
447 	bool				trc_error;
448 	bool				syncpr;
449 	bool				stallctl;
450 	bool				sysstall;
451 	bool				nooverflow;
452 	bool				atbtrig;
453 	bool				lpoverride;
454 	struct etmv4_config		config;
455 	struct etmv4_save_state		*save_state;
456 	bool				state_needs_restore;
457 };
458 
459 /* Address comparator access types */
460 enum etm_addr_acctype {
461 	ETM_INSTR_ADDR,
462 	ETM_DATA_LOAD_ADDR,
463 	ETM_DATA_STORE_ADDR,
464 	ETM_DATA_LOAD_STORE_ADDR,
465 };
466 
467 /* Address comparator context types */
468 enum etm_addr_ctxtype {
469 	ETM_CTX_NONE,
470 	ETM_CTX_CTXID,
471 	ETM_CTX_VMID,
472 	ETM_CTX_CTXID_VMID,
473 };
474 
475 extern const struct attribute_group *coresight_etmv4_groups[];
476 void etm4_config_trace_mode(struct etmv4_config *config);
477 #endif
478