1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef _CORESIGHT_CORESIGHT_ETM_H 7 #define _CORESIGHT_CORESIGHT_ETM_H 8 9 #include <asm/local.h> 10 #include <linux/spinlock.h> 11 #include <linux/types.h> 12 #include "coresight-priv.h" 13 14 /* 15 * Device registers: 16 * 0x000 - 0x2FC: Trace registers 17 * 0x300 - 0x314: Management registers 18 * 0x318 - 0xEFC: Trace registers 19 * 0xF00: Management registers 20 * 0xFA0 - 0xFA4: Trace registers 21 * 0xFA8 - 0xFFC: Management registers 22 */ 23 /* Trace registers (0x000-0x2FC) */ 24 /* Main control and configuration registers */ 25 #define TRCPRGCTLR 0x004 26 #define TRCPROCSELR 0x008 27 #define TRCSTATR 0x00C 28 #define TRCCONFIGR 0x010 29 #define TRCAUXCTLR 0x018 30 #define TRCEVENTCTL0R 0x020 31 #define TRCEVENTCTL1R 0x024 32 #define TRCSTALLCTLR 0x02C 33 #define TRCTSCTLR 0x030 34 #define TRCSYNCPR 0x034 35 #define TRCCCCTLR 0x038 36 #define TRCBBCTLR 0x03C 37 #define TRCTRACEIDR 0x040 38 #define TRCQCTLR 0x044 39 /* Filtering control registers */ 40 #define TRCVICTLR 0x080 41 #define TRCVIIECTLR 0x084 42 #define TRCVISSCTLR 0x088 43 #define TRCVIPCSSCTLR 0x08C 44 #define TRCVDCTLR 0x0A0 45 #define TRCVDSACCTLR 0x0A4 46 #define TRCVDARCCTLR 0x0A8 47 /* Derived resources registers */ 48 #define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ 49 #define TRCSEQRSTEVR 0x118 50 #define TRCSEQSTR 0x11C 51 #define TRCEXTINSELR 0x120 52 #define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ 53 #define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ 54 #define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ 55 /* ID registers */ 56 #define TRCIDR8 0x180 57 #define TRCIDR9 0x184 58 #define TRCIDR10 0x188 59 #define TRCIDR11 0x18C 60 #define TRCIDR12 0x190 61 #define TRCIDR13 0x194 62 #define TRCIMSPEC0 0x1C0 63 #define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ 64 #define TRCIDR0 0x1E0 65 #define TRCIDR1 0x1E4 66 #define TRCIDR2 0x1E8 67 #define TRCIDR3 0x1EC 68 #define TRCIDR4 0x1F0 69 #define TRCIDR5 0x1F4 70 #define TRCIDR6 0x1F8 71 #define TRCIDR7 0x1FC 72 /* 73 * Resource selection registers, n = 2-31. 74 * First pair (regs 0, 1) is always present and is reserved. 75 */ 76 #define TRCRSCTLRn(n) (0x200 + (n * 4)) 77 /* Single-shot comparator registers, n = 0-7 */ 78 #define TRCSSCCRn(n) (0x280 + (n * 4)) 79 #define TRCSSCSRn(n) (0x2A0 + (n * 4)) 80 #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) 81 /* Management registers (0x300-0x314) */ 82 #define TRCOSLAR 0x300 83 #define TRCOSLSR 0x304 84 #define TRCPDCR 0x310 85 #define TRCPDSR 0x314 86 /* Trace registers (0x318-0xEFC) */ 87 /* Address Comparator registers n = 0-15 */ 88 #define TRCACVRn(n) (0x400 + (n * 8)) 89 #define TRCACATRn(n) (0x480 + (n * 8)) 90 /* Data Value Comparator Value registers, n = 0-7 */ 91 #define TRCDVCVRn(n) (0x500 + (n * 16)) 92 #define TRCDVCMRn(n) (0x580 + (n * 16)) 93 /* ContextID/Virtual ContextID comparators, n = 0-7 */ 94 #define TRCCIDCVRn(n) (0x600 + (n * 8)) 95 #define TRCVMIDCVRn(n) (0x640 + (n * 8)) 96 #define TRCCIDCCTLR0 0x680 97 #define TRCCIDCCTLR1 0x684 98 #define TRCVMIDCCTLR0 0x688 99 #define TRCVMIDCCTLR1 0x68C 100 /* Management register (0xF00) */ 101 /* Integration control registers */ 102 #define TRCITCTRL 0xF00 103 /* Trace registers (0xFA0-0xFA4) */ 104 /* Claim tag registers */ 105 #define TRCCLAIMSET 0xFA0 106 #define TRCCLAIMCLR 0xFA4 107 /* Management registers (0xFA8-0xFFC) */ 108 #define TRCDEVAFF0 0xFA8 109 #define TRCDEVAFF1 0xFAC 110 #define TRCLAR 0xFB0 111 #define TRCLSR 0xFB4 112 #define TRCAUTHSTATUS 0xFB8 113 #define TRCDEVARCH 0xFBC 114 #define TRCDEVID 0xFC8 115 #define TRCDEVTYPE 0xFCC 116 #define TRCPIDR4 0xFD0 117 #define TRCPIDR5 0xFD4 118 #define TRCPIDR6 0xFD8 119 #define TRCPIDR7 0xFDC 120 #define TRCPIDR0 0xFE0 121 #define TRCPIDR1 0xFE4 122 #define TRCPIDR2 0xFE8 123 #define TRCPIDR3 0xFEC 124 #define TRCCIDR0 0xFF0 125 #define TRCCIDR1 0xFF4 126 #define TRCCIDR2 0xFF8 127 #define TRCCIDR3 0xFFC 128 129 /* 130 * System instructions to access ETM registers. 131 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions 132 */ 133 #define ETM4x_OFFSET_TO_REG(x) ((x) >> 2) 134 135 #define ETM4x_CRn(n) (((n) >> 7) & 0x7) 136 #define ETM4x_Op2(n) (((n) >> 4) & 0x7) 137 #define ETM4x_CRm(n) ((n) & 0xf) 138 139 #include <asm/sysreg.h> 140 #define ETM4x_REG_NUM_TO_SYSREG(n) \ 141 sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n)) 142 143 #define READ_ETM4x_REG(reg) \ 144 read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg))) 145 #define WRITE_ETM4x_REG(val, reg) \ 146 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg))) 147 148 #define read_etm4x_sysreg_const_offset(offset) \ 149 READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset)) 150 151 #define write_etm4x_sysreg_const_offset(val, offset) \ 152 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset)) 153 154 #define CASE_READ(res, x) \ 155 case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; } 156 157 #define CASE_WRITE(val, x) \ 158 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; } 159 160 #define CASE_NOP(__unused, x) \ 161 case (x): /* fall through */ 162 163 /* List of registers accessible via System instructions */ 164 #define ETM_SYSREG_LIST(op, val) \ 165 CASE_##op((val), TRCPRGCTLR) \ 166 CASE_##op((val), TRCPROCSELR) \ 167 CASE_##op((val), TRCSTATR) \ 168 CASE_##op((val), TRCCONFIGR) \ 169 CASE_##op((val), TRCAUXCTLR) \ 170 CASE_##op((val), TRCEVENTCTL0R) \ 171 CASE_##op((val), TRCEVENTCTL1R) \ 172 CASE_##op((val), TRCSTALLCTLR) \ 173 CASE_##op((val), TRCTSCTLR) \ 174 CASE_##op((val), TRCSYNCPR) \ 175 CASE_##op((val), TRCCCCTLR) \ 176 CASE_##op((val), TRCBBCTLR) \ 177 CASE_##op((val), TRCTRACEIDR) \ 178 CASE_##op((val), TRCQCTLR) \ 179 CASE_##op((val), TRCVICTLR) \ 180 CASE_##op((val), TRCVIIECTLR) \ 181 CASE_##op((val), TRCVISSCTLR) \ 182 CASE_##op((val), TRCVIPCSSCTLR) \ 183 CASE_##op((val), TRCVDCTLR) \ 184 CASE_##op((val), TRCVDSACCTLR) \ 185 CASE_##op((val), TRCVDARCCTLR) \ 186 CASE_##op((val), TRCSEQEVRn(0)) \ 187 CASE_##op((val), TRCSEQEVRn(1)) \ 188 CASE_##op((val), TRCSEQEVRn(2)) \ 189 CASE_##op((val), TRCSEQRSTEVR) \ 190 CASE_##op((val), TRCSEQSTR) \ 191 CASE_##op((val), TRCEXTINSELR) \ 192 CASE_##op((val), TRCCNTRLDVRn(0)) \ 193 CASE_##op((val), TRCCNTRLDVRn(1)) \ 194 CASE_##op((val), TRCCNTRLDVRn(2)) \ 195 CASE_##op((val), TRCCNTRLDVRn(3)) \ 196 CASE_##op((val), TRCCNTCTLRn(0)) \ 197 CASE_##op((val), TRCCNTCTLRn(1)) \ 198 CASE_##op((val), TRCCNTCTLRn(2)) \ 199 CASE_##op((val), TRCCNTCTLRn(3)) \ 200 CASE_##op((val), TRCCNTVRn(0)) \ 201 CASE_##op((val), TRCCNTVRn(1)) \ 202 CASE_##op((val), TRCCNTVRn(2)) \ 203 CASE_##op((val), TRCCNTVRn(3)) \ 204 CASE_##op((val), TRCIDR8) \ 205 CASE_##op((val), TRCIDR9) \ 206 CASE_##op((val), TRCIDR10) \ 207 CASE_##op((val), TRCIDR11) \ 208 CASE_##op((val), TRCIDR12) \ 209 CASE_##op((val), TRCIDR13) \ 210 CASE_##op((val), TRCIMSPECn(0)) \ 211 CASE_##op((val), TRCIMSPECn(1)) \ 212 CASE_##op((val), TRCIMSPECn(2)) \ 213 CASE_##op((val), TRCIMSPECn(3)) \ 214 CASE_##op((val), TRCIMSPECn(4)) \ 215 CASE_##op((val), TRCIMSPECn(5)) \ 216 CASE_##op((val), TRCIMSPECn(6)) \ 217 CASE_##op((val), TRCIMSPECn(7)) \ 218 CASE_##op((val), TRCIDR0) \ 219 CASE_##op((val), TRCIDR1) \ 220 CASE_##op((val), TRCIDR2) \ 221 CASE_##op((val), TRCIDR3) \ 222 CASE_##op((val), TRCIDR4) \ 223 CASE_##op((val), TRCIDR5) \ 224 CASE_##op((val), TRCIDR6) \ 225 CASE_##op((val), TRCIDR7) \ 226 CASE_##op((val), TRCRSCTLRn(2)) \ 227 CASE_##op((val), TRCRSCTLRn(3)) \ 228 CASE_##op((val), TRCRSCTLRn(4)) \ 229 CASE_##op((val), TRCRSCTLRn(5)) \ 230 CASE_##op((val), TRCRSCTLRn(6)) \ 231 CASE_##op((val), TRCRSCTLRn(7)) \ 232 CASE_##op((val), TRCRSCTLRn(8)) \ 233 CASE_##op((val), TRCRSCTLRn(9)) \ 234 CASE_##op((val), TRCRSCTLRn(10)) \ 235 CASE_##op((val), TRCRSCTLRn(11)) \ 236 CASE_##op((val), TRCRSCTLRn(12)) \ 237 CASE_##op((val), TRCRSCTLRn(13)) \ 238 CASE_##op((val), TRCRSCTLRn(14)) \ 239 CASE_##op((val), TRCRSCTLRn(15)) \ 240 CASE_##op((val), TRCRSCTLRn(16)) \ 241 CASE_##op((val), TRCRSCTLRn(17)) \ 242 CASE_##op((val), TRCRSCTLRn(18)) \ 243 CASE_##op((val), TRCRSCTLRn(19)) \ 244 CASE_##op((val), TRCRSCTLRn(20)) \ 245 CASE_##op((val), TRCRSCTLRn(21)) \ 246 CASE_##op((val), TRCRSCTLRn(22)) \ 247 CASE_##op((val), TRCRSCTLRn(23)) \ 248 CASE_##op((val), TRCRSCTLRn(24)) \ 249 CASE_##op((val), TRCRSCTLRn(25)) \ 250 CASE_##op((val), TRCRSCTLRn(26)) \ 251 CASE_##op((val), TRCRSCTLRn(27)) \ 252 CASE_##op((val), TRCRSCTLRn(28)) \ 253 CASE_##op((val), TRCRSCTLRn(29)) \ 254 CASE_##op((val), TRCRSCTLRn(30)) \ 255 CASE_##op((val), TRCRSCTLRn(31)) \ 256 CASE_##op((val), TRCSSCCRn(0)) \ 257 CASE_##op((val), TRCSSCCRn(1)) \ 258 CASE_##op((val), TRCSSCCRn(2)) \ 259 CASE_##op((val), TRCSSCCRn(3)) \ 260 CASE_##op((val), TRCSSCCRn(4)) \ 261 CASE_##op((val), TRCSSCCRn(5)) \ 262 CASE_##op((val), TRCSSCCRn(6)) \ 263 CASE_##op((val), TRCSSCCRn(7)) \ 264 CASE_##op((val), TRCSSCSRn(0)) \ 265 CASE_##op((val), TRCSSCSRn(1)) \ 266 CASE_##op((val), TRCSSCSRn(2)) \ 267 CASE_##op((val), TRCSSCSRn(3)) \ 268 CASE_##op((val), TRCSSCSRn(4)) \ 269 CASE_##op((val), TRCSSCSRn(5)) \ 270 CASE_##op((val), TRCSSCSRn(6)) \ 271 CASE_##op((val), TRCSSCSRn(7)) \ 272 CASE_##op((val), TRCSSPCICRn(0)) \ 273 CASE_##op((val), TRCSSPCICRn(1)) \ 274 CASE_##op((val), TRCSSPCICRn(2)) \ 275 CASE_##op((val), TRCSSPCICRn(3)) \ 276 CASE_##op((val), TRCSSPCICRn(4)) \ 277 CASE_##op((val), TRCSSPCICRn(5)) \ 278 CASE_##op((val), TRCSSPCICRn(6)) \ 279 CASE_##op((val), TRCSSPCICRn(7)) \ 280 CASE_##op((val), TRCOSLAR) \ 281 CASE_##op((val), TRCOSLSR) \ 282 CASE_##op((val), TRCACVRn(0)) \ 283 CASE_##op((val), TRCACVRn(1)) \ 284 CASE_##op((val), TRCACVRn(2)) \ 285 CASE_##op((val), TRCACVRn(3)) \ 286 CASE_##op((val), TRCACVRn(4)) \ 287 CASE_##op((val), TRCACVRn(5)) \ 288 CASE_##op((val), TRCACVRn(6)) \ 289 CASE_##op((val), TRCACVRn(7)) \ 290 CASE_##op((val), TRCACVRn(8)) \ 291 CASE_##op((val), TRCACVRn(9)) \ 292 CASE_##op((val), TRCACVRn(10)) \ 293 CASE_##op((val), TRCACVRn(11)) \ 294 CASE_##op((val), TRCACVRn(12)) \ 295 CASE_##op((val), TRCACVRn(13)) \ 296 CASE_##op((val), TRCACVRn(14)) \ 297 CASE_##op((val), TRCACVRn(15)) \ 298 CASE_##op((val), TRCACATRn(0)) \ 299 CASE_##op((val), TRCACATRn(1)) \ 300 CASE_##op((val), TRCACATRn(2)) \ 301 CASE_##op((val), TRCACATRn(3)) \ 302 CASE_##op((val), TRCACATRn(4)) \ 303 CASE_##op((val), TRCACATRn(5)) \ 304 CASE_##op((val), TRCACATRn(6)) \ 305 CASE_##op((val), TRCACATRn(7)) \ 306 CASE_##op((val), TRCACATRn(8)) \ 307 CASE_##op((val), TRCACATRn(9)) \ 308 CASE_##op((val), TRCACATRn(10)) \ 309 CASE_##op((val), TRCACATRn(11)) \ 310 CASE_##op((val), TRCACATRn(12)) \ 311 CASE_##op((val), TRCACATRn(13)) \ 312 CASE_##op((val), TRCACATRn(14)) \ 313 CASE_##op((val), TRCACATRn(15)) \ 314 CASE_##op((val), TRCDVCVRn(0)) \ 315 CASE_##op((val), TRCDVCVRn(1)) \ 316 CASE_##op((val), TRCDVCVRn(2)) \ 317 CASE_##op((val), TRCDVCVRn(3)) \ 318 CASE_##op((val), TRCDVCVRn(4)) \ 319 CASE_##op((val), TRCDVCVRn(5)) \ 320 CASE_##op((val), TRCDVCVRn(6)) \ 321 CASE_##op((val), TRCDVCVRn(7)) \ 322 CASE_##op((val), TRCDVCMRn(0)) \ 323 CASE_##op((val), TRCDVCMRn(1)) \ 324 CASE_##op((val), TRCDVCMRn(2)) \ 325 CASE_##op((val), TRCDVCMRn(3)) \ 326 CASE_##op((val), TRCDVCMRn(4)) \ 327 CASE_##op((val), TRCDVCMRn(5)) \ 328 CASE_##op((val), TRCDVCMRn(6)) \ 329 CASE_##op((val), TRCDVCMRn(7)) \ 330 CASE_##op((val), TRCCIDCVRn(0)) \ 331 CASE_##op((val), TRCCIDCVRn(1)) \ 332 CASE_##op((val), TRCCIDCVRn(2)) \ 333 CASE_##op((val), TRCCIDCVRn(3)) \ 334 CASE_##op((val), TRCCIDCVRn(4)) \ 335 CASE_##op((val), TRCCIDCVRn(5)) \ 336 CASE_##op((val), TRCCIDCVRn(6)) \ 337 CASE_##op((val), TRCCIDCVRn(7)) \ 338 CASE_##op((val), TRCVMIDCVRn(0)) \ 339 CASE_##op((val), TRCVMIDCVRn(1)) \ 340 CASE_##op((val), TRCVMIDCVRn(2)) \ 341 CASE_##op((val), TRCVMIDCVRn(3)) \ 342 CASE_##op((val), TRCVMIDCVRn(4)) \ 343 CASE_##op((val), TRCVMIDCVRn(5)) \ 344 CASE_##op((val), TRCVMIDCVRn(6)) \ 345 CASE_##op((val), TRCVMIDCVRn(7)) \ 346 CASE_##op((val), TRCCIDCCTLR0) \ 347 CASE_##op((val), TRCCIDCCTLR1) \ 348 CASE_##op((val), TRCVMIDCCTLR0) \ 349 CASE_##op((val), TRCVMIDCCTLR1) \ 350 CASE_##op((val), TRCCLAIMSET) \ 351 CASE_##op((val), TRCCLAIMCLR) \ 352 CASE_##op((val), TRCAUTHSTATUS) \ 353 CASE_##op((val), TRCDEVARCH) \ 354 CASE_##op((val), TRCDEVID) 355 356 /* List of registers only accessible via memory-mapped interface */ 357 #define ETM_MMAP_LIST(op, val) \ 358 CASE_##op((val), TRCDEVTYPE) \ 359 CASE_##op((val), TRCPDCR) \ 360 CASE_##op((val), TRCPDSR) \ 361 CASE_##op((val), TRCDEVAFF0) \ 362 CASE_##op((val), TRCDEVAFF1) \ 363 CASE_##op((val), TRCLAR) \ 364 CASE_##op((val), TRCLSR) \ 365 CASE_##op((val), TRCITCTRL) \ 366 CASE_##op((val), TRCPIDR4) \ 367 CASE_##op((val), TRCPIDR0) \ 368 CASE_##op((val), TRCPIDR1) \ 369 CASE_##op((val), TRCPIDR2) \ 370 CASE_##op((val), TRCPIDR3) 371 372 #define ETM4x_READ_SYSREG_CASES(res) ETM_SYSREG_LIST(READ, (res)) 373 #define ETM4x_WRITE_SYSREG_CASES(val) ETM_SYSREG_LIST(WRITE, (val)) 374 375 #define ETM4x_SYSREG_LIST_CASES ETM_SYSREG_LIST(NOP, __unused) 376 #define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused) 377 378 #define read_etm4x_sysreg_offset(offset, _64bit) \ 379 ({ \ 380 u64 __val; \ 381 \ 382 if (__builtin_constant_p((offset))) \ 383 __val = read_etm4x_sysreg_const_offset((offset)); \ 384 else \ 385 __val = etm4x_sysreg_read((offset), true, (_64bit)); \ 386 __val; \ 387 }) 388 389 #define write_etm4x_sysreg_offset(val, offset, _64bit) \ 390 do { \ 391 if (__builtin_constant_p((offset))) \ 392 write_etm4x_sysreg_const_offset((val), \ 393 (offset)); \ 394 else \ 395 etm4x_sysreg_write((val), (offset), true, \ 396 (_64bit)); \ 397 } while (0) 398 399 400 #define etm4x_relaxed_read32(csa, offset) \ 401 ((u32)((csa)->io_mem ? \ 402 readl_relaxed((csa)->base + (offset)) : \ 403 read_etm4x_sysreg_offset((offset), false))) 404 405 #define etm4x_relaxed_read64(csa, offset) \ 406 ((u64)((csa)->io_mem ? \ 407 readq_relaxed((csa)->base + (offset)) : \ 408 read_etm4x_sysreg_offset((offset), true))) 409 410 #define etm4x_read32(csa, offset) \ 411 ({ \ 412 u32 __val = etm4x_relaxed_read32((csa), (offset)); \ 413 __iormb(__val); \ 414 __val; \ 415 }) 416 417 #define etm4x_read64(csa, offset) \ 418 ({ \ 419 u64 __val = etm4x_relaxed_read64((csa), (offset)); \ 420 __iormb(__val); \ 421 __val; \ 422 }) 423 424 #define etm4x_relaxed_write32(csa, val, offset) \ 425 do { \ 426 if ((csa)->io_mem) \ 427 writel_relaxed((val), (csa)->base + (offset)); \ 428 else \ 429 write_etm4x_sysreg_offset((val), (offset), \ 430 false); \ 431 } while (0) 432 433 #define etm4x_relaxed_write64(csa, val, offset) \ 434 do { \ 435 if ((csa)->io_mem) \ 436 writeq_relaxed((val), (csa)->base + (offset)); \ 437 else \ 438 write_etm4x_sysreg_offset((val), (offset), \ 439 true); \ 440 } while (0) 441 442 #define etm4x_write32(csa, val, offset) \ 443 do { \ 444 __iowmb(); \ 445 etm4x_relaxed_write32((csa), (val), (offset)); \ 446 } while (0) 447 448 #define etm4x_write64(csa, val, offset) \ 449 do { \ 450 __iowmb(); \ 451 etm4x_relaxed_write64((csa), (val), (offset)); \ 452 } while (0) 453 454 455 /* ETMv4 resources */ 456 #define ETM_MAX_NR_PE 8 457 #define ETMv4_MAX_CNTR 4 458 #define ETM_MAX_SEQ_STATES 4 459 #define ETM_MAX_EXT_INP_SEL 4 460 #define ETM_MAX_EXT_INP 256 461 #define ETM_MAX_EXT_OUT 4 462 #define ETM_MAX_SINGLE_ADDR_CMP 16 463 #define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2) 464 #define ETM_MAX_DATA_VAL_CMP 8 465 #define ETMv4_MAX_CTXID_CMP 8 466 #define ETM_MAX_VMID_CMP 8 467 #define ETM_MAX_PE_CMP 8 468 #define ETM_MAX_RES_SEL 32 469 #define ETM_MAX_SS_CMP 8 470 471 #define ETMv4_SYNC_MASK 0x1F 472 #define ETM_CYC_THRESHOLD_MASK 0xFFF 473 #define ETM_CYC_THRESHOLD_DEFAULT 0x100 474 #define ETMv4_EVENT_MASK 0xFF 475 #define ETM_CNTR_MAX_VAL 0xFFFF 476 #define ETM_TRACEID_MASK 0x3f 477 478 /* ETMv4 programming modes */ 479 #define ETM_MODE_EXCLUDE BIT(0) 480 #define ETM_MODE_LOAD BIT(1) 481 #define ETM_MODE_STORE BIT(2) 482 #define ETM_MODE_LOAD_STORE BIT(3) 483 #define ETM_MODE_BB BIT(4) 484 #define ETMv4_MODE_CYCACC BIT(5) 485 #define ETMv4_MODE_CTXID BIT(6) 486 #define ETM_MODE_VMID BIT(7) 487 #define ETM_MODE_COND(val) BMVAL(val, 8, 10) 488 #define ETMv4_MODE_TIMESTAMP BIT(11) 489 #define ETM_MODE_RETURNSTACK BIT(12) 490 #define ETM_MODE_QELEM(val) BMVAL(val, 13, 14) 491 #define ETM_MODE_DATA_TRACE_ADDR BIT(15) 492 #define ETM_MODE_DATA_TRACE_VAL BIT(16) 493 #define ETM_MODE_ISTALL BIT(17) 494 #define ETM_MODE_DSTALL BIT(18) 495 #define ETM_MODE_ATB_TRIGGER BIT(19) 496 #define ETM_MODE_LPOVERRIDE BIT(20) 497 #define ETM_MODE_ISTALL_EN BIT(21) 498 #define ETM_MODE_DSTALL_EN BIT(22) 499 #define ETM_MODE_INSTPRIO BIT(23) 500 #define ETM_MODE_NOOVERFLOW BIT(24) 501 #define ETM_MODE_TRACE_RESET BIT(25) 502 #define ETM_MODE_TRACE_ERR BIT(26) 503 #define ETM_MODE_VIEWINST_STARTSTOP BIT(27) 504 #define ETMv4_MODE_ALL (GENMASK(27, 0) | \ 505 ETM_MODE_EXCL_KERN | \ 506 ETM_MODE_EXCL_USER) 507 508 /* 509 * TRCDEVARCH Bit field definitions 510 * Bits[31:21] - ARCHITECT = Always Arm Ltd. 511 * * Bits[31:28] = 0x4 512 * * Bits[27:21] = 0b0111011 513 * Bit[20] - PRESENT, Indicates the presence of this register. 514 * 515 * Bit[19:16] - REVISION, Revision of the architecture. 516 * 517 * Bit[15:0] - ARCHID, Identifies this component as an ETM 518 * * Bits[15:12] - architecture version of ETM 519 * * = 4 for ETMv4 520 * * Bits[11:0] = 0xA13, architecture part number for ETM. 521 */ 522 #define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21) 523 #define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21)) 524 #define ETM_DEVARCH_PRESENT BIT(20) 525 #define ETM_DEVARCH_REVISION_SHIFT 16 526 #define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16) 527 #define ETM_DEVARCH_REVISION(x) \ 528 (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT) 529 #define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0) 530 #define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12 531 #define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12) 532 #define ETM_DEVARCH_ARCHID_ARCH_VER(x) \ 533 (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) 534 535 #define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \ 536 (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) 537 538 #define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL) 539 540 #define ETM_DEVARCH_MAKE_ARCHID(major) \ 541 ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13)) 542 543 #define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4) 544 545 #define ETM_DEVARCH_ID_MASK \ 546 (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT) 547 #define ETM_DEVARCH_ETMv4x_ARCH \ 548 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT) 549 550 #define TRCSTATR_IDLE_BIT 0 551 #define TRCSTATR_PMSTABLE_BIT 1 552 #define ETM_DEFAULT_ADDR_COMP 0 553 554 #define TRCSSCSRn_PC BIT(3) 555 556 /* PowerDown Control Register bits */ 557 #define TRCPDCR_PU BIT(3) 558 559 #define TRCACATR_EXLEVEL_SHIFT 8 560 561 /* 562 * Exception level mask for Secure and Non-Secure ELs. 563 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn). 564 * The Secure and Non-Secure ELs are always to gether. 565 * Non-secure EL3 is never implemented. 566 * We use the following generic mask as they appear in different 567 * registers and this can be shifted for the appropriate 568 * fields. 569 */ 570 #define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */ 571 #define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */ 572 #define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */ 573 #define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */ 574 #define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */ 575 #define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */ 576 #define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */ 577 578 #define ETM_EXLEVEL_MASK (GENMASK(6, 0)) 579 #define ETM_EXLEVEL_S_MASK (GENMASK(3, 0)) 580 #define ETM_EXLEVEL_NS_MASK (GENMASK(6, 4)) 581 582 /* access level controls in TRCACATRn */ 583 #define TRCACATR_EXLEVEL_SHIFT 8 584 585 /* access level control in TRCVICTLR */ 586 #define TRCVICTLR_EXLEVEL_SHIFT 16 587 #define TRCVICTLR_EXLEVEL_S_SHIFT 16 588 #define TRCVICTLR_EXLEVEL_NS_SHIFT 20 589 590 /* secure / non secure masks - TRCVICTLR, IDR3 */ 591 #define TRCVICTLR_EXLEVEL_MASK (ETM_EXLEVEL_MASK << TRCVICTLR_EXLEVEL_SHIFT) 592 #define TRCVICTLR_EXLEVEL_S_MASK (ETM_EXLEVEL_S_MASK << TRCVICTLR_EXLEVEL_SHIFT) 593 #define TRCVICTLR_EXLEVEL_NS_MASK (ETM_EXLEVEL_NS_MASK << TRCVICTLR_EXLEVEL_SHIFT) 594 595 #define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8 596 #define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT) 597 #define ETM_TRCIDR1_ARCH_MAJOR(x) \ 598 (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT) 599 #define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4 600 #define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT) 601 #define ETM_TRCIDR1_ARCH_MINOR(x) \ 602 (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT) 603 #define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT 604 #define ETM_TRCIDR1_ARCH_MASK \ 605 (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK) 606 607 #define ETM_TRCIDR1_ARCH_ETMv4 0x4 608 609 /* 610 * Driver representation of the ETM architecture. 611 * The version of an ETM component can be detected from 612 * 613 * TRCDEVARCH - CoreSight architected register 614 * - Bits[15:12] - Major version 615 * - Bits[19:16] - Minor version 616 * TRCIDR1 - ETM architected register 617 * - Bits[11:8] - Major version 618 * - Bits[7:4] - Minor version 619 * We must rely on TRCDEVARCH for the version information, 620 * however we don't want to break the support for potential 621 * old implementations which might not implement it. Thus 622 * we fall back to TRCIDR1 if TRCDEVARCH is not implemented 623 * for memory mapped components. 624 * Now to make certain decisions easier based on the version 625 * we use an internal representation of the version in the 626 * driver, as follows : 627 * 628 * ETM_ARCH_VERSION[7:0], where : 629 * Bits[7:4] - Major version 630 * Bits[3:0] - Minro version 631 */ 632 #define ETM_ARCH_VERSION(major, minor) \ 633 ((((major) & 0xfU) << 4) | (((minor) & 0xfU))) 634 #define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU) 635 #define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU) 636 637 #define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0) 638 /* Interpretation of resource numbers change at ETM v4.3 architecture */ 639 #define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3) 640 641 static inline u8 etm_devarch_to_arch(u32 devarch) 642 { 643 return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch), 644 ETM_DEVARCH_REVISION(devarch)); 645 } 646 647 static inline u8 etm_trcidr_to_arch(u32 trcidr1) 648 { 649 return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1), 650 ETM_TRCIDR1_ARCH_MINOR(trcidr1)); 651 } 652 653 enum etm_impdef_type { 654 ETM4_IMPDEF_HISI_CORE_COMMIT, 655 ETM4_IMPDEF_FEATURE_MAX, 656 }; 657 658 /** 659 * struct etmv4_config - configuration information related to an ETMv4 660 * @mode: Controls various modes supported by this ETM. 661 * @pe_sel: Controls which PE to trace. 662 * @cfg: Controls the tracing options. 663 * @eventctrl0: Controls the tracing of arbitrary events. 664 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects. 665 * @stallctl: If functionality that prevents trace unit buffer overflows 666 * is available. 667 * @ts_ctrl: Controls the insertion of global timestamps in the 668 * trace streams. 669 * @syncfreq: Controls how often trace synchronization requests occur. 670 * the TRCCCCTLR register. 671 * @ccctlr: Sets the threshold value for cycle counting. 672 * @vinst_ctrl: Controls instruction trace filtering. 673 * @viiectlr: Set or read, the address range comparators. 674 * @vissctlr: Set, or read, the single address comparators that control the 675 * ViewInst start-stop logic. 676 * @vipcssctlr: Set, or read, which PE comparator inputs can control the 677 * ViewInst start-stop logic. 678 * @seq_idx: Sequencor index selector. 679 * @seq_ctrl: Control for the sequencer state transition control register. 680 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs. 681 * @seq_state: Set, or read the sequencer state. 682 * @cntr_idx: Counter index seletor. 683 * @cntrldvr: Sets or returns the reload count value for a counter. 684 * @cntr_ctrl: Controls the operation of a counter. 685 * @cntr_val: Sets or returns the value for a counter. 686 * @res_idx: Resource index selector. 687 * @res_ctrl: Controls the selection of the resources in the trace unit. 688 * @ss_idx: Single-shot index selector. 689 * @ss_ctrl: Controls the corresponding single-shot comparator resource. 690 * @ss_status: The status of the corresponding single-shot comparator. 691 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control. 692 * @addr_idx: Address comparator index selector. 693 * @addr_val: Value for address comparator. 694 * @addr_acc: Address comparator access type. 695 * @addr_type: Current status of the comparator register. 696 * @ctxid_idx: Context ID index selector. 697 * @ctxid_pid: Value of the context ID comparator. 698 * @ctxid_mask0:Context ID comparator mask for comparator 0-3. 699 * @ctxid_mask1:Context ID comparator mask for comparator 4-7. 700 * @vmid_idx: VM ID index selector. 701 * @vmid_val: Value of the VM ID comparator. 702 * @vmid_mask0: VM ID comparator mask for comparator 0-3. 703 * @vmid_mask1: VM ID comparator mask for comparator 4-7. 704 * @ext_inp: External input selection. 705 * @s_ex_level: Secure ELs where tracing is supported. 706 */ 707 struct etmv4_config { 708 u32 mode; 709 u32 pe_sel; 710 u32 cfg; 711 u32 eventctrl0; 712 u32 eventctrl1; 713 u32 stall_ctrl; 714 u32 ts_ctrl; 715 u32 syncfreq; 716 u32 ccctlr; 717 u32 bb_ctrl; 718 u32 vinst_ctrl; 719 u32 viiectlr; 720 u32 vissctlr; 721 u32 vipcssctlr; 722 u8 seq_idx; 723 u32 seq_ctrl[ETM_MAX_SEQ_STATES]; 724 u32 seq_rst; 725 u32 seq_state; 726 u8 cntr_idx; 727 u32 cntrldvr[ETMv4_MAX_CNTR]; 728 u32 cntr_ctrl[ETMv4_MAX_CNTR]; 729 u32 cntr_val[ETMv4_MAX_CNTR]; 730 u8 res_idx; 731 u32 res_ctrl[ETM_MAX_RES_SEL]; 732 u8 ss_idx; 733 u32 ss_ctrl[ETM_MAX_SS_CMP]; 734 u32 ss_status[ETM_MAX_SS_CMP]; 735 u32 ss_pe_cmp[ETM_MAX_SS_CMP]; 736 u8 addr_idx; 737 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; 738 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP]; 739 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP]; 740 u8 ctxid_idx; 741 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP]; 742 u32 ctxid_mask0; 743 u32 ctxid_mask1; 744 u8 vmid_idx; 745 u64 vmid_val[ETM_MAX_VMID_CMP]; 746 u32 vmid_mask0; 747 u32 vmid_mask1; 748 u32 ext_inp; 749 u8 s_ex_level; 750 }; 751 752 /** 753 * struct etm4_save_state - state to be preserved when ETM is without power 754 */ 755 struct etmv4_save_state { 756 u32 trcprgctlr; 757 u32 trcprocselr; 758 u32 trcconfigr; 759 u32 trcauxctlr; 760 u32 trceventctl0r; 761 u32 trceventctl1r; 762 u32 trcstallctlr; 763 u32 trctsctlr; 764 u32 trcsyncpr; 765 u32 trcccctlr; 766 u32 trcbbctlr; 767 u32 trctraceidr; 768 u32 trcqctlr; 769 770 u32 trcvictlr; 771 u32 trcviiectlr; 772 u32 trcvissctlr; 773 u32 trcvipcssctlr; 774 u32 trcvdctlr; 775 u32 trcvdsacctlr; 776 u32 trcvdarcctlr; 777 778 u32 trcseqevr[ETM_MAX_SEQ_STATES]; 779 u32 trcseqrstevr; 780 u32 trcseqstr; 781 u32 trcextinselr; 782 u32 trccntrldvr[ETMv4_MAX_CNTR]; 783 u32 trccntctlr[ETMv4_MAX_CNTR]; 784 u32 trccntvr[ETMv4_MAX_CNTR]; 785 786 u32 trcrsctlr[ETM_MAX_RES_SEL]; 787 788 u32 trcssccr[ETM_MAX_SS_CMP]; 789 u32 trcsscsr[ETM_MAX_SS_CMP]; 790 u32 trcsspcicr[ETM_MAX_SS_CMP]; 791 792 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP]; 793 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP]; 794 u64 trccidcvr[ETMv4_MAX_CTXID_CMP]; 795 u64 trcvmidcvr[ETM_MAX_VMID_CMP]; 796 u32 trccidcctlr0; 797 u32 trccidcctlr1; 798 u32 trcvmidcctlr0; 799 u32 trcvmidcctlr1; 800 801 u32 trcclaimset; 802 803 u32 cntr_val[ETMv4_MAX_CNTR]; 804 u32 seq_state; 805 u32 vinst_ctrl; 806 u32 ss_status[ETM_MAX_SS_CMP]; 807 808 u32 trcpdcr; 809 }; 810 811 /** 812 * struct etm4_drvdata - specifics associated to an ETM component 813 * @base: Memory mapped base address for this component. 814 * @csdev: Component vitals needed by the framework. 815 * @spinlock: Only one at a time pls. 816 * @mode: This tracer's mode, i.e sysFS, Perf or disabled. 817 * @cpu: The cpu this component is affined to. 818 * @arch: ETM architecture version. 819 * @nr_pe: The number of processing entity available for tracing. 820 * @nr_pe_cmp: The number of processing entity comparator inputs that are 821 * available for tracing. 822 * @nr_addr_cmp:Number of pairs of address comparators available 823 * as found in ETMIDR4 0-3. 824 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. 825 * @nr_ext_inp: Number of external input. 826 * @numcidc: Number of contextID comparators. 827 * @numvmidc: Number of VMID comparators. 828 * @nrseqstate: The number of sequencer states that are implemented. 829 * @nr_event: Indicates how many events the trace unit support. 830 * @nr_resource:The number of resource selection pairs available for tracing. 831 * @nr_ss_cmp: Number of single-shot comparator controls that are available. 832 * @trcid: value of the current ID for this component. 833 * @trcid_size: Indicates the trace ID width. 834 * @ts_size: Global timestamp size field. 835 * @ctxid_size: Size of the context ID field to consider. 836 * @vmid_size: Size of the VM ID comparator to consider. 837 * @ccsize: Indicates the size of the cycle counter in bits. 838 * @ccitmin: minimum value that can be programmed in 839 * @s_ex_level: In secure state, indicates whether instruction tracing is 840 * supported for the corresponding Exception level. 841 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is 842 * supported for the corresponding Exception level. 843 * @sticky_enable: true if ETM base configuration has been done. 844 * @boot_enable:True if we should start tracing at boot time. 845 * @os_unlock: True if access to management registers is allowed. 846 * @instrp0: Tracing of load and store instructions 847 * as P0 elements is supported. 848 * @trcbb: Indicates if the trace unit supports branch broadcast tracing. 849 * @trccond: If the trace unit supports conditional 850 * instruction tracing. 851 * @retstack: Indicates if the implementation supports a return stack. 852 * @trccci: Indicates if the trace unit supports cycle counting 853 * for instruction. 854 * @q_support: Q element support characteristics. 855 * @trc_error: Whether a trace unit can trace a system 856 * error exception. 857 * @syncpr: Indicates if an implementation has a fixed 858 * synchronization period. 859 * @stall_ctrl: Enables trace unit functionality that prevents trace 860 * unit buffer overflows. 861 * @sysstall: Does the system support stall control of the PE? 862 * @nooverflow: Indicate if overflow prevention is supported. 863 * @atbtrig: If the implementation can support ATB triggers 864 * @lpoverride: If the implementation can support low-power state over. 865 * @config: structure holding configuration parameters. 866 * @save_state: State to be preserved across power loss 867 * @state_needs_restore: True when there is context to restore after PM exit 868 * @skip_power_up: Indicates if an implementation can skip powering up 869 * the trace unit. 870 * @arch_features: Bitmap of arch features of etmv4 devices. 871 */ 872 struct etmv4_drvdata { 873 void __iomem *base; 874 struct coresight_device *csdev; 875 spinlock_t spinlock; 876 local_t mode; 877 int cpu; 878 u8 arch; 879 u8 nr_pe; 880 u8 nr_pe_cmp; 881 u8 nr_addr_cmp; 882 u8 nr_cntr; 883 u8 nr_ext_inp; 884 u8 numcidc; 885 u8 numvmidc; 886 u8 nrseqstate; 887 u8 nr_event; 888 u8 nr_resource; 889 u8 nr_ss_cmp; 890 u8 trcid; 891 u8 trcid_size; 892 u8 ts_size; 893 u8 ctxid_size; 894 u8 vmid_size; 895 u8 ccsize; 896 u8 ccitmin; 897 u8 s_ex_level; 898 u8 ns_ex_level; 899 u8 q_support; 900 bool sticky_enable; 901 bool boot_enable; 902 bool os_unlock; 903 bool instrp0; 904 bool trcbb; 905 bool trccond; 906 bool retstack; 907 bool trccci; 908 bool trc_error; 909 bool syncpr; 910 bool stallctl; 911 bool sysstall; 912 bool nooverflow; 913 bool atbtrig; 914 bool lpoverride; 915 struct etmv4_config config; 916 struct etmv4_save_state *save_state; 917 bool state_needs_restore; 918 bool skip_power_up; 919 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); 920 }; 921 922 /* Address comparator access types */ 923 enum etm_addr_acctype { 924 ETM_INSTR_ADDR, 925 ETM_DATA_LOAD_ADDR, 926 ETM_DATA_STORE_ADDR, 927 ETM_DATA_LOAD_STORE_ADDR, 928 }; 929 930 /* Address comparator context types */ 931 enum etm_addr_ctxtype { 932 ETM_CTX_NONE, 933 ETM_CTX_CTXID, 934 ETM_CTX_VMID, 935 ETM_CTX_CTXID_VMID, 936 }; 937 938 extern const struct attribute_group *coresight_etmv4_groups[]; 939 void etm4_config_trace_mode(struct etmv4_config *config); 940 941 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); 942 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit); 943 #endif 944