1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/kernel.h> 8 #include <linux/moduleparam.h> 9 #include <linux/init.h> 10 #include <linux/types.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/err.h> 14 #include <linux/fs.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/smp.h> 18 #include <linux/sysfs.h> 19 #include <linux/stat.h> 20 #include <linux/clk.h> 21 #include <linux/cpu.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/coresight.h> 24 #include <linux/coresight-pmu.h> 25 #include <linux/pm_wakeup.h> 26 #include <linux/amba/bus.h> 27 #include <linux/seq_file.h> 28 #include <linux/uaccess.h> 29 #include <linux/perf_event.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/property.h> 33 34 #include <asm/barrier.h> 35 #include <asm/sections.h> 36 #include <asm/sysreg.h> 37 #include <asm/local.h> 38 #include <asm/virt.h> 39 40 #include "coresight-etm4x.h" 41 #include "coresight-etm-perf.h" 42 #include "coresight-etm4x-cfg.h" 43 #include "coresight-self-hosted-trace.h" 44 #include "coresight-syscfg.h" 45 46 static int boot_enable; 47 module_param(boot_enable, int, 0444); 48 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); 49 50 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */ 51 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */ 52 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ 53 54 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; 55 module_param(pm_save_enable, int, 0444); 56 MODULE_PARM_DESC(pm_save_enable, 57 "Save/restore state on power down: 1 = never, 2 = self-hosted"); 58 59 static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; 60 static void etm4_set_default_config(struct etmv4_config *config); 61 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 62 struct perf_event *event); 63 static u64 etm4_get_access_type(struct etmv4_config *config); 64 65 static enum cpuhp_state hp_online; 66 67 struct etm4_init_arg { 68 unsigned int pid; 69 struct device *dev; 70 struct csdev_access *csa; 71 }; 72 73 static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe); 74 static int etm4_probe_cpu(unsigned int cpu); 75 76 /* 77 * Check if TRCSSPCICRn(i) is implemented for a given instance. 78 * 79 * TRCSSPCICRn is implemented only if : 80 * TRCSSPCICR<n> is present only if all of the following are true: 81 * TRCIDR4.NUMSSCC > n. 82 * TRCIDR4.NUMPC > 0b0000 . 83 * TRCSSCSR<n>.PC == 0b1 84 */ 85 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) 86 { 87 return (n < drvdata->nr_ss_cmp) && 88 drvdata->nr_pe && 89 (drvdata->config.ss_status[n] & TRCSSCSRn_PC); 90 } 91 92 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) 93 { 94 u64 res = 0; 95 96 switch (offset) { 97 ETM4x_READ_SYSREG_CASES(res) 98 default : 99 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n", 100 offset); 101 } 102 103 if (!_relaxed) 104 __io_ar(res); /* Imitate the !relaxed I/O helpers */ 105 106 return res; 107 } 108 109 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) 110 { 111 if (!_relaxed) 112 __io_bw(); /* Imitate the !relaxed I/O helpers */ 113 if (!_64bit) 114 val &= GENMASK(31, 0); 115 116 switch (offset) { 117 ETM4x_WRITE_SYSREG_CASES(val) 118 default : 119 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n", 120 offset); 121 } 122 } 123 124 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit) 125 { 126 u64 res = 0; 127 128 switch (offset) { 129 ETE_READ_CASES(res) 130 default : 131 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n", 132 offset); 133 } 134 135 if (!_relaxed) 136 __io_ar(res); /* Imitate the !relaxed I/O helpers */ 137 138 return res; 139 } 140 141 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) 142 { 143 if (!_relaxed) 144 __io_bw(); /* Imitate the !relaxed I/O helpers */ 145 if (!_64bit) 146 val &= GENMASK(31, 0); 147 148 switch (offset) { 149 ETE_WRITE_CASES(val) 150 default : 151 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n", 152 offset); 153 } 154 } 155 156 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, 157 struct csdev_access *csa) 158 { 159 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR); 160 161 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr); 162 } 163 164 static void etm_write_os_lock(struct etmv4_drvdata *drvdata, 165 struct csdev_access *csa, u32 val) 166 { 167 val = !!val; 168 169 switch (drvdata->os_lock_model) { 170 case ETM_OSLOCK_PRESENT: 171 etm4x_relaxed_write32(csa, val, TRCOSLAR); 172 break; 173 case ETM_OSLOCK_PE: 174 write_sysreg_s(val, SYS_OSLAR_EL1); 175 break; 176 default: 177 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n", 178 smp_processor_id(), drvdata->os_lock_model); 179 fallthrough; 180 case ETM_OSLOCK_NI: 181 return; 182 } 183 isb(); 184 } 185 186 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, 187 struct csdev_access *csa) 188 { 189 WARN_ON(drvdata->cpu != smp_processor_id()); 190 191 /* Writing 0 to OS Lock unlocks the trace unit registers */ 192 etm_write_os_lock(drvdata, csa, 0x0); 193 drvdata->os_unlock = true; 194 } 195 196 static void etm4_os_unlock(struct etmv4_drvdata *drvdata) 197 { 198 if (!WARN_ON(!drvdata->csdev)) 199 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access); 200 } 201 202 static void etm4_os_lock(struct etmv4_drvdata *drvdata) 203 { 204 if (WARN_ON(!drvdata->csdev)) 205 return; 206 /* Writing 0x1 to OS Lock locks the trace registers */ 207 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1); 208 drvdata->os_unlock = false; 209 } 210 211 static void etm4_cs_lock(struct etmv4_drvdata *drvdata, 212 struct csdev_access *csa) 213 { 214 /* Software Lock is only accessible via memory mapped interface */ 215 if (csa->io_mem) 216 CS_LOCK(csa->base); 217 } 218 219 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, 220 struct csdev_access *csa) 221 { 222 if (csa->io_mem) 223 CS_UNLOCK(csa->base); 224 } 225 226 static int etm4_cpu_id(struct coresight_device *csdev) 227 { 228 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 229 230 return drvdata->cpu; 231 } 232 233 static int etm4_trace_id(struct coresight_device *csdev) 234 { 235 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 236 237 return drvdata->trcid; 238 } 239 240 struct etm4_enable_arg { 241 struct etmv4_drvdata *drvdata; 242 int rc; 243 }; 244 245 /* 246 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs. 247 * When the CPU supports FEAT_TRF, we could move the ETM to a trace 248 * prohibited state by filtering the Exception levels via TRFCR_EL1. 249 */ 250 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata) 251 { 252 /* If the CPU doesn't support FEAT_TRF, nothing to do */ 253 if (!drvdata->trfcr) 254 return; 255 cpu_prohibit_trace(); 256 } 257 258 /* 259 * etm4x_allow_trace - Allow CPU tracing in the respective ELs, 260 * as configured by the drvdata->config.mode for the current 261 * session. Even though we have TRCVICTLR bits to filter the 262 * trace in the ELs, it doesn't prevent the ETM from generating 263 * a packet (e.g, TraceInfo) that might contain the addresses from 264 * the excluded levels. Thus we use the additional controls provided 265 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace 266 * is generated for the excluded ELs. 267 */ 268 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) 269 { 270 u64 trfcr = drvdata->trfcr; 271 272 /* If the CPU doesn't support FEAT_TRF, nothing to do */ 273 if (!trfcr) 274 return; 275 276 if (drvdata->config.mode & ETM_MODE_EXCL_KERN) 277 trfcr &= ~TRFCR_ELx_ExTRE; 278 if (drvdata->config.mode & ETM_MODE_EXCL_USER) 279 trfcr &= ~TRFCR_ELx_E0TRE; 280 281 write_trfcr(trfcr); 282 } 283 284 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE 285 286 #define HISI_HIP08_AMBA_ID 0x000b6d01 287 #define ETM4_AMBA_MASK 0xfffff 288 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000 289 #define HISI_HIP08_CORE_COMMIT_SHIFT 12 290 #define HISI_HIP08_CORE_COMMIT_FULL 0b00 291 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01 292 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5) 293 294 struct etm4_arch_features { 295 void (*arch_callback)(bool enable); 296 }; 297 298 static bool etm4_hisi_match_pid(unsigned int id) 299 { 300 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID; 301 } 302 303 static void etm4_hisi_config_core_commit(bool enable) 304 { 305 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 : 306 HISI_HIP08_CORE_COMMIT_FULL; 307 u64 val; 308 309 /* 310 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together 311 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01, 312 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1 313 * speed(minimun value). So bit 12 and 13 should be cleared together. 314 */ 315 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG); 316 val &= ~HISI_HIP08_CORE_COMMIT_MASK; 317 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT; 318 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG); 319 } 320 321 static struct etm4_arch_features etm4_features[] = { 322 [ETM4_IMPDEF_HISI_CORE_COMMIT] = { 323 .arch_callback = etm4_hisi_config_core_commit, 324 }, 325 {}, 326 }; 327 328 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 329 { 330 struct etm4_arch_features *ftr; 331 int bit; 332 333 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 334 ftr = &etm4_features[bit]; 335 336 if (ftr->arch_callback) 337 ftr->arch_callback(true); 338 } 339 } 340 341 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 342 { 343 struct etm4_arch_features *ftr; 344 int bit; 345 346 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 347 ftr = &etm4_features[bit]; 348 349 if (ftr->arch_callback) 350 ftr->arch_callback(false); 351 } 352 } 353 354 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 355 unsigned int id) 356 { 357 if (etm4_hisi_match_pid(id)) 358 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features); 359 } 360 #else 361 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 362 { 363 } 364 365 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 366 { 367 } 368 369 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 370 unsigned int id) 371 { 372 } 373 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */ 374 375 static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 376 { 377 int i, rc; 378 struct etmv4_config *config = &drvdata->config; 379 struct coresight_device *csdev = drvdata->csdev; 380 struct device *etm_dev = &csdev->dev; 381 struct csdev_access *csa = &csdev->access; 382 383 384 etm4_cs_unlock(drvdata, csa); 385 etm4_enable_arch_specific(drvdata); 386 387 etm4_os_unlock(drvdata); 388 389 rc = coresight_claim_device_unlocked(csdev); 390 if (rc) 391 goto done; 392 393 /* Disable the trace unit before programming trace registers */ 394 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); 395 396 /* 397 * If we use system instructions, we need to synchronize the 398 * write to the TRCPRGCTLR, before accessing the TRCSTATR. 399 * See ARM IHI0064F, section 400 * "4.3.7 Synchronization of register updates" 401 */ 402 if (!csa->io_mem) 403 isb(); 404 405 /* wait for TRCSTATR.IDLE to go up */ 406 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) 407 dev_err(etm_dev, 408 "timeout while waiting for Idle Trace Status\n"); 409 if (drvdata->nr_pe) 410 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); 411 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); 412 /* nothing specific implemented */ 413 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); 414 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); 415 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); 416 if (drvdata->stallctl) 417 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); 418 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); 419 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); 420 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR); 421 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR); 422 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR); 423 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); 424 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); 425 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); 426 if (drvdata->nr_pe_cmp) 427 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); 428 for (i = 0; i < drvdata->nrseqstate - 1; i++) 429 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); 430 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); 431 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); 432 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); 433 for (i = 0; i < drvdata->nr_cntr; i++) { 434 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); 435 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); 436 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); 437 } 438 439 /* 440 * Resource selector pair 0 is always implemented and reserved. As 441 * such start at 2. 442 */ 443 for (i = 2; i < drvdata->nr_resource * 2; i++) 444 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); 445 446 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 447 /* always clear status bit on restart if using single-shot */ 448 if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) 449 config->ss_status[i] &= ~TRCSSCSRn_STATUS; 450 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); 451 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); 452 if (etm4x_sspcicrn_present(drvdata, i)) 453 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); 454 } 455 for (i = 0; i < drvdata->nr_addr_cmp; i++) { 456 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); 457 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); 458 } 459 for (i = 0; i < drvdata->numcidc; i++) 460 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); 461 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); 462 if (drvdata->numcidc > 4) 463 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); 464 465 for (i = 0; i < drvdata->numvmidc; i++) 466 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); 467 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); 468 if (drvdata->numvmidc > 4) 469 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); 470 471 if (!drvdata->skip_power_up) { 472 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); 473 474 /* 475 * Request to keep the trace unit powered and also 476 * emulation of powerdown 477 */ 478 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); 479 } 480 481 /* 482 * ETE mandates that the TRCRSR is written to before 483 * enabling it. 484 */ 485 if (etm4x_is_ete(drvdata)) 486 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR); 487 488 etm4x_allow_trace(drvdata); 489 /* Enable the trace unit */ 490 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); 491 492 /* Synchronize the register updates for sysreg access */ 493 if (!csa->io_mem) 494 isb(); 495 496 /* wait for TRCSTATR.IDLE to go back down to '0' */ 497 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) 498 dev_err(etm_dev, 499 "timeout while waiting for Idle Trace Status\n"); 500 501 /* 502 * As recommended by section 4.3.7 ("Synchronization when using the 503 * memory-mapped interface") of ARM IHI 0064D 504 */ 505 dsb(sy); 506 isb(); 507 508 done: 509 etm4_cs_lock(drvdata, csa); 510 511 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", 512 drvdata->cpu, rc); 513 return rc; 514 } 515 516 static void etm4_enable_hw_smp_call(void *info) 517 { 518 struct etm4_enable_arg *arg = info; 519 520 if (WARN_ON(!arg)) 521 return; 522 arg->rc = etm4_enable_hw(arg->drvdata); 523 } 524 525 /* 526 * The goal of function etm4_config_timestamp_event() is to configure a 527 * counter that will tell the tracer to emit a timestamp packet when it 528 * reaches zero. This is done in order to get a more fine grained idea 529 * of when instructions are executed so that they can be correlated 530 * with execution on other CPUs. 531 * 532 * To do this the counter itself is configured to self reload and 533 * TRCRSCTLR1 (always true) used to get the counter to decrement. From 534 * there a resource selector is configured with the counter and the 535 * timestamp control register to use the resource selector to trigger the 536 * event that will insert a timestamp packet in the stream. 537 */ 538 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) 539 { 540 int ctridx, ret = -EINVAL; 541 int counter, rselector; 542 u32 val = 0; 543 struct etmv4_config *config = &drvdata->config; 544 545 /* No point in trying if we don't have at least one counter */ 546 if (!drvdata->nr_cntr) 547 goto out; 548 549 /* Find a counter that hasn't been initialised */ 550 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) 551 if (config->cntr_val[ctridx] == 0) 552 break; 553 554 /* All the counters have been configured already, bail out */ 555 if (ctridx == drvdata->nr_cntr) { 556 pr_debug("%s: no available counter found\n", __func__); 557 ret = -ENOSPC; 558 goto out; 559 } 560 561 /* 562 * Searching for an available resource selector to use, starting at 563 * '2' since every implementation has at least 2 resource selector. 564 * ETMIDR4 gives the number of resource selector _pairs_, 565 * hence multiply by 2. 566 */ 567 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) 568 if (!config->res_ctrl[rselector]) 569 break; 570 571 if (rselector == drvdata->nr_resource * 2) { 572 pr_debug("%s: no available resource selector found\n", 573 __func__); 574 ret = -ENOSPC; 575 goto out; 576 } 577 578 /* Remember what counter we used */ 579 counter = 1 << ctridx; 580 581 /* 582 * Initialise original and reload counter value to the smallest 583 * possible value in order to get as much precision as we can. 584 */ 585 config->cntr_val[ctridx] = 1; 586 config->cntrldvr[ctridx] = 1; 587 588 /* Set the trace counter control register */ 589 val = 0x1 << 16 | /* Bit 16, reload counter automatically */ 590 0x0 << 7 | /* Select single resource selector */ 591 0x1; /* Resource selector 1, i.e always true */ 592 593 config->cntr_ctrl[ctridx] = val; 594 595 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ 596 counter << 0; /* Counter to use */ 597 598 config->res_ctrl[rselector] = val; 599 600 val = 0x0 << 7 | /* Select single resource selector */ 601 rselector; /* Resource selector */ 602 603 config->ts_ctrl = val; 604 605 ret = 0; 606 out: 607 return ret; 608 } 609 610 static int etm4_parse_event_config(struct coresight_device *csdev, 611 struct perf_event *event) 612 { 613 int ret = 0; 614 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 615 struct etmv4_config *config = &drvdata->config; 616 struct perf_event_attr *attr = &event->attr; 617 unsigned long cfg_hash; 618 int preset; 619 620 /* Clear configuration from previous run */ 621 memset(config, 0, sizeof(struct etmv4_config)); 622 623 if (attr->exclude_kernel) 624 config->mode = ETM_MODE_EXCL_KERN; 625 626 if (attr->exclude_user) 627 config->mode = ETM_MODE_EXCL_USER; 628 629 /* Always start from the default config */ 630 etm4_set_default_config(config); 631 632 /* Configure filters specified on the perf cmd line, if any. */ 633 ret = etm4_set_event_filters(drvdata, event); 634 if (ret) 635 goto out; 636 637 /* Go from generic option to ETMv4 specifics */ 638 if (attr->config & BIT(ETM_OPT_CYCACC)) { 639 config->cfg |= TRCCONFIGR_CCI; 640 /* TRM: Must program this for cycacc to work */ 641 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; 642 } 643 if (attr->config & BIT(ETM_OPT_TS)) { 644 /* 645 * Configure timestamps to be emitted at regular intervals in 646 * order to correlate instructions executed on different CPUs 647 * (CPU-wide trace scenarios). 648 */ 649 ret = etm4_config_timestamp_event(drvdata); 650 651 /* 652 * No need to go further if timestamp intervals can't 653 * be configured. 654 */ 655 if (ret) 656 goto out; 657 658 /* bit[11], Global timestamp tracing bit */ 659 config->cfg |= TRCCONFIGR_TS; 660 } 661 662 /* Only trace contextID when runs in root PID namespace */ 663 if ((attr->config & BIT(ETM_OPT_CTXTID)) && 664 task_is_in_init_pid_ns(current)) 665 /* bit[6], Context ID tracing bit */ 666 config->cfg |= TRCCONFIGR_CID; 667 668 /* 669 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID 670 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the 671 * kernel is not running in EL2. 672 */ 673 if (attr->config & BIT(ETM_OPT_CTXTID2)) { 674 if (!is_kernel_in_hyp_mode()) { 675 ret = -EINVAL; 676 goto out; 677 } 678 /* Only trace virtual contextID when runs in root PID namespace */ 679 if (task_is_in_init_pid_ns(current)) 680 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT; 681 } 682 683 /* return stack - enable if selected and supported */ 684 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) 685 /* bit[12], Return stack enable bit */ 686 config->cfg |= TRCCONFIGR_RS; 687 688 /* 689 * Set any selected configuration and preset. 690 * 691 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset) 692 * in the perf attributes defined in coresight-etm-perf.c. 693 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config. 694 * A zero configid means no configuration active, preset = 0 means no preset selected. 695 */ 696 if (attr->config2 & GENMASK_ULL(63, 32)) { 697 cfg_hash = (u32)(attr->config2 >> 32); 698 preset = attr->config & 0xF; 699 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); 700 } 701 702 /* branch broadcast - enable if selected and supported */ 703 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { 704 if (!drvdata->trcbb) { 705 /* 706 * Missing BB support could cause silent decode errors 707 * so fail to open if it's not supported. 708 */ 709 ret = -EINVAL; 710 goto out; 711 } else { 712 config->cfg |= BIT(ETM4_CFG_BIT_BB); 713 } 714 } 715 716 out: 717 return ret; 718 } 719 720 static int etm4_enable_perf(struct coresight_device *csdev, 721 struct perf_event *event) 722 { 723 int ret = 0; 724 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 725 726 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { 727 ret = -EINVAL; 728 goto out; 729 } 730 731 /* Configure the tracer based on the session's specifics */ 732 ret = etm4_parse_event_config(csdev, event); 733 if (ret) 734 goto out; 735 /* And enable it */ 736 ret = etm4_enable_hw(drvdata); 737 738 out: 739 return ret; 740 } 741 742 static int etm4_enable_sysfs(struct coresight_device *csdev) 743 { 744 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 745 struct etm4_enable_arg arg = { }; 746 unsigned long cfg_hash; 747 int ret, preset; 748 749 /* enable any config activated by configfs */ 750 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); 751 if (cfg_hash) { 752 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); 753 if (ret) 754 return ret; 755 } 756 757 spin_lock(&drvdata->spinlock); 758 759 /* 760 * Executing etm4_enable_hw on the cpu whose ETM is being enabled 761 * ensures that register writes occur when cpu is powered. 762 */ 763 arg.drvdata = drvdata; 764 ret = smp_call_function_single(drvdata->cpu, 765 etm4_enable_hw_smp_call, &arg, 1); 766 if (!ret) 767 ret = arg.rc; 768 if (!ret) 769 drvdata->sticky_enable = true; 770 spin_unlock(&drvdata->spinlock); 771 772 if (!ret) 773 dev_dbg(&csdev->dev, "ETM tracing enabled\n"); 774 return ret; 775 } 776 777 static int etm4_enable(struct coresight_device *csdev, 778 struct perf_event *event, u32 mode) 779 { 780 int ret; 781 u32 val; 782 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 783 784 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); 785 786 /* Someone is already using the tracer */ 787 if (val) 788 return -EBUSY; 789 790 switch (mode) { 791 case CS_MODE_SYSFS: 792 ret = etm4_enable_sysfs(csdev); 793 break; 794 case CS_MODE_PERF: 795 ret = etm4_enable_perf(csdev, event); 796 break; 797 default: 798 ret = -EINVAL; 799 } 800 801 /* The tracer didn't start */ 802 if (ret) 803 local_set(&drvdata->mode, CS_MODE_DISABLED); 804 805 return ret; 806 } 807 808 static void etm4_disable_hw(void *info) 809 { 810 u32 control; 811 struct etmv4_drvdata *drvdata = info; 812 struct etmv4_config *config = &drvdata->config; 813 struct coresight_device *csdev = drvdata->csdev; 814 struct device *etm_dev = &csdev->dev; 815 struct csdev_access *csa = &csdev->access; 816 int i; 817 818 etm4_cs_unlock(drvdata, csa); 819 etm4_disable_arch_specific(drvdata); 820 821 if (!drvdata->skip_power_up) { 822 /* power can be removed from the trace unit now */ 823 control = etm4x_relaxed_read32(csa, TRCPDCR); 824 control &= ~TRCPDCR_PU; 825 etm4x_relaxed_write32(csa, control, TRCPDCR); 826 } 827 828 control = etm4x_relaxed_read32(csa, TRCPRGCTLR); 829 830 /* EN, bit[0] Trace unit enable bit */ 831 control &= ~0x1; 832 833 /* 834 * If the CPU supports v8.4 Trace filter Control, 835 * set the ETM to trace prohibited region. 836 */ 837 etm4x_prohibit_trace(drvdata); 838 /* 839 * Make sure everything completes before disabling, as recommended 840 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register, 841 * SSTATUS") of ARM IHI 0064D 842 */ 843 dsb(sy); 844 isb(); 845 /* Trace synchronization barrier, is a nop if not supported */ 846 tsb_csync(); 847 etm4x_relaxed_write32(csa, control, TRCPRGCTLR); 848 849 /* wait for TRCSTATR.PMSTABLE to go to '1' */ 850 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) 851 dev_err(etm_dev, 852 "timeout while waiting for PM stable Trace Status\n"); 853 /* read the status of the single shot comparators */ 854 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 855 config->ss_status[i] = 856 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 857 } 858 859 /* read back the current counter values */ 860 for (i = 0; i < drvdata->nr_cntr; i++) { 861 config->cntr_val[i] = 862 etm4x_relaxed_read32(csa, TRCCNTVRn(i)); 863 } 864 865 coresight_disclaim_device_unlocked(csdev); 866 etm4_cs_lock(drvdata, csa); 867 868 dev_dbg(&drvdata->csdev->dev, 869 "cpu: %d disable smp call done\n", drvdata->cpu); 870 } 871 872 static int etm4_disable_perf(struct coresight_device *csdev, 873 struct perf_event *event) 874 { 875 u32 control; 876 struct etm_filters *filters = event->hw.addr_filters; 877 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 878 struct perf_event_attr *attr = &event->attr; 879 880 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) 881 return -EINVAL; 882 883 etm4_disable_hw(drvdata); 884 /* 885 * The config_id occupies bits 63:32 of the config2 perf event attr 886 * field. If this is non-zero then we will have enabled a config. 887 */ 888 if (attr->config2 & GENMASK_ULL(63, 32)) 889 cscfg_csdev_disable_active_config(csdev); 890 891 /* 892 * Check if the start/stop logic was active when the unit was stopped. 893 * That way we can re-enable the start/stop logic when the process is 894 * scheduled again. Configuration of the start/stop logic happens in 895 * function etm4_set_event_filters(). 896 */ 897 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR); 898 /* TRCVICTLR::SSSTATUS, bit[9] */ 899 filters->ssstatus = (control & BIT(9)); 900 901 return 0; 902 } 903 904 static void etm4_disable_sysfs(struct coresight_device *csdev) 905 { 906 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 907 908 /* 909 * Taking hotplug lock here protects from clocks getting disabled 910 * with tracing being left on (crash scenario) if user disable occurs 911 * after cpu online mask indicates the cpu is offline but before the 912 * DYING hotplug callback is serviced by the ETM driver. 913 */ 914 cpus_read_lock(); 915 spin_lock(&drvdata->spinlock); 916 917 /* 918 * Executing etm4_disable_hw on the cpu whose ETM is being disabled 919 * ensures that register writes occur when cpu is powered. 920 */ 921 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); 922 923 spin_unlock(&drvdata->spinlock); 924 cpus_read_unlock(); 925 926 dev_dbg(&csdev->dev, "ETM tracing disabled\n"); 927 } 928 929 static void etm4_disable(struct coresight_device *csdev, 930 struct perf_event *event) 931 { 932 u32 mode; 933 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 934 935 /* 936 * For as long as the tracer isn't disabled another entity can't 937 * change its status. As such we can read the status here without 938 * fearing it will change under us. 939 */ 940 mode = local_read(&drvdata->mode); 941 942 switch (mode) { 943 case CS_MODE_DISABLED: 944 break; 945 case CS_MODE_SYSFS: 946 etm4_disable_sysfs(csdev); 947 break; 948 case CS_MODE_PERF: 949 etm4_disable_perf(csdev, event); 950 break; 951 } 952 953 if (mode) 954 local_set(&drvdata->mode, CS_MODE_DISABLED); 955 } 956 957 static const struct coresight_ops_source etm4_source_ops = { 958 .cpu_id = etm4_cpu_id, 959 .trace_id = etm4_trace_id, 960 .enable = etm4_enable, 961 .disable = etm4_disable, 962 }; 963 964 static const struct coresight_ops etm4_cs_ops = { 965 .source_ops = &etm4_source_ops, 966 }; 967 968 static inline bool cpu_supports_sysreg_trace(void) 969 { 970 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); 971 972 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0; 973 } 974 975 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, 976 struct csdev_access *csa) 977 { 978 u32 devarch; 979 980 if (!cpu_supports_sysreg_trace()) 981 return false; 982 983 /* 984 * ETMs implementing sysreg access must implement TRCDEVARCH. 985 */ 986 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); 987 switch (devarch & ETM_DEVARCH_ID_MASK) { 988 case ETM_DEVARCH_ETMv4x_ARCH: 989 *csa = (struct csdev_access) { 990 .io_mem = false, 991 .read = etm4x_sysreg_read, 992 .write = etm4x_sysreg_write, 993 }; 994 break; 995 case ETM_DEVARCH_ETE_ARCH: 996 *csa = (struct csdev_access) { 997 .io_mem = false, 998 .read = ete_sysreg_read, 999 .write = ete_sysreg_write, 1000 }; 1001 break; 1002 default: 1003 return false; 1004 } 1005 1006 drvdata->arch = etm_devarch_to_arch(devarch); 1007 return true; 1008 } 1009 1010 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, 1011 struct csdev_access *csa) 1012 { 1013 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH); 1014 u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1); 1015 1016 /* 1017 * All ETMs must implement TRCDEVARCH to indicate that 1018 * the component is an ETMv4. To support any broken 1019 * implementations we fall back to TRCIDR1 check, which 1020 * is not really reliable. 1021 */ 1022 if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) { 1023 drvdata->arch = etm_devarch_to_arch(devarch); 1024 } else { 1025 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n", 1026 smp_processor_id(), devarch); 1027 1028 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4) 1029 return false; 1030 drvdata->arch = etm_trcidr_to_arch(idr1); 1031 } 1032 1033 *csa = CSDEV_ACCESS_IOMEM(drvdata->base); 1034 return true; 1035 } 1036 1037 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, 1038 struct csdev_access *csa) 1039 { 1040 /* 1041 * Always choose the memory mapped io, if there is 1042 * a memory map to prevent sysreg access on broken 1043 * systems. 1044 */ 1045 if (drvdata->base) 1046 return etm4_init_iomem_access(drvdata, csa); 1047 1048 if (etm4_init_sysreg_access(drvdata, csa)) 1049 return true; 1050 1051 return false; 1052 } 1053 1054 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) 1055 { 1056 u64 dfr0 = read_sysreg(id_aa64dfr0_el1); 1057 u64 trfcr; 1058 1059 drvdata->trfcr = 0; 1060 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) 1061 return; 1062 1063 /* 1064 * If the CPU supports v8.4 SelfHosted Tracing, enable 1065 * tracing at the kernel EL and EL0, forcing to use the 1066 * virtual time as the timestamp. 1067 */ 1068 trfcr = (TRFCR_ELx_TS_VIRTUAL | 1069 TRFCR_ELx_ExTRE | 1070 TRFCR_ELx_E0TRE); 1071 1072 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */ 1073 if (is_kernel_in_hyp_mode()) 1074 trfcr |= TRFCR_EL2_CX; 1075 1076 drvdata->trfcr = trfcr; 1077 } 1078 1079 static void etm4_init_arch_data(void *info) 1080 { 1081 u32 etmidr0; 1082 u32 etmidr2; 1083 u32 etmidr3; 1084 u32 etmidr4; 1085 u32 etmidr5; 1086 struct etm4_init_arg *init_arg = info; 1087 struct etmv4_drvdata *drvdata; 1088 struct csdev_access *csa; 1089 int i; 1090 1091 drvdata = dev_get_drvdata(init_arg->dev); 1092 csa = init_arg->csa; 1093 1094 /* 1095 * If we are unable to detect the access mechanism, 1096 * or unable to detect the trace unit type, fail 1097 * early. 1098 */ 1099 if (!etm4_init_csdev_access(drvdata, csa)) 1100 return; 1101 1102 /* Detect the support for OS Lock before we actually use it */ 1103 etm_detect_os_lock(drvdata, csa); 1104 1105 /* Make sure all registers are accessible */ 1106 etm4_os_unlock_csa(drvdata, csa); 1107 etm4_cs_unlock(drvdata, csa); 1108 1109 etm4_check_arch_features(drvdata, init_arg->pid); 1110 1111 /* find all capabilities of the tracing unit */ 1112 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); 1113 1114 /* INSTP0, bits[2:1] P0 tracing support field */ 1115 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11); 1116 /* TRCBB, bit[5] Branch broadcast tracing support bit */ 1117 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); 1118 /* TRCCOND, bit[6] Conditional instruction tracing support bit */ 1119 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); 1120 /* TRCCCI, bit[7] Cycle counting instruction bit */ 1121 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); 1122 /* RETSTACK, bit[9] Return stack bit */ 1123 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); 1124 /* NUMEVENT, bits[11:10] Number of events field */ 1125 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); 1126 /* QSUPP, bits[16:15] Q element support field */ 1127 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); 1128 /* TSSIZE, bits[28:24] Global timestamp size field */ 1129 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0); 1130 1131 /* maximum size of resources */ 1132 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); 1133 /* CIDSIZE, bits[9:5] Indicates the Context ID size */ 1134 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); 1135 /* VMIDSIZE, bits[14:10] Indicates the VMID size */ 1136 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); 1137 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ 1138 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2); 1139 1140 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); 1141 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ 1142 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); 1143 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ 1144 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); 1145 drvdata->config.s_ex_level = drvdata->s_ex_level; 1146 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ 1147 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); 1148 /* 1149 * TRCERR, bit[24] whether a trace unit can trace a 1150 * system error exception. 1151 */ 1152 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR); 1153 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ 1154 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR); 1155 /* STALLCTL, bit[26] is stall control implemented? */ 1156 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL); 1157 /* SYSSTALL, bit[27] implementation can support stall control? */ 1158 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL); 1159 /* 1160 * NUMPROC - the number of PEs available for tracing, 5bits 1161 * = TRCIDR3.bits[13:12]bits[30:28] 1162 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0) 1163 * bits[3:0] = TRCIDR3.bits[30:28] 1164 */ 1165 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) | 1166 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3); 1167 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ 1168 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW); 1169 1170 /* number of resources trace unit supports */ 1171 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); 1172 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ 1173 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); 1174 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ 1175 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); 1176 /* 1177 * NUMRSPAIR, bits[19:16] 1178 * The number of resource pairs conveyed by the HW starts at 0, i.e a 1179 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on. 1180 * As such add 1 to the value of NUMRSPAIR for a better representation. 1181 * 1182 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available - 1183 * the default TRUE and FALSE resource selectors are omitted. 1184 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. 1185 */ 1186 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); 1187 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) 1188 drvdata->nr_resource += 1; 1189 /* 1190 * NUMSSCC, bits[23:20] the number of single-shot 1191 * comparator control for tracing. Read any status regs as these 1192 * also contain RO capability data. 1193 */ 1194 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); 1195 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1196 drvdata->config.ss_status[i] = 1197 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 1198 } 1199 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ 1200 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); 1201 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ 1202 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4); 1203 1204 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); 1205 /* NUMEXTIN, bits[8:0] number of external inputs implemented */ 1206 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); 1207 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ 1208 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); 1209 /* ATBTRIG, bit[22] implementation can support ATB triggers? */ 1210 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); 1211 /* 1212 * LPOVERRIDE, bit[23] implementation supports 1213 * low-power state override 1214 */ 1215 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up); 1216 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ 1217 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); 1218 /* NUMCNTR, bits[30:28] number of counters available for tracing */ 1219 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); 1220 etm4_cs_lock(drvdata, csa); 1221 cpu_detect_trace_filtering(drvdata); 1222 } 1223 1224 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) 1225 { 1226 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK); 1227 } 1228 1229 /* Set ELx trace filter access in the TRCVICTLR register */ 1230 static void etm4_set_victlr_access(struct etmv4_config *config) 1231 { 1232 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK; 1233 config->vinst_ctrl |= etm4_get_victlr_access_type(config); 1234 } 1235 1236 static void etm4_set_default_config(struct etmv4_config *config) 1237 { 1238 /* disable all events tracing */ 1239 config->eventctrl0 = 0x0; 1240 config->eventctrl1 = 0x0; 1241 1242 /* disable stalling */ 1243 config->stall_ctrl = 0x0; 1244 1245 /* enable trace synchronization every 4096 bytes, if available */ 1246 config->syncfreq = 0xC; 1247 1248 /* disable timestamp event */ 1249 config->ts_ctrl = 0x0; 1250 1251 /* TRCVICTLR::EVENT = 0x01, select the always on logic */ 1252 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01); 1253 1254 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ 1255 etm4_set_victlr_access(config); 1256 } 1257 1258 static u64 etm4_get_ns_access_type(struct etmv4_config *config) 1259 { 1260 u64 access_type = 0; 1261 1262 /* 1263 * EXLEVEL_NS, for NonSecure Exception levels. 1264 * The mask here is a generic value and must be 1265 * shifted to the corresponding field for the registers 1266 */ 1267 if (!is_kernel_in_hyp_mode()) { 1268 /* Stay away from hypervisor mode for non-VHE */ 1269 access_type = ETM_EXLEVEL_NS_HYP; 1270 if (config->mode & ETM_MODE_EXCL_KERN) 1271 access_type |= ETM_EXLEVEL_NS_OS; 1272 } else if (config->mode & ETM_MODE_EXCL_KERN) { 1273 access_type = ETM_EXLEVEL_NS_HYP; 1274 } 1275 1276 if (config->mode & ETM_MODE_EXCL_USER) 1277 access_type |= ETM_EXLEVEL_NS_APP; 1278 1279 return access_type; 1280 } 1281 1282 /* 1283 * Construct the exception level masks for a given config. 1284 * This must be shifted to the corresponding register field 1285 * for usage. 1286 */ 1287 static u64 etm4_get_access_type(struct etmv4_config *config) 1288 { 1289 /* All Secure exception levels are excluded from the trace */ 1290 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level; 1291 } 1292 1293 static u64 etm4_get_comparator_access_type(struct etmv4_config *config) 1294 { 1295 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT; 1296 } 1297 1298 static void etm4_set_comparator_filter(struct etmv4_config *config, 1299 u64 start, u64 stop, int comparator) 1300 { 1301 u64 access_type = etm4_get_comparator_access_type(config); 1302 1303 /* First half of default address comparator */ 1304 config->addr_val[comparator] = start; 1305 config->addr_acc[comparator] = access_type; 1306 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE; 1307 1308 /* Second half of default address comparator */ 1309 config->addr_val[comparator + 1] = stop; 1310 config->addr_acc[comparator + 1] = access_type; 1311 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE; 1312 1313 /* 1314 * Configure the ViewInst function to include this address range 1315 * comparator. 1316 * 1317 * @comparator is divided by two since it is the index in the 1318 * etmv4_config::addr_val array but register TRCVIIECTLR deals with 1319 * address range comparator _pairs_. 1320 * 1321 * Therefore: 1322 * index 0 -> compatator pair 0 1323 * index 2 -> comparator pair 1 1324 * index 4 -> comparator pair 2 1325 * ... 1326 * index 14 -> comparator pair 7 1327 */ 1328 config->viiectlr |= BIT(comparator / 2); 1329 } 1330 1331 static void etm4_set_start_stop_filter(struct etmv4_config *config, 1332 u64 address, int comparator, 1333 enum etm_addr_type type) 1334 { 1335 int shift; 1336 u64 access_type = etm4_get_comparator_access_type(config); 1337 1338 /* Configure the comparator */ 1339 config->addr_val[comparator] = address; 1340 config->addr_acc[comparator] = access_type; 1341 config->addr_type[comparator] = type; 1342 1343 /* 1344 * Configure ViewInst Start-Stop control register. 1345 * Addresses configured to start tracing go from bit 0 to n-1, 1346 * while those configured to stop tracing from 16 to 16 + n-1. 1347 */ 1348 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16); 1349 config->vissctlr |= BIT(shift + comparator); 1350 } 1351 1352 static void etm4_set_default_filter(struct etmv4_config *config) 1353 { 1354 /* Trace everything 'default' filter achieved by no filtering */ 1355 config->viiectlr = 0x0; 1356 1357 /* 1358 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1359 * in the started state 1360 */ 1361 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1362 config->mode |= ETM_MODE_VIEWINST_STARTSTOP; 1363 1364 /* No start-stop filtering for ViewInst */ 1365 config->vissctlr = 0x0; 1366 } 1367 1368 static void etm4_set_default(struct etmv4_config *config) 1369 { 1370 if (WARN_ON_ONCE(!config)) 1371 return; 1372 1373 /* 1374 * Make default initialisation trace everything 1375 * 1376 * This is done by a minimum default config sufficient to enable 1377 * full instruction trace - with a default filter for trace all 1378 * achieved by having no filtering. 1379 */ 1380 etm4_set_default_config(config); 1381 etm4_set_default_filter(config); 1382 } 1383 1384 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) 1385 { 1386 int nr_comparator, index = 0; 1387 struct etmv4_config *config = &drvdata->config; 1388 1389 /* 1390 * nr_addr_cmp holds the number of comparator _pair_, so time 2 1391 * for the total number of comparators. 1392 */ 1393 nr_comparator = drvdata->nr_addr_cmp * 2; 1394 1395 /* Go through the tally of comparators looking for a free one. */ 1396 while (index < nr_comparator) { 1397 switch (type) { 1398 case ETM_ADDR_TYPE_RANGE: 1399 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE && 1400 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE) 1401 return index; 1402 1403 /* Address range comparators go in pairs */ 1404 index += 2; 1405 break; 1406 case ETM_ADDR_TYPE_START: 1407 case ETM_ADDR_TYPE_STOP: 1408 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE) 1409 return index; 1410 1411 /* Start/stop address can have odd indexes */ 1412 index += 1; 1413 break; 1414 default: 1415 return -EINVAL; 1416 } 1417 } 1418 1419 /* If we are here all the comparators have been used. */ 1420 return -ENOSPC; 1421 } 1422 1423 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 1424 struct perf_event *event) 1425 { 1426 int i, comparator, ret = 0; 1427 u64 address; 1428 struct etmv4_config *config = &drvdata->config; 1429 struct etm_filters *filters = event->hw.addr_filters; 1430 1431 if (!filters) 1432 goto default_filter; 1433 1434 /* Sync events with what Perf got */ 1435 perf_event_addr_filters_sync(event); 1436 1437 /* 1438 * If there are no filters to deal with simply go ahead with 1439 * the default filter, i.e the entire address range. 1440 */ 1441 if (!filters->nr_filters) 1442 goto default_filter; 1443 1444 for (i = 0; i < filters->nr_filters; i++) { 1445 struct etm_filter *filter = &filters->etm_filter[i]; 1446 enum etm_addr_type type = filter->type; 1447 1448 /* See if a comparator is free. */ 1449 comparator = etm4_get_next_comparator(drvdata, type); 1450 if (comparator < 0) { 1451 ret = comparator; 1452 goto out; 1453 } 1454 1455 switch (type) { 1456 case ETM_ADDR_TYPE_RANGE: 1457 etm4_set_comparator_filter(config, 1458 filter->start_addr, 1459 filter->stop_addr, 1460 comparator); 1461 /* 1462 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1463 * in the started state 1464 */ 1465 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1466 1467 /* No start-stop filtering for ViewInst */ 1468 config->vissctlr = 0x0; 1469 break; 1470 case ETM_ADDR_TYPE_START: 1471 case ETM_ADDR_TYPE_STOP: 1472 /* Get the right start or stop address */ 1473 address = (type == ETM_ADDR_TYPE_START ? 1474 filter->start_addr : 1475 filter->stop_addr); 1476 1477 /* Configure comparator */ 1478 etm4_set_start_stop_filter(config, address, 1479 comparator, type); 1480 1481 /* 1482 * If filters::ssstatus == 1, trace acquisition was 1483 * started but the process was yanked away before the 1484 * stop address was hit. As such the start/stop 1485 * logic needs to be re-started so that tracing can 1486 * resume where it left. 1487 * 1488 * The start/stop logic status when a process is 1489 * scheduled out is checked in function 1490 * etm4_disable_perf(). 1491 */ 1492 if (filters->ssstatus) 1493 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1494 1495 /* No include/exclude filtering for ViewInst */ 1496 config->viiectlr = 0x0; 1497 break; 1498 default: 1499 ret = -EINVAL; 1500 goto out; 1501 } 1502 } 1503 1504 goto out; 1505 1506 1507 default_filter: 1508 etm4_set_default_filter(config); 1509 1510 out: 1511 return ret; 1512 } 1513 1514 void etm4_config_trace_mode(struct etmv4_config *config) 1515 { 1516 u32 mode; 1517 1518 mode = config->mode; 1519 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); 1520 1521 /* excluding kernel AND user space doesn't make sense */ 1522 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)); 1523 1524 /* nothing to do if neither flags are set */ 1525 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) 1526 return; 1527 1528 etm4_set_victlr_access(config); 1529 } 1530 1531 static int etm4_online_cpu(unsigned int cpu) 1532 { 1533 if (!etmdrvdata[cpu]) 1534 return etm4_probe_cpu(cpu); 1535 1536 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) 1537 coresight_enable(etmdrvdata[cpu]->csdev); 1538 return 0; 1539 } 1540 1541 static int etm4_starting_cpu(unsigned int cpu) 1542 { 1543 if (!etmdrvdata[cpu]) 1544 return 0; 1545 1546 spin_lock(&etmdrvdata[cpu]->spinlock); 1547 if (!etmdrvdata[cpu]->os_unlock) 1548 etm4_os_unlock(etmdrvdata[cpu]); 1549 1550 if (local_read(&etmdrvdata[cpu]->mode)) 1551 etm4_enable_hw(etmdrvdata[cpu]); 1552 spin_unlock(&etmdrvdata[cpu]->spinlock); 1553 return 0; 1554 } 1555 1556 static int etm4_dying_cpu(unsigned int cpu) 1557 { 1558 if (!etmdrvdata[cpu]) 1559 return 0; 1560 1561 spin_lock(&etmdrvdata[cpu]->spinlock); 1562 if (local_read(&etmdrvdata[cpu]->mode)) 1563 etm4_disable_hw(etmdrvdata[cpu]); 1564 spin_unlock(&etmdrvdata[cpu]->spinlock); 1565 return 0; 1566 } 1567 1568 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) 1569 { 1570 drvdata->trcid = coresight_get_trace_id(drvdata->cpu); 1571 } 1572 1573 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) 1574 { 1575 int i, ret = 0; 1576 struct etmv4_save_state *state; 1577 struct coresight_device *csdev = drvdata->csdev; 1578 struct csdev_access *csa; 1579 struct device *etm_dev; 1580 1581 if (WARN_ON(!csdev)) 1582 return -ENODEV; 1583 1584 etm_dev = &csdev->dev; 1585 csa = &csdev->access; 1586 1587 /* 1588 * As recommended by 3.4.1 ("The procedure when powering down the PE") 1589 * of ARM IHI 0064D 1590 */ 1591 dsb(sy); 1592 isb(); 1593 1594 etm4_cs_unlock(drvdata, csa); 1595 /* Lock the OS lock to disable trace and external debugger access */ 1596 etm4_os_lock(drvdata); 1597 1598 /* wait for TRCSTATR.PMSTABLE to go up */ 1599 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) { 1600 dev_err(etm_dev, 1601 "timeout while waiting for PM Stable Status\n"); 1602 etm4_os_unlock(drvdata); 1603 ret = -EBUSY; 1604 goto out; 1605 } 1606 1607 state = drvdata->save_state; 1608 1609 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR); 1610 if (drvdata->nr_pe) 1611 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); 1612 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); 1613 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); 1614 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); 1615 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); 1616 if (drvdata->stallctl) 1617 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); 1618 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); 1619 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); 1620 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); 1621 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); 1622 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); 1623 state->trcqctlr = etm4x_read32(csa, TRCQCTLR); 1624 1625 state->trcvictlr = etm4x_read32(csa, TRCVICTLR); 1626 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); 1627 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); 1628 if (drvdata->nr_pe_cmp) 1629 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); 1630 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR); 1631 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR); 1632 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR); 1633 1634 for (i = 0; i < drvdata->nrseqstate - 1; i++) 1635 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); 1636 1637 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); 1638 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); 1639 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); 1640 1641 for (i = 0; i < drvdata->nr_cntr; i++) { 1642 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); 1643 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); 1644 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); 1645 } 1646 1647 for (i = 0; i < drvdata->nr_resource * 2; i++) 1648 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i)); 1649 1650 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1651 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); 1652 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); 1653 if (etm4x_sspcicrn_present(drvdata, i)) 1654 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); 1655 } 1656 1657 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 1658 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); 1659 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); 1660 } 1661 1662 /* 1663 * Data trace stream is architecturally prohibited for A profile cores 1664 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per 1665 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace 1666 * unit") of ARM IHI 0064D. 1667 */ 1668 1669 for (i = 0; i < drvdata->numcidc; i++) 1670 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); 1671 1672 for (i = 0; i < drvdata->numvmidc; i++) 1673 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); 1674 1675 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); 1676 if (drvdata->numcidc > 4) 1677 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1); 1678 1679 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); 1680 if (drvdata->numvmidc > 4) 1681 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); 1682 1683 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR); 1684 1685 if (!drvdata->skip_power_up) 1686 state->trcpdcr = etm4x_read32(csa, TRCPDCR); 1687 1688 /* wait for TRCSTATR.IDLE to go up */ 1689 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { 1690 dev_err(etm_dev, 1691 "timeout while waiting for Idle Trace Status\n"); 1692 etm4_os_unlock(drvdata); 1693 ret = -EBUSY; 1694 goto out; 1695 } 1696 1697 drvdata->state_needs_restore = true; 1698 1699 /* 1700 * Power can be removed from the trace unit now. We do this to 1701 * potentially save power on systems that respect the TRCPDCR_PU 1702 * despite requesting software to save/restore state. 1703 */ 1704 if (!drvdata->skip_power_up) 1705 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), 1706 TRCPDCR); 1707 out: 1708 etm4_cs_lock(drvdata, csa); 1709 return ret; 1710 } 1711 1712 static int etm4_cpu_save(struct etmv4_drvdata *drvdata) 1713 { 1714 int ret = 0; 1715 1716 /* Save the TRFCR irrespective of whether the ETM is ON */ 1717 if (drvdata->trfcr) 1718 drvdata->save_trfcr = read_trfcr(); 1719 /* 1720 * Save and restore the ETM Trace registers only if 1721 * the ETM is active. 1722 */ 1723 if (local_read(&drvdata->mode) && drvdata->save_state) 1724 ret = __etm4_cpu_save(drvdata); 1725 return ret; 1726 } 1727 1728 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) 1729 { 1730 int i; 1731 struct etmv4_save_state *state = drvdata->save_state; 1732 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); 1733 struct csdev_access *csa = &tmp_csa; 1734 1735 etm4_cs_unlock(drvdata, csa); 1736 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 1737 1738 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); 1739 if (drvdata->nr_pe) 1740 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); 1741 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); 1742 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); 1743 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); 1744 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); 1745 if (drvdata->stallctl) 1746 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); 1747 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); 1748 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); 1749 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); 1750 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); 1751 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); 1752 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); 1753 1754 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); 1755 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); 1756 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); 1757 if (drvdata->nr_pe_cmp) 1758 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); 1759 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR); 1760 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR); 1761 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR); 1762 1763 for (i = 0; i < drvdata->nrseqstate - 1; i++) 1764 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); 1765 1766 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); 1767 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); 1768 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); 1769 1770 for (i = 0; i < drvdata->nr_cntr; i++) { 1771 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); 1772 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); 1773 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); 1774 } 1775 1776 for (i = 0; i < drvdata->nr_resource * 2; i++) 1777 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); 1778 1779 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1780 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); 1781 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); 1782 if (etm4x_sspcicrn_present(drvdata, i)) 1783 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); 1784 } 1785 1786 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 1787 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); 1788 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); 1789 } 1790 1791 for (i = 0; i < drvdata->numcidc; i++) 1792 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); 1793 1794 for (i = 0; i < drvdata->numvmidc; i++) 1795 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); 1796 1797 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); 1798 if (drvdata->numcidc > 4) 1799 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); 1800 1801 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); 1802 if (drvdata->numvmidc > 4) 1803 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); 1804 1805 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 1806 1807 if (!drvdata->skip_power_up) 1808 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); 1809 1810 drvdata->state_needs_restore = false; 1811 1812 /* 1813 * As recommended by section 4.3.7 ("Synchronization when using the 1814 * memory-mapped interface") of ARM IHI 0064D 1815 */ 1816 dsb(sy); 1817 isb(); 1818 1819 /* Unlock the OS lock to re-enable trace and external debug access */ 1820 etm4_os_unlock(drvdata); 1821 etm4_cs_lock(drvdata, csa); 1822 } 1823 1824 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) 1825 { 1826 if (drvdata->trfcr) 1827 write_trfcr(drvdata->save_trfcr); 1828 if (drvdata->state_needs_restore) 1829 __etm4_cpu_restore(drvdata); 1830 } 1831 1832 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, 1833 void *v) 1834 { 1835 struct etmv4_drvdata *drvdata; 1836 unsigned int cpu = smp_processor_id(); 1837 1838 if (!etmdrvdata[cpu]) 1839 return NOTIFY_OK; 1840 1841 drvdata = etmdrvdata[cpu]; 1842 1843 if (WARN_ON_ONCE(drvdata->cpu != cpu)) 1844 return NOTIFY_BAD; 1845 1846 switch (cmd) { 1847 case CPU_PM_ENTER: 1848 if (etm4_cpu_save(drvdata)) 1849 return NOTIFY_BAD; 1850 break; 1851 case CPU_PM_EXIT: 1852 case CPU_PM_ENTER_FAILED: 1853 etm4_cpu_restore(drvdata); 1854 break; 1855 default: 1856 return NOTIFY_DONE; 1857 } 1858 1859 return NOTIFY_OK; 1860 } 1861 1862 static struct notifier_block etm4_cpu_pm_nb = { 1863 .notifier_call = etm4_cpu_pm_notify, 1864 }; 1865 1866 /* Setup PM. Deals with error conditions and counts */ 1867 static int __init etm4_pm_setup(void) 1868 { 1869 int ret; 1870 1871 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb); 1872 if (ret) 1873 return ret; 1874 1875 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING, 1876 "arm/coresight4:starting", 1877 etm4_starting_cpu, etm4_dying_cpu); 1878 1879 if (ret) 1880 goto unregister_notifier; 1881 1882 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, 1883 "arm/coresight4:online", 1884 etm4_online_cpu, NULL); 1885 1886 /* HP dyn state ID returned in ret on success */ 1887 if (ret > 0) { 1888 hp_online = ret; 1889 return 0; 1890 } 1891 1892 /* failed dyn state - remove others */ 1893 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 1894 1895 unregister_notifier: 1896 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 1897 return ret; 1898 } 1899 1900 static void etm4_pm_clear(void) 1901 { 1902 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 1903 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 1904 if (hp_online) { 1905 cpuhp_remove_state_nocalls(hp_online); 1906 hp_online = 0; 1907 } 1908 } 1909 1910 static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) 1911 { 1912 int ret; 1913 struct coresight_platform_data *pdata = NULL; 1914 struct device *dev = init_arg->dev; 1915 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 1916 struct coresight_desc desc = { 0 }; 1917 u8 major, minor; 1918 char *type_name; 1919 1920 if (!drvdata) 1921 return -EINVAL; 1922 1923 desc.access = *init_arg->csa; 1924 1925 if (!drvdata->arch) 1926 return -EINVAL; 1927 1928 /* TRCPDCR is not accessible with system instructions. */ 1929 if (!desc.access.io_mem || 1930 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) 1931 drvdata->skip_power_up = true; 1932 1933 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch); 1934 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch); 1935 1936 if (etm4x_is_ete(drvdata)) { 1937 type_name = "ete"; 1938 /* ETE v1 has major version == 0b101. Adjust this for logging.*/ 1939 major -= 4; 1940 } else { 1941 type_name = "etm"; 1942 } 1943 1944 desc.name = devm_kasprintf(dev, GFP_KERNEL, 1945 "%s%d", type_name, drvdata->cpu); 1946 if (!desc.name) 1947 return -ENOMEM; 1948 1949 etm4_init_trace_id(drvdata); 1950 etm4_set_default(&drvdata->config); 1951 1952 pdata = coresight_get_platform_data(dev); 1953 if (IS_ERR(pdata)) 1954 return PTR_ERR(pdata); 1955 1956 dev->platform_data = pdata; 1957 1958 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 1959 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; 1960 desc.ops = &etm4_cs_ops; 1961 desc.pdata = pdata; 1962 desc.dev = dev; 1963 desc.groups = coresight_etmv4_groups; 1964 drvdata->csdev = coresight_register(&desc); 1965 if (IS_ERR(drvdata->csdev)) 1966 return PTR_ERR(drvdata->csdev); 1967 1968 ret = etm_perf_symlink(drvdata->csdev, true); 1969 if (ret) { 1970 coresight_unregister(drvdata->csdev); 1971 return ret; 1972 } 1973 1974 /* register with config infrastructure & load any current features */ 1975 ret = etm4_cscfg_register(drvdata->csdev); 1976 if (ret) { 1977 coresight_unregister(drvdata->csdev); 1978 return ret; 1979 } 1980 1981 etmdrvdata[drvdata->cpu] = drvdata; 1982 1983 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n", 1984 drvdata->cpu, type_name, major, minor); 1985 1986 if (boot_enable) { 1987 coresight_enable(drvdata->csdev); 1988 drvdata->boot_enable = true; 1989 } 1990 1991 return 0; 1992 } 1993 1994 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) 1995 { 1996 struct etmv4_drvdata *drvdata; 1997 struct csdev_access access = { 0 }; 1998 struct etm4_init_arg init_arg = { 0 }; 1999 struct etm4_init_arg *delayed; 2000 2001 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 2002 if (!drvdata) 2003 return -ENOMEM; 2004 2005 dev_set_drvdata(dev, drvdata); 2006 2007 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) 2008 pm_save_enable = coresight_loses_context_with_cpu(dev) ? 2009 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; 2010 2011 if (pm_save_enable != PARAM_PM_SAVE_NEVER) { 2012 drvdata->save_state = devm_kmalloc(dev, 2013 sizeof(struct etmv4_save_state), GFP_KERNEL); 2014 if (!drvdata->save_state) 2015 return -ENOMEM; 2016 } 2017 2018 drvdata->base = base; 2019 2020 spin_lock_init(&drvdata->spinlock); 2021 2022 drvdata->cpu = coresight_get_cpu(dev); 2023 if (drvdata->cpu < 0) 2024 return drvdata->cpu; 2025 2026 init_arg.dev = dev; 2027 init_arg.csa = &access; 2028 init_arg.pid = etm_pid; 2029 2030 /* 2031 * Serialize against CPUHP callbacks to avoid race condition 2032 * between the smp call and saving the delayed probe. 2033 */ 2034 cpus_read_lock(); 2035 if (smp_call_function_single(drvdata->cpu, 2036 etm4_init_arch_data, &init_arg, 1)) { 2037 /* The CPU was offline, try again once it comes online. */ 2038 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); 2039 if (!delayed) { 2040 cpus_read_unlock(); 2041 return -ENOMEM; 2042 } 2043 2044 *delayed = init_arg; 2045 2046 per_cpu(delayed_probe, drvdata->cpu) = delayed; 2047 2048 cpus_read_unlock(); 2049 return 0; 2050 } 2051 cpus_read_unlock(); 2052 2053 return etm4_add_coresight_dev(&init_arg); 2054 } 2055 2056 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) 2057 { 2058 void __iomem *base; 2059 struct device *dev = &adev->dev; 2060 struct resource *res = &adev->res; 2061 int ret; 2062 2063 /* Validity for the resource is already checked by the AMBA core */ 2064 base = devm_ioremap_resource(dev, res); 2065 if (IS_ERR(base)) 2066 return PTR_ERR(base); 2067 2068 ret = etm4_probe(dev, base, id->id); 2069 if (!ret) 2070 pm_runtime_put(&adev->dev); 2071 2072 return ret; 2073 } 2074 2075 static int etm4_probe_platform_dev(struct platform_device *pdev) 2076 { 2077 int ret; 2078 2079 pm_runtime_get_noresume(&pdev->dev); 2080 pm_runtime_set_active(&pdev->dev); 2081 pm_runtime_enable(&pdev->dev); 2082 2083 /* 2084 * System register based devices could match the 2085 * HW by reading appropriate registers on the HW 2086 * and thus we could skip the PID. 2087 */ 2088 ret = etm4_probe(&pdev->dev, NULL, 0); 2089 2090 pm_runtime_put(&pdev->dev); 2091 return ret; 2092 } 2093 2094 static int etm4_probe_cpu(unsigned int cpu) 2095 { 2096 int ret; 2097 struct etm4_init_arg init_arg; 2098 struct csdev_access access = { 0 }; 2099 struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe); 2100 2101 if (!iap) 2102 return 0; 2103 2104 init_arg = *iap; 2105 devm_kfree(init_arg.dev, iap); 2106 *this_cpu_ptr(&delayed_probe) = NULL; 2107 2108 ret = pm_runtime_resume_and_get(init_arg.dev); 2109 if (ret < 0) { 2110 dev_err(init_arg.dev, "Failed to get PM runtime!\n"); 2111 return 0; 2112 } 2113 2114 init_arg.csa = &access; 2115 etm4_init_arch_data(&init_arg); 2116 2117 etm4_add_coresight_dev(&init_arg); 2118 2119 pm_runtime_put(init_arg.dev); 2120 return 0; 2121 } 2122 2123 static struct amba_cs_uci_id uci_id_etm4[] = { 2124 { 2125 /* ETMv4 UCI data */ 2126 .devarch = ETM_DEVARCH_ETMv4x_ARCH, 2127 .devarch_mask = ETM_DEVARCH_ID_MASK, 2128 .devtype = 0x00000013, 2129 } 2130 }; 2131 2132 static void clear_etmdrvdata(void *info) 2133 { 2134 int cpu = *(int *)info; 2135 2136 etmdrvdata[cpu] = NULL; 2137 per_cpu(delayed_probe, cpu) = NULL; 2138 } 2139 2140 static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) 2141 { 2142 bool had_delayed_probe; 2143 /* 2144 * Taking hotplug lock here to avoid racing between etm4_remove_dev() 2145 * and CPU hotplug call backs. 2146 */ 2147 cpus_read_lock(); 2148 2149 had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu); 2150 2151 /* 2152 * The readers for etmdrvdata[] are CPU hotplug call backs 2153 * and PM notification call backs. Change etmdrvdata[i] on 2154 * CPU i ensures these call backs has consistent view 2155 * inside one call back function. 2156 */ 2157 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) 2158 clear_etmdrvdata(&drvdata->cpu); 2159 2160 cpus_read_unlock(); 2161 2162 if (!had_delayed_probe) { 2163 etm_perf_symlink(drvdata->csdev, false); 2164 cscfg_unregister_csdev(drvdata->csdev); 2165 coresight_unregister(drvdata->csdev); 2166 } 2167 2168 return 0; 2169 } 2170 2171 static void __exit etm4_remove_amba(struct amba_device *adev) 2172 { 2173 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev); 2174 2175 if (drvdata) 2176 etm4_remove_dev(drvdata); 2177 } 2178 2179 static int __exit etm4_remove_platform_dev(struct platform_device *pdev) 2180 { 2181 int ret = 0; 2182 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 2183 2184 if (drvdata) 2185 ret = etm4_remove_dev(drvdata); 2186 pm_runtime_disable(&pdev->dev); 2187 return ret; 2188 } 2189 2190 static const struct amba_id etm4_ids[] = { 2191 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ 2192 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ 2193 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ 2194 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ 2195 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ 2196 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ 2197 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ 2198 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ 2199 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */ 2200 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ 2201 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ 2202 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */ 2203 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ 2204 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ 2205 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ 2206 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */ 2207 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ 2208 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ 2209 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ 2210 {}, 2211 }; 2212 2213 MODULE_DEVICE_TABLE(amba, etm4_ids); 2214 2215 static struct amba_driver etm4x_amba_driver = { 2216 .drv = { 2217 .name = "coresight-etm4x", 2218 .owner = THIS_MODULE, 2219 .suppress_bind_attrs = true, 2220 }, 2221 .probe = etm4_probe_amba, 2222 .remove = etm4_remove_amba, 2223 .id_table = etm4_ids, 2224 }; 2225 2226 static const struct of_device_id etm4_sysreg_match[] = { 2227 { .compatible = "arm,coresight-etm4x-sysreg" }, 2228 { .compatible = "arm,embedded-trace-extension" }, 2229 {} 2230 }; 2231 2232 static struct platform_driver etm4_platform_driver = { 2233 .probe = etm4_probe_platform_dev, 2234 .remove = etm4_remove_platform_dev, 2235 .driver = { 2236 .name = "coresight-etm4x", 2237 .of_match_table = etm4_sysreg_match, 2238 .suppress_bind_attrs = true, 2239 }, 2240 }; 2241 2242 static int __init etm4x_init(void) 2243 { 2244 int ret; 2245 2246 ret = etm4_pm_setup(); 2247 2248 /* etm4_pm_setup() does its own cleanup - exit on error */ 2249 if (ret) 2250 return ret; 2251 2252 ret = amba_driver_register(&etm4x_amba_driver); 2253 if (ret) { 2254 pr_err("Error registering etm4x AMBA driver\n"); 2255 goto clear_pm; 2256 } 2257 2258 ret = platform_driver_register(&etm4_platform_driver); 2259 if (!ret) 2260 return 0; 2261 2262 pr_err("Error registering etm4x platform driver\n"); 2263 amba_driver_unregister(&etm4x_amba_driver); 2264 2265 clear_pm: 2266 etm4_pm_clear(); 2267 return ret; 2268 } 2269 2270 static void __exit etm4x_exit(void) 2271 { 2272 amba_driver_unregister(&etm4x_amba_driver); 2273 platform_driver_unregister(&etm4_platform_driver); 2274 etm4_pm_clear(); 2275 } 2276 2277 module_init(etm4x_init); 2278 module_exit(etm4x_exit); 2279 2280 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 2281 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>"); 2282 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver"); 2283 MODULE_LICENSE("GPL v2"); 2284