1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/acpi.h> 7 #include <linux/bitops.h> 8 #include <linux/kernel.h> 9 #include <linux/moduleparam.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/err.h> 15 #include <linux/fs.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 #include <linux/smp.h> 19 #include <linux/sysfs.h> 20 #include <linux/stat.h> 21 #include <linux/clk.h> 22 #include <linux/cpu.h> 23 #include <linux/cpu_pm.h> 24 #include <linux/coresight.h> 25 #include <linux/coresight-pmu.h> 26 #include <linux/pm_wakeup.h> 27 #include <linux/amba/bus.h> 28 #include <linux/seq_file.h> 29 #include <linux/uaccess.h> 30 #include <linux/perf_event.h> 31 #include <linux/platform_device.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/property.h> 34 #include <linux/clk/clk-conf.h> 35 36 #include <asm/barrier.h> 37 #include <asm/sections.h> 38 #include <asm/sysreg.h> 39 #include <asm/local.h> 40 #include <asm/virt.h> 41 42 #include "coresight-etm4x.h" 43 #include "coresight-etm-perf.h" 44 #include "coresight-etm4x-cfg.h" 45 #include "coresight-self-hosted-trace.h" 46 #include "coresight-syscfg.h" 47 #include "coresight-trace-id.h" 48 49 static int boot_enable; 50 module_param(boot_enable, int, 0444); 51 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); 52 53 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */ 54 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */ 55 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ 56 57 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; 58 module_param(pm_save_enable, int, 0444); 59 MODULE_PARM_DESC(pm_save_enable, 60 "Save/restore state on power down: 1 = never, 2 = self-hosted"); 61 62 static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; 63 static void etm4_set_default_config(struct etmv4_config *config); 64 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 65 struct perf_event *event); 66 static u64 etm4_get_access_type(struct etmv4_config *config); 67 68 static enum cpuhp_state hp_online; 69 70 struct etm4_init_arg { 71 struct device *dev; 72 struct csdev_access *csa; 73 }; 74 75 static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe); 76 static int etm4_probe_cpu(unsigned int cpu); 77 78 /* 79 * Check if TRCSSPCICRn(i) is implemented for a given instance. 80 * 81 * TRCSSPCICRn is implemented only if : 82 * TRCSSPCICR<n> is present only if all of the following are true: 83 * TRCIDR4.NUMSSCC > n. 84 * TRCIDR4.NUMPC > 0b0000 . 85 * TRCSSCSR<n>.PC == 0b1 86 */ 87 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) 88 { 89 return (n < drvdata->nr_ss_cmp) && 90 drvdata->nr_pe && 91 (drvdata->config.ss_status[n] & TRCSSCSRn_PC); 92 } 93 94 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) 95 { 96 u64 res = 0; 97 98 switch (offset) { 99 ETM4x_READ_SYSREG_CASES(res) 100 default : 101 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n", 102 offset); 103 } 104 105 if (!_relaxed) 106 __io_ar(res); /* Imitate the !relaxed I/O helpers */ 107 108 return res; 109 } 110 111 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) 112 { 113 if (!_relaxed) 114 __io_bw(); /* Imitate the !relaxed I/O helpers */ 115 if (!_64bit) 116 val &= GENMASK(31, 0); 117 118 switch (offset) { 119 ETM4x_WRITE_SYSREG_CASES(val) 120 default : 121 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n", 122 offset); 123 } 124 } 125 126 static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit) 127 { 128 u64 res = 0; 129 130 switch (offset) { 131 ETE_READ_CASES(res) 132 default : 133 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n", 134 offset); 135 } 136 137 if (!_relaxed) 138 __io_ar(res); /* Imitate the !relaxed I/O helpers */ 139 140 return res; 141 } 142 143 static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) 144 { 145 if (!_relaxed) 146 __io_bw(); /* Imitate the !relaxed I/O helpers */ 147 if (!_64bit) 148 val &= GENMASK(31, 0); 149 150 switch (offset) { 151 ETE_WRITE_CASES(val) 152 default : 153 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n", 154 offset); 155 } 156 } 157 158 static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, 159 struct csdev_access *csa) 160 { 161 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR); 162 163 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr); 164 } 165 166 static void etm_write_os_lock(struct etmv4_drvdata *drvdata, 167 struct csdev_access *csa, u32 val) 168 { 169 val = !!val; 170 171 switch (drvdata->os_lock_model) { 172 case ETM_OSLOCK_PRESENT: 173 etm4x_relaxed_write32(csa, val, TRCOSLAR); 174 break; 175 case ETM_OSLOCK_PE: 176 write_sysreg_s(val, SYS_OSLAR_EL1); 177 break; 178 default: 179 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n", 180 smp_processor_id(), drvdata->os_lock_model); 181 fallthrough; 182 case ETM_OSLOCK_NI: 183 return; 184 } 185 isb(); 186 } 187 188 static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, 189 struct csdev_access *csa) 190 { 191 WARN_ON(drvdata->cpu != smp_processor_id()); 192 193 /* Writing 0 to OS Lock unlocks the trace unit registers */ 194 etm_write_os_lock(drvdata, csa, 0x0); 195 drvdata->os_unlock = true; 196 } 197 198 static void etm4_os_unlock(struct etmv4_drvdata *drvdata) 199 { 200 if (!WARN_ON(!drvdata->csdev)) 201 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access); 202 } 203 204 static void etm4_os_lock(struct etmv4_drvdata *drvdata) 205 { 206 if (WARN_ON(!drvdata->csdev)) 207 return; 208 /* Writing 0x1 to OS Lock locks the trace registers */ 209 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1); 210 drvdata->os_unlock = false; 211 } 212 213 static void etm4_cs_lock(struct etmv4_drvdata *drvdata, 214 struct csdev_access *csa) 215 { 216 /* Software Lock is only accessible via memory mapped interface */ 217 if (csa->io_mem) 218 CS_LOCK(csa->base); 219 } 220 221 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, 222 struct csdev_access *csa) 223 { 224 if (csa->io_mem) 225 CS_UNLOCK(csa->base); 226 } 227 228 static int etm4_cpu_id(struct coresight_device *csdev) 229 { 230 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 231 232 return drvdata->cpu; 233 } 234 235 int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata) 236 { 237 int trace_id; 238 239 /* 240 * This will allocate a trace ID to the cpu, 241 * or return the one currently allocated. 242 * The trace id function has its own lock 243 */ 244 trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu); 245 if (IS_VALID_CS_TRACE_ID(trace_id)) 246 drvdata->trcid = (u8)trace_id; 247 else 248 dev_err(&drvdata->csdev->dev, 249 "Failed to allocate trace ID for %s on CPU%d\n", 250 dev_name(&drvdata->csdev->dev), drvdata->cpu); 251 return trace_id; 252 } 253 254 void etm4_release_trace_id(struct etmv4_drvdata *drvdata) 255 { 256 coresight_trace_id_put_cpu_id(drvdata->cpu); 257 } 258 259 struct etm4_enable_arg { 260 struct etmv4_drvdata *drvdata; 261 int rc; 262 }; 263 264 /* 265 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs. 266 * When the CPU supports FEAT_TRF, we could move the ETM to a trace 267 * prohibited state by filtering the Exception levels via TRFCR_EL1. 268 */ 269 static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata) 270 { 271 /* If the CPU doesn't support FEAT_TRF, nothing to do */ 272 if (!drvdata->trfcr) 273 return; 274 cpu_prohibit_trace(); 275 } 276 277 /* 278 * etm4x_allow_trace - Allow CPU tracing in the respective ELs, 279 * as configured by the drvdata->config.mode for the current 280 * session. Even though we have TRCVICTLR bits to filter the 281 * trace in the ELs, it doesn't prevent the ETM from generating 282 * a packet (e.g, TraceInfo) that might contain the addresses from 283 * the excluded levels. Thus we use the additional controls provided 284 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace 285 * is generated for the excluded ELs. 286 */ 287 static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) 288 { 289 u64 trfcr = drvdata->trfcr; 290 291 /* If the CPU doesn't support FEAT_TRF, nothing to do */ 292 if (!trfcr) 293 return; 294 295 if (drvdata->config.mode & ETM_MODE_EXCL_KERN) 296 trfcr &= ~TRFCR_ELx_ExTRE; 297 if (drvdata->config.mode & ETM_MODE_EXCL_USER) 298 trfcr &= ~TRFCR_ELx_E0TRE; 299 300 write_trfcr(trfcr); 301 } 302 303 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE 304 305 #define HISI_HIP08_AMBA_ID 0x000b6d01 306 #define ETM4_AMBA_MASK 0xfffff 307 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000 308 #define HISI_HIP08_CORE_COMMIT_SHIFT 12 309 #define HISI_HIP08_CORE_COMMIT_FULL 0b00 310 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01 311 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5) 312 313 struct etm4_arch_features { 314 void (*arch_callback)(bool enable); 315 }; 316 317 static bool etm4_hisi_match_pid(unsigned int id) 318 { 319 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID; 320 } 321 322 static void etm4_hisi_config_core_commit(bool enable) 323 { 324 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 : 325 HISI_HIP08_CORE_COMMIT_FULL; 326 u64 val; 327 328 /* 329 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together 330 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01, 331 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1 332 * speed(minimun value). So bit 12 and 13 should be cleared together. 333 */ 334 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG); 335 val &= ~HISI_HIP08_CORE_COMMIT_MASK; 336 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT; 337 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG); 338 } 339 340 static struct etm4_arch_features etm4_features[] = { 341 [ETM4_IMPDEF_HISI_CORE_COMMIT] = { 342 .arch_callback = etm4_hisi_config_core_commit, 343 }, 344 {}, 345 }; 346 347 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 348 { 349 struct etm4_arch_features *ftr; 350 int bit; 351 352 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 353 ftr = &etm4_features[bit]; 354 355 if (ftr->arch_callback) 356 ftr->arch_callback(true); 357 } 358 } 359 360 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 361 { 362 struct etm4_arch_features *ftr; 363 int bit; 364 365 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 366 ftr = &etm4_features[bit]; 367 368 if (ftr->arch_callback) 369 ftr->arch_callback(false); 370 } 371 } 372 373 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 374 struct csdev_access *csa) 375 { 376 /* 377 * TRCPIDR* registers are not required for ETMs with system 378 * instructions. They must be identified by the MIDR+REVIDRs. 379 * Skip the TRCPID checks for now. 380 */ 381 if (!csa->io_mem) 382 return; 383 384 if (etm4_hisi_match_pid(coresight_get_pid(csa))) 385 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features); 386 } 387 #else 388 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 389 { 390 } 391 392 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 393 { 394 } 395 396 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 397 struct csdev_access *csa) 398 { 399 } 400 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */ 401 402 static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 403 { 404 int i, rc; 405 struct etmv4_config *config = &drvdata->config; 406 struct coresight_device *csdev = drvdata->csdev; 407 struct device *etm_dev = &csdev->dev; 408 struct csdev_access *csa = &csdev->access; 409 410 411 etm4_cs_unlock(drvdata, csa); 412 etm4_enable_arch_specific(drvdata); 413 414 etm4_os_unlock(drvdata); 415 416 rc = coresight_claim_device_unlocked(csdev); 417 if (rc) 418 goto done; 419 420 /* Disable the trace unit before programming trace registers */ 421 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); 422 423 /* 424 * If we use system instructions, we need to synchronize the 425 * write to the TRCPRGCTLR, before accessing the TRCSTATR. 426 * See ARM IHI0064F, section 427 * "4.3.7 Synchronization of register updates" 428 */ 429 if (!csa->io_mem) 430 isb(); 431 432 /* wait for TRCSTATR.IDLE to go up */ 433 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) 434 dev_err(etm_dev, 435 "timeout while waiting for Idle Trace Status\n"); 436 if (drvdata->nr_pe) 437 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); 438 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); 439 /* nothing specific implemented */ 440 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); 441 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); 442 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); 443 if (drvdata->stallctl) 444 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); 445 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); 446 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); 447 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR); 448 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR); 449 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR); 450 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); 451 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); 452 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); 453 if (drvdata->nr_pe_cmp) 454 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); 455 for (i = 0; i < drvdata->nrseqstate - 1; i++) 456 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); 457 if (drvdata->nrseqstate) { 458 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); 459 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); 460 } 461 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); 462 for (i = 0; i < drvdata->nr_cntr; i++) { 463 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); 464 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); 465 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); 466 } 467 468 /* 469 * Resource selector pair 0 is always implemented and reserved. As 470 * such start at 2. 471 */ 472 for (i = 2; i < drvdata->nr_resource * 2; i++) 473 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); 474 475 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 476 /* always clear status bit on restart if using single-shot */ 477 if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) 478 config->ss_status[i] &= ~TRCSSCSRn_STATUS; 479 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); 480 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); 481 if (etm4x_sspcicrn_present(drvdata, i)) 482 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); 483 } 484 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 485 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); 486 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); 487 } 488 for (i = 0; i < drvdata->numcidc; i++) 489 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); 490 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); 491 if (drvdata->numcidc > 4) 492 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); 493 494 for (i = 0; i < drvdata->numvmidc; i++) 495 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); 496 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); 497 if (drvdata->numvmidc > 4) 498 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); 499 500 if (!drvdata->skip_power_up) { 501 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); 502 503 /* 504 * Request to keep the trace unit powered and also 505 * emulation of powerdown 506 */ 507 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); 508 } 509 510 /* 511 * ETE mandates that the TRCRSR is written to before 512 * enabling it. 513 */ 514 if (etm4x_is_ete(drvdata)) 515 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR); 516 517 etm4x_allow_trace(drvdata); 518 /* Enable the trace unit */ 519 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); 520 521 /* Synchronize the register updates for sysreg access */ 522 if (!csa->io_mem) 523 isb(); 524 525 /* wait for TRCSTATR.IDLE to go back down to '0' */ 526 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) 527 dev_err(etm_dev, 528 "timeout while waiting for Idle Trace Status\n"); 529 530 /* 531 * As recommended by section 4.3.7 ("Synchronization when using the 532 * memory-mapped interface") of ARM IHI 0064D 533 */ 534 dsb(sy); 535 isb(); 536 537 done: 538 etm4_cs_lock(drvdata, csa); 539 540 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", 541 drvdata->cpu, rc); 542 return rc; 543 } 544 545 static void etm4_enable_hw_smp_call(void *info) 546 { 547 struct etm4_enable_arg *arg = info; 548 549 if (WARN_ON(!arg)) 550 return; 551 arg->rc = etm4_enable_hw(arg->drvdata); 552 } 553 554 /* 555 * The goal of function etm4_config_timestamp_event() is to configure a 556 * counter that will tell the tracer to emit a timestamp packet when it 557 * reaches zero. This is done in order to get a more fine grained idea 558 * of when instructions are executed so that they can be correlated 559 * with execution on other CPUs. 560 * 561 * To do this the counter itself is configured to self reload and 562 * TRCRSCTLR1 (always true) used to get the counter to decrement. From 563 * there a resource selector is configured with the counter and the 564 * timestamp control register to use the resource selector to trigger the 565 * event that will insert a timestamp packet in the stream. 566 */ 567 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) 568 { 569 int ctridx, ret = -EINVAL; 570 int counter, rselector; 571 u32 val = 0; 572 struct etmv4_config *config = &drvdata->config; 573 574 /* No point in trying if we don't have at least one counter */ 575 if (!drvdata->nr_cntr) 576 goto out; 577 578 /* Find a counter that hasn't been initialised */ 579 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) 580 if (config->cntr_val[ctridx] == 0) 581 break; 582 583 /* All the counters have been configured already, bail out */ 584 if (ctridx == drvdata->nr_cntr) { 585 pr_debug("%s: no available counter found\n", __func__); 586 ret = -ENOSPC; 587 goto out; 588 } 589 590 /* 591 * Searching for an available resource selector to use, starting at 592 * '2' since every implementation has at least 2 resource selector. 593 * ETMIDR4 gives the number of resource selector _pairs_, 594 * hence multiply by 2. 595 */ 596 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) 597 if (!config->res_ctrl[rselector]) 598 break; 599 600 if (rselector == drvdata->nr_resource * 2) { 601 pr_debug("%s: no available resource selector found\n", 602 __func__); 603 ret = -ENOSPC; 604 goto out; 605 } 606 607 /* Remember what counter we used */ 608 counter = 1 << ctridx; 609 610 /* 611 * Initialise original and reload counter value to the smallest 612 * possible value in order to get as much precision as we can. 613 */ 614 config->cntr_val[ctridx] = 1; 615 config->cntrldvr[ctridx] = 1; 616 617 /* Set the trace counter control register */ 618 val = 0x1 << 16 | /* Bit 16, reload counter automatically */ 619 0x0 << 7 | /* Select single resource selector */ 620 0x1; /* Resource selector 1, i.e always true */ 621 622 config->cntr_ctrl[ctridx] = val; 623 624 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ 625 counter << 0; /* Counter to use */ 626 627 config->res_ctrl[rselector] = val; 628 629 val = 0x0 << 7 | /* Select single resource selector */ 630 rselector; /* Resource selector */ 631 632 config->ts_ctrl = val; 633 634 ret = 0; 635 out: 636 return ret; 637 } 638 639 static int etm4_parse_event_config(struct coresight_device *csdev, 640 struct perf_event *event) 641 { 642 int ret = 0; 643 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 644 struct etmv4_config *config = &drvdata->config; 645 struct perf_event_attr *attr = &event->attr; 646 unsigned long cfg_hash; 647 int preset; 648 649 /* Clear configuration from previous run */ 650 memset(config, 0, sizeof(struct etmv4_config)); 651 652 if (attr->exclude_kernel) 653 config->mode = ETM_MODE_EXCL_KERN; 654 655 if (attr->exclude_user) 656 config->mode = ETM_MODE_EXCL_USER; 657 658 /* Always start from the default config */ 659 etm4_set_default_config(config); 660 661 /* Configure filters specified on the perf cmd line, if any. */ 662 ret = etm4_set_event_filters(drvdata, event); 663 if (ret) 664 goto out; 665 666 /* Go from generic option to ETMv4 specifics */ 667 if (attr->config & BIT(ETM_OPT_CYCACC)) { 668 config->cfg |= TRCCONFIGR_CCI; 669 /* TRM: Must program this for cycacc to work */ 670 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; 671 } 672 if (attr->config & BIT(ETM_OPT_TS)) { 673 /* 674 * Configure timestamps to be emitted at regular intervals in 675 * order to correlate instructions executed on different CPUs 676 * (CPU-wide trace scenarios). 677 */ 678 ret = etm4_config_timestamp_event(drvdata); 679 680 /* 681 * No need to go further if timestamp intervals can't 682 * be configured. 683 */ 684 if (ret) 685 goto out; 686 687 /* bit[11], Global timestamp tracing bit */ 688 config->cfg |= TRCCONFIGR_TS; 689 } 690 691 /* Only trace contextID when runs in root PID namespace */ 692 if ((attr->config & BIT(ETM_OPT_CTXTID)) && 693 task_is_in_init_pid_ns(current)) 694 /* bit[6], Context ID tracing bit */ 695 config->cfg |= TRCCONFIGR_CID; 696 697 /* 698 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID 699 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the 700 * kernel is not running in EL2. 701 */ 702 if (attr->config & BIT(ETM_OPT_CTXTID2)) { 703 if (!is_kernel_in_hyp_mode()) { 704 ret = -EINVAL; 705 goto out; 706 } 707 /* Only trace virtual contextID when runs in root PID namespace */ 708 if (task_is_in_init_pid_ns(current)) 709 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT; 710 } 711 712 /* return stack - enable if selected and supported */ 713 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) 714 /* bit[12], Return stack enable bit */ 715 config->cfg |= TRCCONFIGR_RS; 716 717 /* 718 * Set any selected configuration and preset. 719 * 720 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset) 721 * in the perf attributes defined in coresight-etm-perf.c. 722 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config. 723 * A zero configid means no configuration active, preset = 0 means no preset selected. 724 */ 725 if (attr->config2 & GENMASK_ULL(63, 32)) { 726 cfg_hash = (u32)(attr->config2 >> 32); 727 preset = attr->config & 0xF; 728 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); 729 } 730 731 /* branch broadcast - enable if selected and supported */ 732 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) { 733 if (!drvdata->trcbb) { 734 /* 735 * Missing BB support could cause silent decode errors 736 * so fail to open if it's not supported. 737 */ 738 ret = -EINVAL; 739 goto out; 740 } else { 741 config->cfg |= BIT(ETM4_CFG_BIT_BB); 742 } 743 } 744 745 out: 746 return ret; 747 } 748 749 static int etm4_enable_perf(struct coresight_device *csdev, 750 struct perf_event *event) 751 { 752 int ret = 0, trace_id; 753 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 754 755 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { 756 ret = -EINVAL; 757 goto out; 758 } 759 760 /* Configure the tracer based on the session's specifics */ 761 ret = etm4_parse_event_config(csdev, event); 762 if (ret) 763 goto out; 764 765 /* 766 * perf allocates cpu ids as part of _setup_aux() - device needs to use 767 * the allocated ID. This reads the current version without allocation. 768 * 769 * This does not use the trace id lock to prevent lock_dep issues 770 * with perf locks - we know the ID cannot change until perf shuts down 771 * the session 772 */ 773 trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu); 774 if (!IS_VALID_CS_TRACE_ID(trace_id)) { 775 dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n", 776 dev_name(&drvdata->csdev->dev), drvdata->cpu); 777 ret = -EINVAL; 778 goto out; 779 } 780 drvdata->trcid = (u8)trace_id; 781 782 /* And enable it */ 783 ret = etm4_enable_hw(drvdata); 784 785 out: 786 return ret; 787 } 788 789 static int etm4_enable_sysfs(struct coresight_device *csdev) 790 { 791 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 792 struct etm4_enable_arg arg = { }; 793 unsigned long cfg_hash; 794 int ret, preset; 795 796 /* enable any config activated by configfs */ 797 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); 798 if (cfg_hash) { 799 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); 800 if (ret) 801 return ret; 802 } 803 804 spin_lock(&drvdata->spinlock); 805 806 /* sysfs needs to read and allocate a trace ID */ 807 ret = etm4_read_alloc_trace_id(drvdata); 808 if (ret < 0) 809 goto unlock_sysfs_enable; 810 811 /* 812 * Executing etm4_enable_hw on the cpu whose ETM is being enabled 813 * ensures that register writes occur when cpu is powered. 814 */ 815 arg.drvdata = drvdata; 816 ret = smp_call_function_single(drvdata->cpu, 817 etm4_enable_hw_smp_call, &arg, 1); 818 if (!ret) 819 ret = arg.rc; 820 if (!ret) 821 drvdata->sticky_enable = true; 822 823 if (ret) 824 etm4_release_trace_id(drvdata); 825 826 unlock_sysfs_enable: 827 spin_unlock(&drvdata->spinlock); 828 829 if (!ret) 830 dev_dbg(&csdev->dev, "ETM tracing enabled\n"); 831 return ret; 832 } 833 834 static int etm4_enable(struct coresight_device *csdev, struct perf_event *event, 835 enum cs_mode mode) 836 { 837 int ret; 838 u32 val; 839 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 840 841 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); 842 843 /* Someone is already using the tracer */ 844 if (val) 845 return -EBUSY; 846 847 switch (mode) { 848 case CS_MODE_SYSFS: 849 ret = etm4_enable_sysfs(csdev); 850 break; 851 case CS_MODE_PERF: 852 ret = etm4_enable_perf(csdev, event); 853 break; 854 default: 855 ret = -EINVAL; 856 } 857 858 /* The tracer didn't start */ 859 if (ret) 860 local_set(&drvdata->mode, CS_MODE_DISABLED); 861 862 return ret; 863 } 864 865 static void etm4_disable_hw(void *info) 866 { 867 u32 control; 868 struct etmv4_drvdata *drvdata = info; 869 struct etmv4_config *config = &drvdata->config; 870 struct coresight_device *csdev = drvdata->csdev; 871 struct device *etm_dev = &csdev->dev; 872 struct csdev_access *csa = &csdev->access; 873 int i; 874 875 etm4_cs_unlock(drvdata, csa); 876 etm4_disable_arch_specific(drvdata); 877 878 if (!drvdata->skip_power_up) { 879 /* power can be removed from the trace unit now */ 880 control = etm4x_relaxed_read32(csa, TRCPDCR); 881 control &= ~TRCPDCR_PU; 882 etm4x_relaxed_write32(csa, control, TRCPDCR); 883 } 884 885 control = etm4x_relaxed_read32(csa, TRCPRGCTLR); 886 887 /* EN, bit[0] Trace unit enable bit */ 888 control &= ~0x1; 889 890 /* 891 * If the CPU supports v8.4 Trace filter Control, 892 * set the ETM to trace prohibited region. 893 */ 894 etm4x_prohibit_trace(drvdata); 895 /* 896 * Make sure everything completes before disabling, as recommended 897 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register, 898 * SSTATUS") of ARM IHI 0064D 899 */ 900 dsb(sy); 901 isb(); 902 /* Trace synchronization barrier, is a nop if not supported */ 903 tsb_csync(); 904 etm4x_relaxed_write32(csa, control, TRCPRGCTLR); 905 906 /* wait for TRCSTATR.PMSTABLE to go to '1' */ 907 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) 908 dev_err(etm_dev, 909 "timeout while waiting for PM stable Trace Status\n"); 910 /* read the status of the single shot comparators */ 911 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 912 config->ss_status[i] = 913 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 914 } 915 916 /* read back the current counter values */ 917 for (i = 0; i < drvdata->nr_cntr; i++) { 918 config->cntr_val[i] = 919 etm4x_relaxed_read32(csa, TRCCNTVRn(i)); 920 } 921 922 coresight_disclaim_device_unlocked(csdev); 923 etm4_cs_lock(drvdata, csa); 924 925 dev_dbg(&drvdata->csdev->dev, 926 "cpu: %d disable smp call done\n", drvdata->cpu); 927 } 928 929 static int etm4_disable_perf(struct coresight_device *csdev, 930 struct perf_event *event) 931 { 932 u32 control; 933 struct etm_filters *filters = event->hw.addr_filters; 934 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 935 struct perf_event_attr *attr = &event->attr; 936 937 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) 938 return -EINVAL; 939 940 etm4_disable_hw(drvdata); 941 /* 942 * The config_id occupies bits 63:32 of the config2 perf event attr 943 * field. If this is non-zero then we will have enabled a config. 944 */ 945 if (attr->config2 & GENMASK_ULL(63, 32)) 946 cscfg_csdev_disable_active_config(csdev); 947 948 /* 949 * Check if the start/stop logic was active when the unit was stopped. 950 * That way we can re-enable the start/stop logic when the process is 951 * scheduled again. Configuration of the start/stop logic happens in 952 * function etm4_set_event_filters(). 953 */ 954 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR); 955 /* TRCVICTLR::SSSTATUS, bit[9] */ 956 filters->ssstatus = (control & BIT(9)); 957 958 /* 959 * perf will release trace ids when _free_aux() is 960 * called at the end of the session. 961 */ 962 963 return 0; 964 } 965 966 static void etm4_disable_sysfs(struct coresight_device *csdev) 967 { 968 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 969 970 /* 971 * Taking hotplug lock here protects from clocks getting disabled 972 * with tracing being left on (crash scenario) if user disable occurs 973 * after cpu online mask indicates the cpu is offline but before the 974 * DYING hotplug callback is serviced by the ETM driver. 975 */ 976 cpus_read_lock(); 977 spin_lock(&drvdata->spinlock); 978 979 /* 980 * Executing etm4_disable_hw on the cpu whose ETM is being disabled 981 * ensures that register writes occur when cpu is powered. 982 */ 983 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); 984 985 spin_unlock(&drvdata->spinlock); 986 cpus_read_unlock(); 987 988 /* 989 * we only release trace IDs when resetting sysfs. 990 * This permits sysfs users to read the trace ID after the trace 991 * session has completed. This maintains operational behaviour with 992 * prior trace id allocation method 993 */ 994 995 dev_dbg(&csdev->dev, "ETM tracing disabled\n"); 996 } 997 998 static void etm4_disable(struct coresight_device *csdev, 999 struct perf_event *event) 1000 { 1001 enum cs_mode mode; 1002 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 1003 1004 /* 1005 * For as long as the tracer isn't disabled another entity can't 1006 * change its status. As such we can read the status here without 1007 * fearing it will change under us. 1008 */ 1009 mode = local_read(&drvdata->mode); 1010 1011 switch (mode) { 1012 case CS_MODE_DISABLED: 1013 break; 1014 case CS_MODE_SYSFS: 1015 etm4_disable_sysfs(csdev); 1016 break; 1017 case CS_MODE_PERF: 1018 etm4_disable_perf(csdev, event); 1019 break; 1020 } 1021 1022 if (mode) 1023 local_set(&drvdata->mode, CS_MODE_DISABLED); 1024 } 1025 1026 static const struct coresight_ops_source etm4_source_ops = { 1027 .cpu_id = etm4_cpu_id, 1028 .enable = etm4_enable, 1029 .disable = etm4_disable, 1030 }; 1031 1032 static const struct coresight_ops etm4_cs_ops = { 1033 .source_ops = &etm4_source_ops, 1034 }; 1035 1036 static inline bool cpu_supports_sysreg_trace(void) 1037 { 1038 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); 1039 1040 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0; 1041 } 1042 1043 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, 1044 struct csdev_access *csa) 1045 { 1046 u32 devarch; 1047 1048 if (!cpu_supports_sysreg_trace()) 1049 return false; 1050 1051 /* 1052 * ETMs implementing sysreg access must implement TRCDEVARCH. 1053 */ 1054 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); 1055 switch (devarch & ETM_DEVARCH_ID_MASK) { 1056 case ETM_DEVARCH_ETMv4x_ARCH: 1057 *csa = (struct csdev_access) { 1058 .io_mem = false, 1059 .read = etm4x_sysreg_read, 1060 .write = etm4x_sysreg_write, 1061 }; 1062 break; 1063 case ETM_DEVARCH_ETE_ARCH: 1064 *csa = (struct csdev_access) { 1065 .io_mem = false, 1066 .read = ete_sysreg_read, 1067 .write = ete_sysreg_write, 1068 }; 1069 break; 1070 default: 1071 return false; 1072 } 1073 1074 drvdata->arch = etm_devarch_to_arch(devarch); 1075 return true; 1076 } 1077 1078 static bool is_devtype_cpu_trace(void __iomem *base) 1079 { 1080 u32 devtype = readl(base + TRCDEVTYPE); 1081 1082 return (devtype == CS_DEVTYPE_PE_TRACE); 1083 } 1084 1085 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, 1086 struct csdev_access *csa) 1087 { 1088 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH); 1089 1090 if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base)) 1091 return false; 1092 1093 /* 1094 * All ETMs must implement TRCDEVARCH to indicate that 1095 * the component is an ETMv4. Even though TRCIDR1 also 1096 * contains the information, it is part of the "Trace" 1097 * register and must be accessed with the OSLK cleared, 1098 * with MMIO. But we cannot touch the OSLK until we are 1099 * sure this is an ETM. So rely only on the TRCDEVARCH. 1100 */ 1101 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) { 1102 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n"); 1103 return false; 1104 } 1105 1106 drvdata->arch = etm_devarch_to_arch(devarch); 1107 *csa = CSDEV_ACCESS_IOMEM(drvdata->base); 1108 return true; 1109 } 1110 1111 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, 1112 struct csdev_access *csa) 1113 { 1114 /* 1115 * Always choose the memory mapped io, if there is 1116 * a memory map to prevent sysreg access on broken 1117 * systems. 1118 */ 1119 if (drvdata->base) 1120 return etm4_init_iomem_access(drvdata, csa); 1121 1122 if (etm4_init_sysreg_access(drvdata, csa)) 1123 return true; 1124 1125 return false; 1126 } 1127 1128 static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) 1129 { 1130 u64 dfr0 = read_sysreg(id_aa64dfr0_el1); 1131 u64 trfcr; 1132 1133 drvdata->trfcr = 0; 1134 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT)) 1135 return; 1136 1137 /* 1138 * If the CPU supports v8.4 SelfHosted Tracing, enable 1139 * tracing at the kernel EL and EL0, forcing to use the 1140 * virtual time as the timestamp. 1141 */ 1142 trfcr = (TRFCR_ELx_TS_VIRTUAL | 1143 TRFCR_ELx_ExTRE | 1144 TRFCR_ELx_E0TRE); 1145 1146 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */ 1147 if (is_kernel_in_hyp_mode()) 1148 trfcr |= TRFCR_EL2_CX; 1149 1150 drvdata->trfcr = trfcr; 1151 } 1152 1153 static void etm4_init_arch_data(void *info) 1154 { 1155 u32 etmidr0; 1156 u32 etmidr2; 1157 u32 etmidr3; 1158 u32 etmidr4; 1159 u32 etmidr5; 1160 struct etm4_init_arg *init_arg = info; 1161 struct etmv4_drvdata *drvdata; 1162 struct csdev_access *csa; 1163 struct device *dev = init_arg->dev; 1164 int i; 1165 1166 drvdata = dev_get_drvdata(init_arg->dev); 1167 csa = init_arg->csa; 1168 1169 /* 1170 * If we are unable to detect the access mechanism, 1171 * or unable to detect the trace unit type, fail 1172 * early. 1173 */ 1174 if (!etm4_init_csdev_access(drvdata, csa)) 1175 return; 1176 1177 if (!csa->io_mem || 1178 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) 1179 drvdata->skip_power_up = true; 1180 1181 /* Detect the support for OS Lock before we actually use it */ 1182 etm_detect_os_lock(drvdata, csa); 1183 1184 /* Make sure all registers are accessible */ 1185 etm4_os_unlock_csa(drvdata, csa); 1186 etm4_cs_unlock(drvdata, csa); 1187 1188 etm4_check_arch_features(drvdata, csa); 1189 1190 /* find all capabilities of the tracing unit */ 1191 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); 1192 1193 /* INSTP0, bits[2:1] P0 tracing support field */ 1194 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11); 1195 /* TRCBB, bit[5] Branch broadcast tracing support bit */ 1196 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB); 1197 /* TRCCOND, bit[6] Conditional instruction tracing support bit */ 1198 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND); 1199 /* TRCCCI, bit[7] Cycle counting instruction bit */ 1200 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI); 1201 /* RETSTACK, bit[9] Return stack bit */ 1202 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK); 1203 /* NUMEVENT, bits[11:10] Number of events field */ 1204 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); 1205 /* QSUPP, bits[16:15] Q element support field */ 1206 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); 1207 if (drvdata->q_support) 1208 drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT); 1209 /* TSSIZE, bits[28:24] Global timestamp size field */ 1210 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0); 1211 1212 /* maximum size of resources */ 1213 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); 1214 /* CIDSIZE, bits[9:5] Indicates the Context ID size */ 1215 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); 1216 /* VMIDSIZE, bits[14:10] Indicates the VMID size */ 1217 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); 1218 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ 1219 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2); 1220 1221 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); 1222 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ 1223 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); 1224 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ 1225 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); 1226 drvdata->config.s_ex_level = drvdata->s_ex_level; 1227 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ 1228 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); 1229 /* 1230 * TRCERR, bit[24] whether a trace unit can trace a 1231 * system error exception. 1232 */ 1233 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR); 1234 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ 1235 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR); 1236 /* STALLCTL, bit[26] is stall control implemented? */ 1237 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL); 1238 /* SYSSTALL, bit[27] implementation can support stall control? */ 1239 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL); 1240 /* 1241 * NUMPROC - the number of PEs available for tracing, 5bits 1242 * = TRCIDR3.bits[13:12]bits[30:28] 1243 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0) 1244 * bits[3:0] = TRCIDR3.bits[30:28] 1245 */ 1246 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) | 1247 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3); 1248 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ 1249 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW); 1250 1251 /* number of resources trace unit supports */ 1252 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); 1253 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ 1254 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); 1255 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ 1256 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); 1257 /* 1258 * NUMRSPAIR, bits[19:16] 1259 * The number of resource pairs conveyed by the HW starts at 0, i.e a 1260 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on. 1261 * As such add 1 to the value of NUMRSPAIR for a better representation. 1262 * 1263 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available - 1264 * the default TRUE and FALSE resource selectors are omitted. 1265 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. 1266 */ 1267 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); 1268 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) 1269 drvdata->nr_resource += 1; 1270 /* 1271 * NUMSSCC, bits[23:20] the number of single-shot 1272 * comparator control for tracing. Read any status regs as these 1273 * also contain RO capability data. 1274 */ 1275 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); 1276 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1277 drvdata->config.ss_status[i] = 1278 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 1279 } 1280 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ 1281 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); 1282 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ 1283 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4); 1284 1285 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); 1286 /* NUMEXTIN, bits[8:0] number of external inputs implemented */ 1287 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); 1288 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ 1289 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); 1290 /* ATBTRIG, bit[22] implementation can support ATB triggers? */ 1291 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG); 1292 /* 1293 * LPOVERRIDE, bit[23] implementation supports 1294 * low-power state override 1295 */ 1296 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up); 1297 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ 1298 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); 1299 /* NUMCNTR, bits[30:28] number of counters available for tracing */ 1300 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); 1301 etm4_cs_lock(drvdata, csa); 1302 cpu_detect_trace_filtering(drvdata); 1303 } 1304 1305 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) 1306 { 1307 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK); 1308 } 1309 1310 /* Set ELx trace filter access in the TRCVICTLR register */ 1311 static void etm4_set_victlr_access(struct etmv4_config *config) 1312 { 1313 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK; 1314 config->vinst_ctrl |= etm4_get_victlr_access_type(config); 1315 } 1316 1317 static void etm4_set_default_config(struct etmv4_config *config) 1318 { 1319 /* disable all events tracing */ 1320 config->eventctrl0 = 0x0; 1321 config->eventctrl1 = 0x0; 1322 1323 /* disable stalling */ 1324 config->stall_ctrl = 0x0; 1325 1326 /* enable trace synchronization every 4096 bytes, if available */ 1327 config->syncfreq = 0xC; 1328 1329 /* disable timestamp event */ 1330 config->ts_ctrl = 0x0; 1331 1332 /* TRCVICTLR::EVENT = 0x01, select the always on logic */ 1333 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01); 1334 1335 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ 1336 etm4_set_victlr_access(config); 1337 } 1338 1339 static u64 etm4_get_ns_access_type(struct etmv4_config *config) 1340 { 1341 u64 access_type = 0; 1342 1343 /* 1344 * EXLEVEL_NS, for NonSecure Exception levels. 1345 * The mask here is a generic value and must be 1346 * shifted to the corresponding field for the registers 1347 */ 1348 if (!is_kernel_in_hyp_mode()) { 1349 /* Stay away from hypervisor mode for non-VHE */ 1350 access_type = ETM_EXLEVEL_NS_HYP; 1351 if (config->mode & ETM_MODE_EXCL_KERN) 1352 access_type |= ETM_EXLEVEL_NS_OS; 1353 } else if (config->mode & ETM_MODE_EXCL_KERN) { 1354 access_type = ETM_EXLEVEL_NS_HYP; 1355 } 1356 1357 if (config->mode & ETM_MODE_EXCL_USER) 1358 access_type |= ETM_EXLEVEL_NS_APP; 1359 1360 return access_type; 1361 } 1362 1363 /* 1364 * Construct the exception level masks for a given config. 1365 * This must be shifted to the corresponding register field 1366 * for usage. 1367 */ 1368 static u64 etm4_get_access_type(struct etmv4_config *config) 1369 { 1370 /* All Secure exception levels are excluded from the trace */ 1371 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level; 1372 } 1373 1374 static u64 etm4_get_comparator_access_type(struct etmv4_config *config) 1375 { 1376 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT; 1377 } 1378 1379 static void etm4_set_comparator_filter(struct etmv4_config *config, 1380 u64 start, u64 stop, int comparator) 1381 { 1382 u64 access_type = etm4_get_comparator_access_type(config); 1383 1384 /* First half of default address comparator */ 1385 config->addr_val[comparator] = start; 1386 config->addr_acc[comparator] = access_type; 1387 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE; 1388 1389 /* Second half of default address comparator */ 1390 config->addr_val[comparator + 1] = stop; 1391 config->addr_acc[comparator + 1] = access_type; 1392 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE; 1393 1394 /* 1395 * Configure the ViewInst function to include this address range 1396 * comparator. 1397 * 1398 * @comparator is divided by two since it is the index in the 1399 * etmv4_config::addr_val array but register TRCVIIECTLR deals with 1400 * address range comparator _pairs_. 1401 * 1402 * Therefore: 1403 * index 0 -> compatator pair 0 1404 * index 2 -> comparator pair 1 1405 * index 4 -> comparator pair 2 1406 * ... 1407 * index 14 -> comparator pair 7 1408 */ 1409 config->viiectlr |= BIT(comparator / 2); 1410 } 1411 1412 static void etm4_set_start_stop_filter(struct etmv4_config *config, 1413 u64 address, int comparator, 1414 enum etm_addr_type type) 1415 { 1416 int shift; 1417 u64 access_type = etm4_get_comparator_access_type(config); 1418 1419 /* Configure the comparator */ 1420 config->addr_val[comparator] = address; 1421 config->addr_acc[comparator] = access_type; 1422 config->addr_type[comparator] = type; 1423 1424 /* 1425 * Configure ViewInst Start-Stop control register. 1426 * Addresses configured to start tracing go from bit 0 to n-1, 1427 * while those configured to stop tracing from 16 to 16 + n-1. 1428 */ 1429 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16); 1430 config->vissctlr |= BIT(shift + comparator); 1431 } 1432 1433 static void etm4_set_default_filter(struct etmv4_config *config) 1434 { 1435 /* Trace everything 'default' filter achieved by no filtering */ 1436 config->viiectlr = 0x0; 1437 1438 /* 1439 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1440 * in the started state 1441 */ 1442 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1443 config->mode |= ETM_MODE_VIEWINST_STARTSTOP; 1444 1445 /* No start-stop filtering for ViewInst */ 1446 config->vissctlr = 0x0; 1447 } 1448 1449 static void etm4_set_default(struct etmv4_config *config) 1450 { 1451 if (WARN_ON_ONCE(!config)) 1452 return; 1453 1454 /* 1455 * Make default initialisation trace everything 1456 * 1457 * This is done by a minimum default config sufficient to enable 1458 * full instruction trace - with a default filter for trace all 1459 * achieved by having no filtering. 1460 */ 1461 etm4_set_default_config(config); 1462 etm4_set_default_filter(config); 1463 } 1464 1465 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) 1466 { 1467 int nr_comparator, index = 0; 1468 struct etmv4_config *config = &drvdata->config; 1469 1470 /* 1471 * nr_addr_cmp holds the number of comparator _pair_, so time 2 1472 * for the total number of comparators. 1473 */ 1474 nr_comparator = drvdata->nr_addr_cmp * 2; 1475 1476 /* Go through the tally of comparators looking for a free one. */ 1477 while (index < nr_comparator) { 1478 switch (type) { 1479 case ETM_ADDR_TYPE_RANGE: 1480 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE && 1481 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE) 1482 return index; 1483 1484 /* Address range comparators go in pairs */ 1485 index += 2; 1486 break; 1487 case ETM_ADDR_TYPE_START: 1488 case ETM_ADDR_TYPE_STOP: 1489 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE) 1490 return index; 1491 1492 /* Start/stop address can have odd indexes */ 1493 index += 1; 1494 break; 1495 default: 1496 return -EINVAL; 1497 } 1498 } 1499 1500 /* If we are here all the comparators have been used. */ 1501 return -ENOSPC; 1502 } 1503 1504 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 1505 struct perf_event *event) 1506 { 1507 int i, comparator, ret = 0; 1508 u64 address; 1509 struct etmv4_config *config = &drvdata->config; 1510 struct etm_filters *filters = event->hw.addr_filters; 1511 1512 if (!filters) 1513 goto default_filter; 1514 1515 /* Sync events with what Perf got */ 1516 perf_event_addr_filters_sync(event); 1517 1518 /* 1519 * If there are no filters to deal with simply go ahead with 1520 * the default filter, i.e the entire address range. 1521 */ 1522 if (!filters->nr_filters) 1523 goto default_filter; 1524 1525 for (i = 0; i < filters->nr_filters; i++) { 1526 struct etm_filter *filter = &filters->etm_filter[i]; 1527 enum etm_addr_type type = filter->type; 1528 1529 /* See if a comparator is free. */ 1530 comparator = etm4_get_next_comparator(drvdata, type); 1531 if (comparator < 0) { 1532 ret = comparator; 1533 goto out; 1534 } 1535 1536 switch (type) { 1537 case ETM_ADDR_TYPE_RANGE: 1538 etm4_set_comparator_filter(config, 1539 filter->start_addr, 1540 filter->stop_addr, 1541 comparator); 1542 /* 1543 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1544 * in the started state 1545 */ 1546 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1547 1548 /* No start-stop filtering for ViewInst */ 1549 config->vissctlr = 0x0; 1550 break; 1551 case ETM_ADDR_TYPE_START: 1552 case ETM_ADDR_TYPE_STOP: 1553 /* Get the right start or stop address */ 1554 address = (type == ETM_ADDR_TYPE_START ? 1555 filter->start_addr : 1556 filter->stop_addr); 1557 1558 /* Configure comparator */ 1559 etm4_set_start_stop_filter(config, address, 1560 comparator, type); 1561 1562 /* 1563 * If filters::ssstatus == 1, trace acquisition was 1564 * started but the process was yanked away before the 1565 * stop address was hit. As such the start/stop 1566 * logic needs to be re-started so that tracing can 1567 * resume where it left. 1568 * 1569 * The start/stop logic status when a process is 1570 * scheduled out is checked in function 1571 * etm4_disable_perf(). 1572 */ 1573 if (filters->ssstatus) 1574 config->vinst_ctrl |= TRCVICTLR_SSSTATUS; 1575 1576 /* No include/exclude filtering for ViewInst */ 1577 config->viiectlr = 0x0; 1578 break; 1579 default: 1580 ret = -EINVAL; 1581 goto out; 1582 } 1583 } 1584 1585 goto out; 1586 1587 1588 default_filter: 1589 etm4_set_default_filter(config); 1590 1591 out: 1592 return ret; 1593 } 1594 1595 void etm4_config_trace_mode(struct etmv4_config *config) 1596 { 1597 u32 mode; 1598 1599 mode = config->mode; 1600 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); 1601 1602 /* excluding kernel AND user space doesn't make sense */ 1603 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)); 1604 1605 /* nothing to do if neither flags are set */ 1606 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) 1607 return; 1608 1609 etm4_set_victlr_access(config); 1610 } 1611 1612 static int etm4_online_cpu(unsigned int cpu) 1613 { 1614 if (!etmdrvdata[cpu]) 1615 return etm4_probe_cpu(cpu); 1616 1617 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) 1618 coresight_enable(etmdrvdata[cpu]->csdev); 1619 return 0; 1620 } 1621 1622 static int etm4_starting_cpu(unsigned int cpu) 1623 { 1624 if (!etmdrvdata[cpu]) 1625 return 0; 1626 1627 spin_lock(&etmdrvdata[cpu]->spinlock); 1628 if (!etmdrvdata[cpu]->os_unlock) 1629 etm4_os_unlock(etmdrvdata[cpu]); 1630 1631 if (local_read(&etmdrvdata[cpu]->mode)) 1632 etm4_enable_hw(etmdrvdata[cpu]); 1633 spin_unlock(&etmdrvdata[cpu]->spinlock); 1634 return 0; 1635 } 1636 1637 static int etm4_dying_cpu(unsigned int cpu) 1638 { 1639 if (!etmdrvdata[cpu]) 1640 return 0; 1641 1642 spin_lock(&etmdrvdata[cpu]->spinlock); 1643 if (local_read(&etmdrvdata[cpu]->mode)) 1644 etm4_disable_hw(etmdrvdata[cpu]); 1645 spin_unlock(&etmdrvdata[cpu]->spinlock); 1646 return 0; 1647 } 1648 1649 static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) 1650 { 1651 int i, ret = 0; 1652 struct etmv4_save_state *state; 1653 struct coresight_device *csdev = drvdata->csdev; 1654 struct csdev_access *csa; 1655 struct device *etm_dev; 1656 1657 if (WARN_ON(!csdev)) 1658 return -ENODEV; 1659 1660 etm_dev = &csdev->dev; 1661 csa = &csdev->access; 1662 1663 /* 1664 * As recommended by 3.4.1 ("The procedure when powering down the PE") 1665 * of ARM IHI 0064D 1666 */ 1667 dsb(sy); 1668 isb(); 1669 1670 etm4_cs_unlock(drvdata, csa); 1671 /* Lock the OS lock to disable trace and external debugger access */ 1672 etm4_os_lock(drvdata); 1673 1674 /* wait for TRCSTATR.PMSTABLE to go up */ 1675 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) { 1676 dev_err(etm_dev, 1677 "timeout while waiting for PM Stable Status\n"); 1678 etm4_os_unlock(drvdata); 1679 ret = -EBUSY; 1680 goto out; 1681 } 1682 1683 state = drvdata->save_state; 1684 1685 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR); 1686 if (drvdata->nr_pe) 1687 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); 1688 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); 1689 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); 1690 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); 1691 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); 1692 if (drvdata->stallctl) 1693 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); 1694 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); 1695 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); 1696 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); 1697 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); 1698 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); 1699 if (drvdata->q_filt) 1700 state->trcqctlr = etm4x_read32(csa, TRCQCTLR); 1701 1702 state->trcvictlr = etm4x_read32(csa, TRCVICTLR); 1703 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); 1704 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); 1705 if (drvdata->nr_pe_cmp) 1706 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); 1707 1708 for (i = 0; i < drvdata->nrseqstate - 1; i++) 1709 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); 1710 1711 if (drvdata->nrseqstate) { 1712 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); 1713 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); 1714 } 1715 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); 1716 1717 for (i = 0; i < drvdata->nr_cntr; i++) { 1718 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); 1719 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); 1720 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); 1721 } 1722 1723 /* Resource selector pair 0 is reserved */ 1724 for (i = 2; i < drvdata->nr_resource * 2; i++) 1725 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i)); 1726 1727 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1728 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); 1729 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); 1730 if (etm4x_sspcicrn_present(drvdata, i)) 1731 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); 1732 } 1733 1734 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 1735 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); 1736 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); 1737 } 1738 1739 /* 1740 * Data trace stream is architecturally prohibited for A profile cores 1741 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per 1742 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace 1743 * unit") of ARM IHI 0064D. 1744 */ 1745 1746 for (i = 0; i < drvdata->numcidc; i++) 1747 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); 1748 1749 for (i = 0; i < drvdata->numvmidc; i++) 1750 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); 1751 1752 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); 1753 if (drvdata->numcidc > 4) 1754 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1); 1755 1756 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); 1757 if (drvdata->numvmidc > 4) 1758 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); 1759 1760 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR); 1761 1762 if (!drvdata->skip_power_up) 1763 state->trcpdcr = etm4x_read32(csa, TRCPDCR); 1764 1765 /* wait for TRCSTATR.IDLE to go up */ 1766 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { 1767 dev_err(etm_dev, 1768 "timeout while waiting for Idle Trace Status\n"); 1769 etm4_os_unlock(drvdata); 1770 ret = -EBUSY; 1771 goto out; 1772 } 1773 1774 drvdata->state_needs_restore = true; 1775 1776 /* 1777 * Power can be removed from the trace unit now. We do this to 1778 * potentially save power on systems that respect the TRCPDCR_PU 1779 * despite requesting software to save/restore state. 1780 */ 1781 if (!drvdata->skip_power_up) 1782 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), 1783 TRCPDCR); 1784 out: 1785 etm4_cs_lock(drvdata, csa); 1786 return ret; 1787 } 1788 1789 static int etm4_cpu_save(struct etmv4_drvdata *drvdata) 1790 { 1791 int ret = 0; 1792 1793 /* Save the TRFCR irrespective of whether the ETM is ON */ 1794 if (drvdata->trfcr) 1795 drvdata->save_trfcr = read_trfcr(); 1796 /* 1797 * Save and restore the ETM Trace registers only if 1798 * the ETM is active. 1799 */ 1800 if (local_read(&drvdata->mode) && drvdata->save_state) 1801 ret = __etm4_cpu_save(drvdata); 1802 return ret; 1803 } 1804 1805 static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) 1806 { 1807 int i; 1808 struct etmv4_save_state *state = drvdata->save_state; 1809 struct csdev_access *csa = &drvdata->csdev->access; 1810 1811 if (WARN_ON(!drvdata->csdev)) 1812 return; 1813 1814 etm4_cs_unlock(drvdata, csa); 1815 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 1816 1817 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); 1818 if (drvdata->nr_pe) 1819 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); 1820 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); 1821 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); 1822 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); 1823 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); 1824 if (drvdata->stallctl) 1825 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); 1826 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); 1827 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); 1828 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); 1829 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); 1830 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); 1831 if (drvdata->q_filt) 1832 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); 1833 1834 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); 1835 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); 1836 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); 1837 if (drvdata->nr_pe_cmp) 1838 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); 1839 1840 for (i = 0; i < drvdata->nrseqstate - 1; i++) 1841 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); 1842 1843 if (drvdata->nrseqstate) { 1844 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); 1845 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); 1846 } 1847 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); 1848 1849 for (i = 0; i < drvdata->nr_cntr; i++) { 1850 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); 1851 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); 1852 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); 1853 } 1854 1855 /* Resource selector pair 0 is reserved */ 1856 for (i = 2; i < drvdata->nr_resource * 2; i++) 1857 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); 1858 1859 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1860 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); 1861 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); 1862 if (etm4x_sspcicrn_present(drvdata, i)) 1863 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); 1864 } 1865 1866 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 1867 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); 1868 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); 1869 } 1870 1871 for (i = 0; i < drvdata->numcidc; i++) 1872 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); 1873 1874 for (i = 0; i < drvdata->numvmidc; i++) 1875 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); 1876 1877 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); 1878 if (drvdata->numcidc > 4) 1879 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); 1880 1881 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); 1882 if (drvdata->numvmidc > 4) 1883 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); 1884 1885 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 1886 1887 if (!drvdata->skip_power_up) 1888 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); 1889 1890 drvdata->state_needs_restore = false; 1891 1892 /* 1893 * As recommended by section 4.3.7 ("Synchronization when using the 1894 * memory-mapped interface") of ARM IHI 0064D 1895 */ 1896 dsb(sy); 1897 isb(); 1898 1899 /* Unlock the OS lock to re-enable trace and external debug access */ 1900 etm4_os_unlock(drvdata); 1901 etm4_cs_lock(drvdata, csa); 1902 } 1903 1904 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) 1905 { 1906 if (drvdata->trfcr) 1907 write_trfcr(drvdata->save_trfcr); 1908 if (drvdata->state_needs_restore) 1909 __etm4_cpu_restore(drvdata); 1910 } 1911 1912 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, 1913 void *v) 1914 { 1915 struct etmv4_drvdata *drvdata; 1916 unsigned int cpu = smp_processor_id(); 1917 1918 if (!etmdrvdata[cpu]) 1919 return NOTIFY_OK; 1920 1921 drvdata = etmdrvdata[cpu]; 1922 1923 if (WARN_ON_ONCE(drvdata->cpu != cpu)) 1924 return NOTIFY_BAD; 1925 1926 switch (cmd) { 1927 case CPU_PM_ENTER: 1928 if (etm4_cpu_save(drvdata)) 1929 return NOTIFY_BAD; 1930 break; 1931 case CPU_PM_EXIT: 1932 case CPU_PM_ENTER_FAILED: 1933 etm4_cpu_restore(drvdata); 1934 break; 1935 default: 1936 return NOTIFY_DONE; 1937 } 1938 1939 return NOTIFY_OK; 1940 } 1941 1942 static struct notifier_block etm4_cpu_pm_nb = { 1943 .notifier_call = etm4_cpu_pm_notify, 1944 }; 1945 1946 /* Setup PM. Deals with error conditions and counts */ 1947 static int __init etm4_pm_setup(void) 1948 { 1949 int ret; 1950 1951 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb); 1952 if (ret) 1953 return ret; 1954 1955 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING, 1956 "arm/coresight4:starting", 1957 etm4_starting_cpu, etm4_dying_cpu); 1958 1959 if (ret) 1960 goto unregister_notifier; 1961 1962 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, 1963 "arm/coresight4:online", 1964 etm4_online_cpu, NULL); 1965 1966 /* HP dyn state ID returned in ret on success */ 1967 if (ret > 0) { 1968 hp_online = ret; 1969 return 0; 1970 } 1971 1972 /* failed dyn state - remove others */ 1973 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 1974 1975 unregister_notifier: 1976 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 1977 return ret; 1978 } 1979 1980 static void etm4_pm_clear(void) 1981 { 1982 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 1983 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 1984 if (hp_online) { 1985 cpuhp_remove_state_nocalls(hp_online); 1986 hp_online = 0; 1987 } 1988 } 1989 1990 static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg) 1991 { 1992 int ret; 1993 struct coresight_platform_data *pdata = NULL; 1994 struct device *dev = init_arg->dev; 1995 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 1996 struct coresight_desc desc = { 0 }; 1997 u8 major, minor; 1998 char *type_name; 1999 2000 if (!drvdata) 2001 return -EINVAL; 2002 2003 desc.access = *init_arg->csa; 2004 2005 if (!drvdata->arch) 2006 return -EINVAL; 2007 2008 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch); 2009 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch); 2010 2011 if (etm4x_is_ete(drvdata)) { 2012 type_name = "ete"; 2013 /* ETE v1 has major version == 0b101. Adjust this for logging.*/ 2014 major -= 4; 2015 } else { 2016 type_name = "etm"; 2017 } 2018 2019 desc.name = devm_kasprintf(dev, GFP_KERNEL, 2020 "%s%d", type_name, drvdata->cpu); 2021 if (!desc.name) 2022 return -ENOMEM; 2023 2024 etm4_set_default(&drvdata->config); 2025 2026 pdata = coresight_get_platform_data(dev); 2027 if (IS_ERR(pdata)) 2028 return PTR_ERR(pdata); 2029 2030 dev->platform_data = pdata; 2031 2032 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 2033 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; 2034 desc.ops = &etm4_cs_ops; 2035 desc.pdata = pdata; 2036 desc.dev = dev; 2037 desc.groups = coresight_etmv4_groups; 2038 drvdata->csdev = coresight_register(&desc); 2039 if (IS_ERR(drvdata->csdev)) 2040 return PTR_ERR(drvdata->csdev); 2041 2042 ret = etm_perf_symlink(drvdata->csdev, true); 2043 if (ret) { 2044 coresight_unregister(drvdata->csdev); 2045 return ret; 2046 } 2047 2048 /* register with config infrastructure & load any current features */ 2049 ret = etm4_cscfg_register(drvdata->csdev); 2050 if (ret) { 2051 coresight_unregister(drvdata->csdev); 2052 return ret; 2053 } 2054 2055 etmdrvdata[drvdata->cpu] = drvdata; 2056 2057 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n", 2058 drvdata->cpu, type_name, major, minor); 2059 2060 if (boot_enable) { 2061 coresight_enable(drvdata->csdev); 2062 drvdata->boot_enable = true; 2063 } 2064 2065 return 0; 2066 } 2067 2068 static int etm4_probe(struct device *dev) 2069 { 2070 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 2071 struct csdev_access access = { 0 }; 2072 struct etm4_init_arg init_arg = { 0 }; 2073 struct etm4_init_arg *delayed; 2074 2075 if (WARN_ON(!drvdata)) 2076 return -ENOMEM; 2077 2078 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) 2079 pm_save_enable = coresight_loses_context_with_cpu(dev) ? 2080 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; 2081 2082 if (pm_save_enable != PARAM_PM_SAVE_NEVER) { 2083 drvdata->save_state = devm_kmalloc(dev, 2084 sizeof(struct etmv4_save_state), GFP_KERNEL); 2085 if (!drvdata->save_state) 2086 return -ENOMEM; 2087 } 2088 2089 spin_lock_init(&drvdata->spinlock); 2090 2091 drvdata->cpu = coresight_get_cpu(dev); 2092 if (drvdata->cpu < 0) 2093 return drvdata->cpu; 2094 2095 init_arg.dev = dev; 2096 init_arg.csa = &access; 2097 2098 /* 2099 * Serialize against CPUHP callbacks to avoid race condition 2100 * between the smp call and saving the delayed probe. 2101 */ 2102 cpus_read_lock(); 2103 if (smp_call_function_single(drvdata->cpu, 2104 etm4_init_arch_data, &init_arg, 1)) { 2105 /* The CPU was offline, try again once it comes online. */ 2106 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL); 2107 if (!delayed) { 2108 cpus_read_unlock(); 2109 return -ENOMEM; 2110 } 2111 2112 *delayed = init_arg; 2113 2114 per_cpu(delayed_probe, drvdata->cpu) = delayed; 2115 2116 cpus_read_unlock(); 2117 return 0; 2118 } 2119 cpus_read_unlock(); 2120 2121 return etm4_add_coresight_dev(&init_arg); 2122 } 2123 2124 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) 2125 { 2126 struct etmv4_drvdata *drvdata; 2127 void __iomem *base; 2128 struct device *dev = &adev->dev; 2129 struct resource *res = &adev->res; 2130 int ret; 2131 2132 /* Validity for the resource is already checked by the AMBA core */ 2133 base = devm_ioremap_resource(dev, res); 2134 if (IS_ERR(base)) 2135 return PTR_ERR(base); 2136 2137 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 2138 if (!drvdata) 2139 return -ENOMEM; 2140 2141 drvdata->base = base; 2142 dev_set_drvdata(dev, drvdata); 2143 ret = etm4_probe(dev); 2144 if (!ret) 2145 pm_runtime_put(&adev->dev); 2146 2147 return ret; 2148 } 2149 2150 static int etm4_probe_platform_dev(struct platform_device *pdev) 2151 { 2152 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2153 struct etmv4_drvdata *drvdata; 2154 int ret; 2155 2156 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL); 2157 if (!drvdata) 2158 return -ENOMEM; 2159 2160 drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev); 2161 if (IS_ERR(drvdata->pclk)) 2162 return -ENODEV; 2163 2164 if (res) { 2165 drvdata->base = devm_ioremap_resource(&pdev->dev, res); 2166 if (IS_ERR(drvdata->base)) { 2167 clk_put(drvdata->pclk); 2168 return PTR_ERR(drvdata->base); 2169 } 2170 } 2171 2172 dev_set_drvdata(&pdev->dev, drvdata); 2173 pm_runtime_get_noresume(&pdev->dev); 2174 pm_runtime_set_active(&pdev->dev); 2175 pm_runtime_enable(&pdev->dev); 2176 2177 ret = etm4_probe(&pdev->dev); 2178 2179 pm_runtime_put(&pdev->dev); 2180 if (ret) 2181 pm_runtime_disable(&pdev->dev); 2182 2183 return ret; 2184 } 2185 2186 static int etm4_probe_cpu(unsigned int cpu) 2187 { 2188 int ret; 2189 struct etm4_init_arg init_arg; 2190 struct csdev_access access = { 0 }; 2191 struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe); 2192 2193 if (!iap) 2194 return 0; 2195 2196 init_arg = *iap; 2197 devm_kfree(init_arg.dev, iap); 2198 *this_cpu_ptr(&delayed_probe) = NULL; 2199 2200 ret = pm_runtime_resume_and_get(init_arg.dev); 2201 if (ret < 0) { 2202 dev_err(init_arg.dev, "Failed to get PM runtime!\n"); 2203 return 0; 2204 } 2205 2206 init_arg.csa = &access; 2207 etm4_init_arch_data(&init_arg); 2208 2209 etm4_add_coresight_dev(&init_arg); 2210 2211 pm_runtime_put(init_arg.dev); 2212 return 0; 2213 } 2214 2215 static struct amba_cs_uci_id uci_id_etm4[] = { 2216 { 2217 /* ETMv4 UCI data */ 2218 .devarch = ETM_DEVARCH_ETMv4x_ARCH, 2219 .devarch_mask = ETM_DEVARCH_ID_MASK, 2220 .devtype = CS_DEVTYPE_PE_TRACE, 2221 } 2222 }; 2223 2224 static void clear_etmdrvdata(void *info) 2225 { 2226 int cpu = *(int *)info; 2227 2228 etmdrvdata[cpu] = NULL; 2229 per_cpu(delayed_probe, cpu) = NULL; 2230 } 2231 2232 static void etm4_remove_dev(struct etmv4_drvdata *drvdata) 2233 { 2234 bool had_delayed_probe; 2235 /* 2236 * Taking hotplug lock here to avoid racing between etm4_remove_dev() 2237 * and CPU hotplug call backs. 2238 */ 2239 cpus_read_lock(); 2240 2241 had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu); 2242 2243 /* 2244 * The readers for etmdrvdata[] are CPU hotplug call backs 2245 * and PM notification call backs. Change etmdrvdata[i] on 2246 * CPU i ensures these call backs has consistent view 2247 * inside one call back function. 2248 */ 2249 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) 2250 clear_etmdrvdata(&drvdata->cpu); 2251 2252 cpus_read_unlock(); 2253 2254 if (!had_delayed_probe) { 2255 etm_perf_symlink(drvdata->csdev, false); 2256 cscfg_unregister_csdev(drvdata->csdev); 2257 coresight_unregister(drvdata->csdev); 2258 } 2259 } 2260 2261 static void etm4_remove_amba(struct amba_device *adev) 2262 { 2263 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev); 2264 2265 if (drvdata) 2266 etm4_remove_dev(drvdata); 2267 } 2268 2269 static int etm4_remove_platform_dev(struct platform_device *pdev) 2270 { 2271 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 2272 2273 if (drvdata) 2274 etm4_remove_dev(drvdata); 2275 pm_runtime_disable(&pdev->dev); 2276 2277 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) 2278 clk_put(drvdata->pclk); 2279 2280 return 0; 2281 } 2282 2283 static const struct amba_id etm4_ids[] = { 2284 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ 2285 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ 2286 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ 2287 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ 2288 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ 2289 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ 2290 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ 2291 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ 2292 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */ 2293 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ 2294 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ 2295 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */ 2296 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ 2297 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ 2298 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ 2299 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */ 2300 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ 2301 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ 2302 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ 2303 /* 2304 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new 2305 * CPUs to the list here. 2306 */ 2307 CS_AMBA_MATCH_ALL_UCI(uci_id_etm4), 2308 {}, 2309 }; 2310 2311 MODULE_DEVICE_TABLE(amba, etm4_ids); 2312 2313 static struct amba_driver etm4x_amba_driver = { 2314 .drv = { 2315 .name = "coresight-etm4x", 2316 .owner = THIS_MODULE, 2317 .suppress_bind_attrs = true, 2318 }, 2319 .probe = etm4_probe_amba, 2320 .remove = etm4_remove_amba, 2321 .id_table = etm4_ids, 2322 }; 2323 2324 #ifdef CONFIG_PM 2325 static int etm4_runtime_suspend(struct device *dev) 2326 { 2327 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 2328 2329 if (drvdata->pclk && !IS_ERR(drvdata->pclk)) 2330 clk_disable_unprepare(drvdata->pclk); 2331 2332 return 0; 2333 } 2334 2335 static int etm4_runtime_resume(struct device *dev) 2336 { 2337 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev); 2338 2339 if (drvdata->pclk && !IS_ERR(drvdata->pclk)) 2340 clk_prepare_enable(drvdata->pclk); 2341 2342 return 0; 2343 } 2344 #endif 2345 2346 static const struct dev_pm_ops etm4_dev_pm_ops = { 2347 SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL) 2348 }; 2349 2350 static const struct of_device_id etm4_sysreg_match[] = { 2351 { .compatible = "arm,coresight-etm4x-sysreg" }, 2352 { .compatible = "arm,embedded-trace-extension" }, 2353 {} 2354 }; 2355 2356 #ifdef CONFIG_ACPI 2357 static const struct acpi_device_id etm4x_acpi_ids[] = { 2358 {"ARMHC500", 0}, /* ARM CoreSight ETM4x */ 2359 {} 2360 }; 2361 MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids); 2362 #endif 2363 2364 static struct platform_driver etm4_platform_driver = { 2365 .probe = etm4_probe_platform_dev, 2366 .remove = etm4_remove_platform_dev, 2367 .driver = { 2368 .name = "coresight-etm4x", 2369 .of_match_table = etm4_sysreg_match, 2370 .acpi_match_table = ACPI_PTR(etm4x_acpi_ids), 2371 .suppress_bind_attrs = true, 2372 .pm = &etm4_dev_pm_ops, 2373 }, 2374 }; 2375 2376 static int __init etm4x_init(void) 2377 { 2378 int ret; 2379 2380 ret = etm4_pm_setup(); 2381 2382 /* etm4_pm_setup() does its own cleanup - exit on error */ 2383 if (ret) 2384 return ret; 2385 2386 ret = amba_driver_register(&etm4x_amba_driver); 2387 if (ret) { 2388 pr_err("Error registering etm4x AMBA driver\n"); 2389 goto clear_pm; 2390 } 2391 2392 ret = platform_driver_register(&etm4_platform_driver); 2393 if (!ret) 2394 return 0; 2395 2396 pr_err("Error registering etm4x platform driver\n"); 2397 amba_driver_unregister(&etm4x_amba_driver); 2398 2399 clear_pm: 2400 etm4_pm_clear(); 2401 return ret; 2402 } 2403 2404 static void __exit etm4x_exit(void) 2405 { 2406 amba_driver_unregister(&etm4x_amba_driver); 2407 platform_driver_unregister(&etm4_platform_driver); 2408 etm4_pm_clear(); 2409 } 2410 2411 module_init(etm4x_init); 2412 module_exit(etm4x_exit); 2413 2414 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 2415 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>"); 2416 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver"); 2417 MODULE_LICENSE("GPL v2"); 2418