1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitops.h> 7 #include <linux/kernel.h> 8 #include <linux/moduleparam.h> 9 #include <linux/init.h> 10 #include <linux/types.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/err.h> 14 #include <linux/fs.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/smp.h> 18 #include <linux/sysfs.h> 19 #include <linux/stat.h> 20 #include <linux/clk.h> 21 #include <linux/cpu.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/coresight.h> 24 #include <linux/coresight-pmu.h> 25 #include <linux/pm_wakeup.h> 26 #include <linux/amba/bus.h> 27 #include <linux/seq_file.h> 28 #include <linux/uaccess.h> 29 #include <linux/perf_event.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/property.h> 33 34 #include <asm/sections.h> 35 #include <asm/sysreg.h> 36 #include <asm/local.h> 37 #include <asm/virt.h> 38 39 #include "coresight-etm4x.h" 40 #include "coresight-etm-perf.h" 41 42 static int boot_enable; 43 module_param(boot_enable, int, 0444); 44 MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); 45 46 #define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */ 47 #define PARAM_PM_SAVE_NEVER 1 /* never save any state */ 48 #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ 49 50 static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; 51 module_param(pm_save_enable, int, 0444); 52 MODULE_PARM_DESC(pm_save_enable, 53 "Save/restore state on power down: 1 = never, 2 = self-hosted"); 54 55 static struct etmv4_drvdata *etmdrvdata[NR_CPUS]; 56 static void etm4_set_default_config(struct etmv4_config *config); 57 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 58 struct perf_event *event); 59 static u64 etm4_get_access_type(struct etmv4_config *config); 60 61 static enum cpuhp_state hp_online; 62 63 struct etm4_init_arg { 64 unsigned int pid; 65 struct etmv4_drvdata *drvdata; 66 struct csdev_access *csa; 67 }; 68 69 /* 70 * Check if TRCSSPCICRn(i) is implemented for a given instance. 71 * 72 * TRCSSPCICRn is implemented only if : 73 * TRCSSPCICR<n> is present only if all of the following are true: 74 * TRCIDR4.NUMSSCC > n. 75 * TRCIDR4.NUMPC > 0b0000 . 76 * TRCSSCSR<n>.PC == 0b1 77 */ 78 static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) 79 { 80 return (n < drvdata->nr_ss_cmp) && 81 drvdata->nr_pe && 82 (drvdata->config.ss_status[n] & TRCSSCSRn_PC); 83 } 84 85 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) 86 { 87 u64 res = 0; 88 89 switch (offset) { 90 ETM4x_READ_SYSREG_CASES(res) 91 default : 92 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n", 93 offset); 94 } 95 96 if (!_relaxed) 97 __iormb(res); /* Imitate the !relaxed I/O helpers */ 98 99 return res; 100 } 101 102 void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit) 103 { 104 if (!_relaxed) 105 __iowmb(); /* Imitate the !relaxed I/O helpers */ 106 if (!_64bit) 107 val &= GENMASK(31, 0); 108 109 switch (offset) { 110 ETM4x_WRITE_SYSREG_CASES(val) 111 default : 112 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n", 113 offset); 114 } 115 } 116 117 static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) 118 { 119 /* Writing 0 to TRCOSLAR unlocks the trace registers */ 120 etm4x_relaxed_write32(csa, 0x0, TRCOSLAR); 121 drvdata->os_unlock = true; 122 isb(); 123 } 124 125 static void etm4_os_unlock(struct etmv4_drvdata *drvdata) 126 { 127 if (!WARN_ON(!drvdata->csdev)) 128 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access); 129 130 } 131 132 static void etm4_os_lock(struct etmv4_drvdata *drvdata) 133 { 134 if (WARN_ON(!drvdata->csdev)) 135 return; 136 137 /* Writing 0x1 to TRCOSLAR locks the trace registers */ 138 etm4x_relaxed_write32(&drvdata->csdev->access, 0x1, TRCOSLAR); 139 drvdata->os_unlock = false; 140 isb(); 141 } 142 143 static void etm4_cs_lock(struct etmv4_drvdata *drvdata, 144 struct csdev_access *csa) 145 { 146 /* Software Lock is only accessible via memory mapped interface */ 147 if (csa->io_mem) 148 CS_LOCK(csa->base); 149 } 150 151 static void etm4_cs_unlock(struct etmv4_drvdata *drvdata, 152 struct csdev_access *csa) 153 { 154 if (csa->io_mem) 155 CS_UNLOCK(csa->base); 156 } 157 158 static int etm4_cpu_id(struct coresight_device *csdev) 159 { 160 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 161 162 return drvdata->cpu; 163 } 164 165 static int etm4_trace_id(struct coresight_device *csdev) 166 { 167 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 168 169 return drvdata->trcid; 170 } 171 172 struct etm4_enable_arg { 173 struct etmv4_drvdata *drvdata; 174 int rc; 175 }; 176 177 #ifdef CONFIG_ETM4X_IMPDEF_FEATURE 178 179 #define HISI_HIP08_AMBA_ID 0x000b6d01 180 #define ETM4_AMBA_MASK 0xfffff 181 #define HISI_HIP08_CORE_COMMIT_MASK 0x3000 182 #define HISI_HIP08_CORE_COMMIT_SHIFT 12 183 #define HISI_HIP08_CORE_COMMIT_FULL 0b00 184 #define HISI_HIP08_CORE_COMMIT_LVL_1 0b01 185 #define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5) 186 187 struct etm4_arch_features { 188 void (*arch_callback)(bool enable); 189 }; 190 191 static bool etm4_hisi_match_pid(unsigned int id) 192 { 193 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID; 194 } 195 196 static void etm4_hisi_config_core_commit(bool enable) 197 { 198 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 : 199 HISI_HIP08_CORE_COMMIT_FULL; 200 u64 val; 201 202 /* 203 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together 204 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01, 205 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1 206 * speed(minimun value). So bit 12 and 13 should be cleared together. 207 */ 208 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG); 209 val &= ~HISI_HIP08_CORE_COMMIT_MASK; 210 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT; 211 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG); 212 } 213 214 static struct etm4_arch_features etm4_features[] = { 215 [ETM4_IMPDEF_HISI_CORE_COMMIT] = { 216 .arch_callback = etm4_hisi_config_core_commit, 217 }, 218 {}, 219 }; 220 221 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 222 { 223 struct etm4_arch_features *ftr; 224 int bit; 225 226 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 227 ftr = &etm4_features[bit]; 228 229 if (ftr->arch_callback) 230 ftr->arch_callback(true); 231 } 232 } 233 234 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 235 { 236 struct etm4_arch_features *ftr; 237 int bit; 238 239 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) { 240 ftr = &etm4_features[bit]; 241 242 if (ftr->arch_callback) 243 ftr->arch_callback(false); 244 } 245 } 246 247 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 248 unsigned int id) 249 { 250 if (etm4_hisi_match_pid(id)) 251 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features); 252 } 253 #else 254 static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) 255 { 256 } 257 258 static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) 259 { 260 } 261 262 static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, 263 unsigned int id) 264 { 265 } 266 #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */ 267 268 static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 269 { 270 int i, rc; 271 struct etmv4_config *config = &drvdata->config; 272 struct coresight_device *csdev = drvdata->csdev; 273 struct device *etm_dev = &csdev->dev; 274 struct csdev_access *csa = &csdev->access; 275 276 277 etm4_cs_unlock(drvdata, csa); 278 etm4_enable_arch_specific(drvdata); 279 280 etm4_os_unlock(drvdata); 281 282 rc = coresight_claim_device_unlocked(csdev); 283 if (rc) 284 goto done; 285 286 /* Disable the trace unit before programming trace registers */ 287 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR); 288 289 /* 290 * If we use system instructions, we need to synchronize the 291 * write to the TRCPRGCTLR, before accessing the TRCSTATR. 292 * See ARM IHI0064F, section 293 * "4.3.7 Synchronization of register updates" 294 */ 295 if (!csa->io_mem) 296 isb(); 297 298 /* wait for TRCSTATR.IDLE to go up */ 299 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) 300 dev_err(etm_dev, 301 "timeout while waiting for Idle Trace Status\n"); 302 if (drvdata->nr_pe) 303 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); 304 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); 305 /* nothing specific implemented */ 306 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); 307 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); 308 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); 309 if (drvdata->stallctl) 310 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); 311 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); 312 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); 313 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR); 314 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR); 315 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR); 316 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); 317 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); 318 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); 319 if (drvdata->nr_pe_cmp) 320 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); 321 for (i = 0; i < drvdata->nrseqstate - 1; i++) 322 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); 323 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); 324 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); 325 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); 326 for (i = 0; i < drvdata->nr_cntr; i++) { 327 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); 328 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); 329 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); 330 } 331 332 /* 333 * Resource selector pair 0 is always implemented and reserved. As 334 * such start at 2. 335 */ 336 for (i = 2; i < drvdata->nr_resource * 2; i++) 337 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); 338 339 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 340 /* always clear status bit on restart if using single-shot */ 341 if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) 342 config->ss_status[i] &= ~BIT(31); 343 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); 344 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); 345 if (etm4x_sspcicrn_present(drvdata, i)) 346 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); 347 } 348 for (i = 0; i < drvdata->nr_addr_cmp; i++) { 349 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); 350 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); 351 } 352 for (i = 0; i < drvdata->numcidc; i++) 353 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); 354 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); 355 if (drvdata->numcidc > 4) 356 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); 357 358 for (i = 0; i < drvdata->numvmidc; i++) 359 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); 360 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); 361 if (drvdata->numvmidc > 4) 362 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); 363 364 if (!drvdata->skip_power_up) { 365 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); 366 367 /* 368 * Request to keep the trace unit powered and also 369 * emulation of powerdown 370 */ 371 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); 372 } 373 374 /* Enable the trace unit */ 375 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR); 376 377 /* Synchronize the register updates for sysreg access */ 378 if (!csa->io_mem) 379 isb(); 380 381 /* wait for TRCSTATR.IDLE to go back down to '0' */ 382 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0)) 383 dev_err(etm_dev, 384 "timeout while waiting for Idle Trace Status\n"); 385 386 /* 387 * As recommended by section 4.3.7 ("Synchronization when using the 388 * memory-mapped interface") of ARM IHI 0064D 389 */ 390 dsb(sy); 391 isb(); 392 393 done: 394 etm4_cs_lock(drvdata, csa); 395 396 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n", 397 drvdata->cpu, rc); 398 return rc; 399 } 400 401 static void etm4_enable_hw_smp_call(void *info) 402 { 403 struct etm4_enable_arg *arg = info; 404 405 if (WARN_ON(!arg)) 406 return; 407 arg->rc = etm4_enable_hw(arg->drvdata); 408 } 409 410 /* 411 * The goal of function etm4_config_timestamp_event() is to configure a 412 * counter that will tell the tracer to emit a timestamp packet when it 413 * reaches zero. This is done in order to get a more fine grained idea 414 * of when instructions are executed so that they can be correlated 415 * with execution on other CPUs. 416 * 417 * To do this the counter itself is configured to self reload and 418 * TRCRSCTLR1 (always true) used to get the counter to decrement. From 419 * there a resource selector is configured with the counter and the 420 * timestamp control register to use the resource selector to trigger the 421 * event that will insert a timestamp packet in the stream. 422 */ 423 static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) 424 { 425 int ctridx, ret = -EINVAL; 426 int counter, rselector; 427 u32 val = 0; 428 struct etmv4_config *config = &drvdata->config; 429 430 /* No point in trying if we don't have at least one counter */ 431 if (!drvdata->nr_cntr) 432 goto out; 433 434 /* Find a counter that hasn't been initialised */ 435 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++) 436 if (config->cntr_val[ctridx] == 0) 437 break; 438 439 /* All the counters have been configured already, bail out */ 440 if (ctridx == drvdata->nr_cntr) { 441 pr_debug("%s: no available counter found\n", __func__); 442 ret = -ENOSPC; 443 goto out; 444 } 445 446 /* 447 * Searching for an available resource selector to use, starting at 448 * '2' since every implementation has at least 2 resource selector. 449 * ETMIDR4 gives the number of resource selector _pairs_, 450 * hence multiply by 2. 451 */ 452 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++) 453 if (!config->res_ctrl[rselector]) 454 break; 455 456 if (rselector == drvdata->nr_resource * 2) { 457 pr_debug("%s: no available resource selector found\n", 458 __func__); 459 ret = -ENOSPC; 460 goto out; 461 } 462 463 /* Remember what counter we used */ 464 counter = 1 << ctridx; 465 466 /* 467 * Initialise original and reload counter value to the smallest 468 * possible value in order to get as much precision as we can. 469 */ 470 config->cntr_val[ctridx] = 1; 471 config->cntrldvr[ctridx] = 1; 472 473 /* Set the trace counter control register */ 474 val = 0x1 << 16 | /* Bit 16, reload counter automatically */ 475 0x0 << 7 | /* Select single resource selector */ 476 0x1; /* Resource selector 1, i.e always true */ 477 478 config->cntr_ctrl[ctridx] = val; 479 480 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */ 481 counter << 0; /* Counter to use */ 482 483 config->res_ctrl[rselector] = val; 484 485 val = 0x0 << 7 | /* Select single resource selector */ 486 rselector; /* Resource selector */ 487 488 config->ts_ctrl = val; 489 490 ret = 0; 491 out: 492 return ret; 493 } 494 495 static int etm4_parse_event_config(struct etmv4_drvdata *drvdata, 496 struct perf_event *event) 497 { 498 int ret = 0; 499 struct etmv4_config *config = &drvdata->config; 500 struct perf_event_attr *attr = &event->attr; 501 502 if (!attr) { 503 ret = -EINVAL; 504 goto out; 505 } 506 507 /* Clear configuration from previous run */ 508 memset(config, 0, sizeof(struct etmv4_config)); 509 510 if (attr->exclude_kernel) 511 config->mode = ETM_MODE_EXCL_KERN; 512 513 if (attr->exclude_user) 514 config->mode = ETM_MODE_EXCL_USER; 515 516 /* Always start from the default config */ 517 etm4_set_default_config(config); 518 519 /* Configure filters specified on the perf cmd line, if any. */ 520 ret = etm4_set_event_filters(drvdata, event); 521 if (ret) 522 goto out; 523 524 /* Go from generic option to ETMv4 specifics */ 525 if (attr->config & BIT(ETM_OPT_CYCACC)) { 526 config->cfg |= BIT(4); 527 /* TRM: Must program this for cycacc to work */ 528 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; 529 } 530 if (attr->config & BIT(ETM_OPT_TS)) { 531 /* 532 * Configure timestamps to be emitted at regular intervals in 533 * order to correlate instructions executed on different CPUs 534 * (CPU-wide trace scenarios). 535 */ 536 ret = etm4_config_timestamp_event(drvdata); 537 538 /* 539 * No need to go further if timestamp intervals can't 540 * be configured. 541 */ 542 if (ret) 543 goto out; 544 545 /* bit[11], Global timestamp tracing bit */ 546 config->cfg |= BIT(11); 547 } 548 549 if (attr->config & BIT(ETM_OPT_CTXTID)) 550 /* bit[6], Context ID tracing bit */ 551 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID); 552 553 /* 554 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID 555 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the 556 * kernel is not running in EL2. 557 */ 558 if (attr->config & BIT(ETM_OPT_CTXTID2)) { 559 if (!is_kernel_in_hyp_mode()) { 560 ret = -EINVAL; 561 goto out; 562 } 563 config->cfg |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT); 564 } 565 566 /* return stack - enable if selected and supported */ 567 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack) 568 /* bit[12], Return stack enable bit */ 569 config->cfg |= BIT(12); 570 571 out: 572 return ret; 573 } 574 575 static int etm4_enable_perf(struct coresight_device *csdev, 576 struct perf_event *event) 577 { 578 int ret = 0; 579 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 580 581 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) { 582 ret = -EINVAL; 583 goto out; 584 } 585 586 /* Configure the tracer based on the session's specifics */ 587 ret = etm4_parse_event_config(drvdata, event); 588 if (ret) 589 goto out; 590 /* And enable it */ 591 ret = etm4_enable_hw(drvdata); 592 593 out: 594 return ret; 595 } 596 597 static int etm4_enable_sysfs(struct coresight_device *csdev) 598 { 599 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 600 struct etm4_enable_arg arg = { }; 601 int ret; 602 603 spin_lock(&drvdata->spinlock); 604 605 /* 606 * Executing etm4_enable_hw on the cpu whose ETM is being enabled 607 * ensures that register writes occur when cpu is powered. 608 */ 609 arg.drvdata = drvdata; 610 ret = smp_call_function_single(drvdata->cpu, 611 etm4_enable_hw_smp_call, &arg, 1); 612 if (!ret) 613 ret = arg.rc; 614 if (!ret) 615 drvdata->sticky_enable = true; 616 spin_unlock(&drvdata->spinlock); 617 618 if (!ret) 619 dev_dbg(&csdev->dev, "ETM tracing enabled\n"); 620 return ret; 621 } 622 623 static int etm4_enable(struct coresight_device *csdev, 624 struct perf_event *event, u32 mode) 625 { 626 int ret; 627 u32 val; 628 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 629 630 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode); 631 632 /* Someone is already using the tracer */ 633 if (val) 634 return -EBUSY; 635 636 switch (mode) { 637 case CS_MODE_SYSFS: 638 ret = etm4_enable_sysfs(csdev); 639 break; 640 case CS_MODE_PERF: 641 ret = etm4_enable_perf(csdev, event); 642 break; 643 default: 644 ret = -EINVAL; 645 } 646 647 /* The tracer didn't start */ 648 if (ret) 649 local_set(&drvdata->mode, CS_MODE_DISABLED); 650 651 return ret; 652 } 653 654 static void etm4_disable_hw(void *info) 655 { 656 u32 control; 657 struct etmv4_drvdata *drvdata = info; 658 struct etmv4_config *config = &drvdata->config; 659 struct coresight_device *csdev = drvdata->csdev; 660 struct device *etm_dev = &csdev->dev; 661 struct csdev_access *csa = &csdev->access; 662 int i; 663 664 etm4_cs_unlock(drvdata, csa); 665 etm4_disable_arch_specific(drvdata); 666 667 if (!drvdata->skip_power_up) { 668 /* power can be removed from the trace unit now */ 669 control = etm4x_relaxed_read32(csa, TRCPDCR); 670 control &= ~TRCPDCR_PU; 671 etm4x_relaxed_write32(csa, control, TRCPDCR); 672 } 673 674 control = etm4x_relaxed_read32(csa, TRCPRGCTLR); 675 676 /* EN, bit[0] Trace unit enable bit */ 677 control &= ~0x1; 678 679 /* 680 * Make sure everything completes before disabling, as recommended 681 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register, 682 * SSTATUS") of ARM IHI 0064D 683 */ 684 dsb(sy); 685 isb(); 686 etm4x_relaxed_write32(csa, control, TRCPRGCTLR); 687 688 /* wait for TRCSTATR.PMSTABLE to go to '1' */ 689 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) 690 dev_err(etm_dev, 691 "timeout while waiting for PM stable Trace Status\n"); 692 693 /* read the status of the single shot comparators */ 694 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 695 config->ss_status[i] = 696 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 697 } 698 699 /* read back the current counter values */ 700 for (i = 0; i < drvdata->nr_cntr; i++) { 701 config->cntr_val[i] = 702 etm4x_relaxed_read32(csa, TRCCNTVRn(i)); 703 } 704 705 coresight_disclaim_device_unlocked(csdev); 706 etm4_cs_lock(drvdata, csa); 707 708 dev_dbg(&drvdata->csdev->dev, 709 "cpu: %d disable smp call done\n", drvdata->cpu); 710 } 711 712 static int etm4_disable_perf(struct coresight_device *csdev, 713 struct perf_event *event) 714 { 715 u32 control; 716 struct etm_filters *filters = event->hw.addr_filters; 717 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 718 719 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) 720 return -EINVAL; 721 722 etm4_disable_hw(drvdata); 723 724 /* 725 * Check if the start/stop logic was active when the unit was stopped. 726 * That way we can re-enable the start/stop logic when the process is 727 * scheduled again. Configuration of the start/stop logic happens in 728 * function etm4_set_event_filters(). 729 */ 730 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR); 731 /* TRCVICTLR::SSSTATUS, bit[9] */ 732 filters->ssstatus = (control & BIT(9)); 733 734 return 0; 735 } 736 737 static void etm4_disable_sysfs(struct coresight_device *csdev) 738 { 739 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 740 741 /* 742 * Taking hotplug lock here protects from clocks getting disabled 743 * with tracing being left on (crash scenario) if user disable occurs 744 * after cpu online mask indicates the cpu is offline but before the 745 * DYING hotplug callback is serviced by the ETM driver. 746 */ 747 cpus_read_lock(); 748 spin_lock(&drvdata->spinlock); 749 750 /* 751 * Executing etm4_disable_hw on the cpu whose ETM is being disabled 752 * ensures that register writes occur when cpu is powered. 753 */ 754 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1); 755 756 spin_unlock(&drvdata->spinlock); 757 cpus_read_unlock(); 758 759 dev_dbg(&csdev->dev, "ETM tracing disabled\n"); 760 } 761 762 static void etm4_disable(struct coresight_device *csdev, 763 struct perf_event *event) 764 { 765 u32 mode; 766 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 767 768 /* 769 * For as long as the tracer isn't disabled another entity can't 770 * change its status. As such we can read the status here without 771 * fearing it will change under us. 772 */ 773 mode = local_read(&drvdata->mode); 774 775 switch (mode) { 776 case CS_MODE_DISABLED: 777 break; 778 case CS_MODE_SYSFS: 779 etm4_disable_sysfs(csdev); 780 break; 781 case CS_MODE_PERF: 782 etm4_disable_perf(csdev, event); 783 break; 784 } 785 786 if (mode) 787 local_set(&drvdata->mode, CS_MODE_DISABLED); 788 } 789 790 static const struct coresight_ops_source etm4_source_ops = { 791 .cpu_id = etm4_cpu_id, 792 .trace_id = etm4_trace_id, 793 .enable = etm4_enable, 794 .disable = etm4_disable, 795 }; 796 797 static const struct coresight_ops etm4_cs_ops = { 798 .source_ops = &etm4_source_ops, 799 }; 800 801 static inline bool cpu_supports_sysreg_trace(void) 802 { 803 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1); 804 805 return ((dfr0 >> ID_AA64DFR0_TRACEVER_SHIFT) & 0xfUL) > 0; 806 } 807 808 static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata, 809 struct csdev_access *csa) 810 { 811 u32 devarch; 812 813 if (!cpu_supports_sysreg_trace()) 814 return false; 815 816 /* 817 * ETMs implementing sysreg access must implement TRCDEVARCH. 818 */ 819 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH); 820 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) 821 return false; 822 *csa = (struct csdev_access) { 823 .io_mem = false, 824 .read = etm4x_sysreg_read, 825 .write = etm4x_sysreg_write, 826 }; 827 828 drvdata->arch = etm_devarch_to_arch(devarch); 829 return true; 830 } 831 832 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, 833 struct csdev_access *csa) 834 { 835 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH); 836 u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1); 837 838 /* 839 * All ETMs must implement TRCDEVARCH to indicate that 840 * the component is an ETMv4. To support any broken 841 * implementations we fall back to TRCIDR1 check, which 842 * is not really reliable. 843 */ 844 if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) { 845 drvdata->arch = etm_devarch_to_arch(devarch); 846 } else { 847 pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n", 848 smp_processor_id(), devarch); 849 850 if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4) 851 return false; 852 drvdata->arch = etm_trcidr_to_arch(idr1); 853 } 854 855 *csa = CSDEV_ACCESS_IOMEM(drvdata->base); 856 return true; 857 } 858 859 static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata, 860 struct csdev_access *csa) 861 { 862 /* 863 * Always choose the memory mapped io, if there is 864 * a memory map to prevent sysreg access on broken 865 * systems. 866 */ 867 if (drvdata->base) 868 return etm4_init_iomem_access(drvdata, csa); 869 870 if (etm4_init_sysreg_access(drvdata, csa)) 871 return true; 872 873 return false; 874 } 875 876 static void cpu_enable_tracing(void) 877 { 878 u64 dfr0 = read_sysreg(id_aa64dfr0_el1); 879 u64 trfcr; 880 881 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_TRACE_FILT_SHIFT)) 882 return; 883 884 /* 885 * If the CPU supports v8.4 SelfHosted Tracing, enable 886 * tracing at the kernel EL and EL0, forcing to use the 887 * virtual time as the timestamp. 888 */ 889 trfcr = (TRFCR_ELx_TS_VIRTUAL | 890 TRFCR_ELx_ExTRE | 891 TRFCR_ELx_E0TRE); 892 893 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */ 894 if (is_kernel_in_hyp_mode()) 895 trfcr |= TRFCR_EL2_CX; 896 897 write_sysreg_s(trfcr, SYS_TRFCR_EL1); 898 } 899 900 static void etm4_init_arch_data(void *info) 901 { 902 u32 etmidr0; 903 u32 etmidr2; 904 u32 etmidr3; 905 u32 etmidr4; 906 u32 etmidr5; 907 struct etm4_init_arg *init_arg = info; 908 struct etmv4_drvdata *drvdata; 909 struct csdev_access *csa; 910 int i; 911 912 drvdata = init_arg->drvdata; 913 csa = init_arg->csa; 914 915 /* 916 * If we are unable to detect the access mechanism, 917 * or unable to detect the trace unit type, fail 918 * early. 919 */ 920 if (!etm4_init_csdev_access(drvdata, csa)) 921 return; 922 923 /* Make sure all registers are accessible */ 924 etm4_os_unlock_csa(drvdata, csa); 925 etm4_cs_unlock(drvdata, csa); 926 927 etm4_check_arch_features(drvdata, init_arg->pid); 928 929 /* find all capabilities of the tracing unit */ 930 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0); 931 932 /* INSTP0, bits[2:1] P0 tracing support field */ 933 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2)) 934 drvdata->instrp0 = true; 935 else 936 drvdata->instrp0 = false; 937 938 /* TRCBB, bit[5] Branch broadcast tracing support bit */ 939 if (BMVAL(etmidr0, 5, 5)) 940 drvdata->trcbb = true; 941 else 942 drvdata->trcbb = false; 943 944 /* TRCCOND, bit[6] Conditional instruction tracing support bit */ 945 if (BMVAL(etmidr0, 6, 6)) 946 drvdata->trccond = true; 947 else 948 drvdata->trccond = false; 949 950 /* TRCCCI, bit[7] Cycle counting instruction bit */ 951 if (BMVAL(etmidr0, 7, 7)) 952 drvdata->trccci = true; 953 else 954 drvdata->trccci = false; 955 956 /* RETSTACK, bit[9] Return stack bit */ 957 if (BMVAL(etmidr0, 9, 9)) 958 drvdata->retstack = true; 959 else 960 drvdata->retstack = false; 961 962 /* NUMEVENT, bits[11:10] Number of events field */ 963 drvdata->nr_event = BMVAL(etmidr0, 10, 11); 964 /* QSUPP, bits[16:15] Q element support field */ 965 drvdata->q_support = BMVAL(etmidr0, 15, 16); 966 /* TSSIZE, bits[28:24] Global timestamp size field */ 967 drvdata->ts_size = BMVAL(etmidr0, 24, 28); 968 969 /* maximum size of resources */ 970 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2); 971 /* CIDSIZE, bits[9:5] Indicates the Context ID size */ 972 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9); 973 /* VMIDSIZE, bits[14:10] Indicates the VMID size */ 974 drvdata->vmid_size = BMVAL(etmidr2, 10, 14); 975 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ 976 drvdata->ccsize = BMVAL(etmidr2, 25, 28); 977 978 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); 979 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ 980 drvdata->ccitmin = BMVAL(etmidr3, 0, 11); 981 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ 982 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19); 983 drvdata->config.s_ex_level = drvdata->s_ex_level; 984 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ 985 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23); 986 987 /* 988 * TRCERR, bit[24] whether a trace unit can trace a 989 * system error exception. 990 */ 991 if (BMVAL(etmidr3, 24, 24)) 992 drvdata->trc_error = true; 993 else 994 drvdata->trc_error = false; 995 996 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ 997 if (BMVAL(etmidr3, 25, 25)) 998 drvdata->syncpr = true; 999 else 1000 drvdata->syncpr = false; 1001 1002 /* STALLCTL, bit[26] is stall control implemented? */ 1003 if (BMVAL(etmidr3, 26, 26)) 1004 drvdata->stallctl = true; 1005 else 1006 drvdata->stallctl = false; 1007 1008 /* SYSSTALL, bit[27] implementation can support stall control? */ 1009 if (BMVAL(etmidr3, 27, 27)) 1010 drvdata->sysstall = true; 1011 else 1012 drvdata->sysstall = false; 1013 1014 /* 1015 * NUMPROC - the number of PEs available for tracing, 5bits 1016 * = TRCIDR3.bits[13:12]bits[30:28] 1017 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0) 1018 * bits[3:0] = TRCIDR3.bits[30:28] 1019 */ 1020 drvdata->nr_pe = (BMVAL(etmidr3, 12, 13) << 3) | BMVAL(etmidr3, 28, 30); 1021 1022 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ 1023 if (BMVAL(etmidr3, 31, 31)) 1024 drvdata->nooverflow = true; 1025 else 1026 drvdata->nooverflow = false; 1027 1028 /* number of resources trace unit supports */ 1029 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4); 1030 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ 1031 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3); 1032 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ 1033 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15); 1034 /* 1035 * NUMRSPAIR, bits[19:16] 1036 * The number of resource pairs conveyed by the HW starts at 0, i.e a 1037 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on. 1038 * As such add 1 to the value of NUMRSPAIR for a better representation. 1039 * 1040 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available - 1041 * the default TRUE and FALSE resource selectors are omitted. 1042 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. 1043 */ 1044 drvdata->nr_resource = BMVAL(etmidr4, 16, 19); 1045 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) 1046 drvdata->nr_resource += 1; 1047 /* 1048 * NUMSSCC, bits[23:20] the number of single-shot 1049 * comparator control for tracing. Read any status regs as these 1050 * also contain RO capability data. 1051 */ 1052 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23); 1053 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1054 drvdata->config.ss_status[i] = 1055 etm4x_relaxed_read32(csa, TRCSSCSRn(i)); 1056 } 1057 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ 1058 drvdata->numcidc = BMVAL(etmidr4, 24, 27); 1059 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ 1060 drvdata->numvmidc = BMVAL(etmidr4, 28, 31); 1061 1062 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5); 1063 /* NUMEXTIN, bits[8:0] number of external inputs implemented */ 1064 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8); 1065 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ 1066 drvdata->trcid_size = BMVAL(etmidr5, 16, 21); 1067 /* ATBTRIG, bit[22] implementation can support ATB triggers? */ 1068 if (BMVAL(etmidr5, 22, 22)) 1069 drvdata->atbtrig = true; 1070 else 1071 drvdata->atbtrig = false; 1072 /* 1073 * LPOVERRIDE, bit[23] implementation supports 1074 * low-power state override 1075 */ 1076 if (BMVAL(etmidr5, 23, 23) && (!drvdata->skip_power_up)) 1077 drvdata->lpoverride = true; 1078 else 1079 drvdata->lpoverride = false; 1080 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ 1081 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27); 1082 /* NUMCNTR, bits[30:28] number of counters available for tracing */ 1083 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30); 1084 etm4_cs_lock(drvdata, csa); 1085 cpu_enable_tracing(); 1086 } 1087 1088 static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) 1089 { 1090 return etm4_get_access_type(config) << TRCVICTLR_EXLEVEL_SHIFT; 1091 } 1092 1093 /* Set ELx trace filter access in the TRCVICTLR register */ 1094 static void etm4_set_victlr_access(struct etmv4_config *config) 1095 { 1096 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK; 1097 config->vinst_ctrl |= etm4_get_victlr_access_type(config); 1098 } 1099 1100 static void etm4_set_default_config(struct etmv4_config *config) 1101 { 1102 /* disable all events tracing */ 1103 config->eventctrl0 = 0x0; 1104 config->eventctrl1 = 0x0; 1105 1106 /* disable stalling */ 1107 config->stall_ctrl = 0x0; 1108 1109 /* enable trace synchronization every 4096 bytes, if available */ 1110 config->syncfreq = 0xC; 1111 1112 /* disable timestamp event */ 1113 config->ts_ctrl = 0x0; 1114 1115 /* TRCVICTLR::EVENT = 0x01, select the always on logic */ 1116 config->vinst_ctrl = BIT(0); 1117 1118 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */ 1119 etm4_set_victlr_access(config); 1120 } 1121 1122 static u64 etm4_get_ns_access_type(struct etmv4_config *config) 1123 { 1124 u64 access_type = 0; 1125 1126 /* 1127 * EXLEVEL_NS, for NonSecure Exception levels. 1128 * The mask here is a generic value and must be 1129 * shifted to the corresponding field for the registers 1130 */ 1131 if (!is_kernel_in_hyp_mode()) { 1132 /* Stay away from hypervisor mode for non-VHE */ 1133 access_type = ETM_EXLEVEL_NS_HYP; 1134 if (config->mode & ETM_MODE_EXCL_KERN) 1135 access_type |= ETM_EXLEVEL_NS_OS; 1136 } else if (config->mode & ETM_MODE_EXCL_KERN) { 1137 access_type = ETM_EXLEVEL_NS_HYP; 1138 } 1139 1140 if (config->mode & ETM_MODE_EXCL_USER) 1141 access_type |= ETM_EXLEVEL_NS_APP; 1142 1143 return access_type; 1144 } 1145 1146 /* 1147 * Construct the exception level masks for a given config. 1148 * This must be shifted to the corresponding register field 1149 * for usage. 1150 */ 1151 static u64 etm4_get_access_type(struct etmv4_config *config) 1152 { 1153 /* All Secure exception levels are excluded from the trace */ 1154 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level; 1155 } 1156 1157 static u64 etm4_get_comparator_access_type(struct etmv4_config *config) 1158 { 1159 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT; 1160 } 1161 1162 static void etm4_set_comparator_filter(struct etmv4_config *config, 1163 u64 start, u64 stop, int comparator) 1164 { 1165 u64 access_type = etm4_get_comparator_access_type(config); 1166 1167 /* First half of default address comparator */ 1168 config->addr_val[comparator] = start; 1169 config->addr_acc[comparator] = access_type; 1170 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE; 1171 1172 /* Second half of default address comparator */ 1173 config->addr_val[comparator + 1] = stop; 1174 config->addr_acc[comparator + 1] = access_type; 1175 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE; 1176 1177 /* 1178 * Configure the ViewInst function to include this address range 1179 * comparator. 1180 * 1181 * @comparator is divided by two since it is the index in the 1182 * etmv4_config::addr_val array but register TRCVIIECTLR deals with 1183 * address range comparator _pairs_. 1184 * 1185 * Therefore: 1186 * index 0 -> compatator pair 0 1187 * index 2 -> comparator pair 1 1188 * index 4 -> comparator pair 2 1189 * ... 1190 * index 14 -> comparator pair 7 1191 */ 1192 config->viiectlr |= BIT(comparator / 2); 1193 } 1194 1195 static void etm4_set_start_stop_filter(struct etmv4_config *config, 1196 u64 address, int comparator, 1197 enum etm_addr_type type) 1198 { 1199 int shift; 1200 u64 access_type = etm4_get_comparator_access_type(config); 1201 1202 /* Configure the comparator */ 1203 config->addr_val[comparator] = address; 1204 config->addr_acc[comparator] = access_type; 1205 config->addr_type[comparator] = type; 1206 1207 /* 1208 * Configure ViewInst Start-Stop control register. 1209 * Addresses configured to start tracing go from bit 0 to n-1, 1210 * while those configured to stop tracing from 16 to 16 + n-1. 1211 */ 1212 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16); 1213 config->vissctlr |= BIT(shift + comparator); 1214 } 1215 1216 static void etm4_set_default_filter(struct etmv4_config *config) 1217 { 1218 /* Trace everything 'default' filter achieved by no filtering */ 1219 config->viiectlr = 0x0; 1220 1221 /* 1222 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1223 * in the started state 1224 */ 1225 config->vinst_ctrl |= BIT(9); 1226 config->mode |= ETM_MODE_VIEWINST_STARTSTOP; 1227 1228 /* No start-stop filtering for ViewInst */ 1229 config->vissctlr = 0x0; 1230 } 1231 1232 static void etm4_set_default(struct etmv4_config *config) 1233 { 1234 if (WARN_ON_ONCE(!config)) 1235 return; 1236 1237 /* 1238 * Make default initialisation trace everything 1239 * 1240 * This is done by a minimum default config sufficient to enable 1241 * full instruction trace - with a default filter for trace all 1242 * achieved by having no filtering. 1243 */ 1244 etm4_set_default_config(config); 1245 etm4_set_default_filter(config); 1246 } 1247 1248 static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type) 1249 { 1250 int nr_comparator, index = 0; 1251 struct etmv4_config *config = &drvdata->config; 1252 1253 /* 1254 * nr_addr_cmp holds the number of comparator _pair_, so time 2 1255 * for the total number of comparators. 1256 */ 1257 nr_comparator = drvdata->nr_addr_cmp * 2; 1258 1259 /* Go through the tally of comparators looking for a free one. */ 1260 while (index < nr_comparator) { 1261 switch (type) { 1262 case ETM_ADDR_TYPE_RANGE: 1263 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE && 1264 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE) 1265 return index; 1266 1267 /* Address range comparators go in pairs */ 1268 index += 2; 1269 break; 1270 case ETM_ADDR_TYPE_START: 1271 case ETM_ADDR_TYPE_STOP: 1272 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE) 1273 return index; 1274 1275 /* Start/stop address can have odd indexes */ 1276 index += 1; 1277 break; 1278 default: 1279 return -EINVAL; 1280 } 1281 } 1282 1283 /* If we are here all the comparators have been used. */ 1284 return -ENOSPC; 1285 } 1286 1287 static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, 1288 struct perf_event *event) 1289 { 1290 int i, comparator, ret = 0; 1291 u64 address; 1292 struct etmv4_config *config = &drvdata->config; 1293 struct etm_filters *filters = event->hw.addr_filters; 1294 1295 if (!filters) 1296 goto default_filter; 1297 1298 /* Sync events with what Perf got */ 1299 perf_event_addr_filters_sync(event); 1300 1301 /* 1302 * If there are no filters to deal with simply go ahead with 1303 * the default filter, i.e the entire address range. 1304 */ 1305 if (!filters->nr_filters) 1306 goto default_filter; 1307 1308 for (i = 0; i < filters->nr_filters; i++) { 1309 struct etm_filter *filter = &filters->etm_filter[i]; 1310 enum etm_addr_type type = filter->type; 1311 1312 /* See if a comparator is free. */ 1313 comparator = etm4_get_next_comparator(drvdata, type); 1314 if (comparator < 0) { 1315 ret = comparator; 1316 goto out; 1317 } 1318 1319 switch (type) { 1320 case ETM_ADDR_TYPE_RANGE: 1321 etm4_set_comparator_filter(config, 1322 filter->start_addr, 1323 filter->stop_addr, 1324 comparator); 1325 /* 1326 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is 1327 * in the started state 1328 */ 1329 config->vinst_ctrl |= BIT(9); 1330 1331 /* No start-stop filtering for ViewInst */ 1332 config->vissctlr = 0x0; 1333 break; 1334 case ETM_ADDR_TYPE_START: 1335 case ETM_ADDR_TYPE_STOP: 1336 /* Get the right start or stop address */ 1337 address = (type == ETM_ADDR_TYPE_START ? 1338 filter->start_addr : 1339 filter->stop_addr); 1340 1341 /* Configure comparator */ 1342 etm4_set_start_stop_filter(config, address, 1343 comparator, type); 1344 1345 /* 1346 * If filters::ssstatus == 1, trace acquisition was 1347 * started but the process was yanked away before the 1348 * the stop address was hit. As such the start/stop 1349 * logic needs to be re-started so that tracing can 1350 * resume where it left. 1351 * 1352 * The start/stop logic status when a process is 1353 * scheduled out is checked in function 1354 * etm4_disable_perf(). 1355 */ 1356 if (filters->ssstatus) 1357 config->vinst_ctrl |= BIT(9); 1358 1359 /* No include/exclude filtering for ViewInst */ 1360 config->viiectlr = 0x0; 1361 break; 1362 default: 1363 ret = -EINVAL; 1364 goto out; 1365 } 1366 } 1367 1368 goto out; 1369 1370 1371 default_filter: 1372 etm4_set_default_filter(config); 1373 1374 out: 1375 return ret; 1376 } 1377 1378 void etm4_config_trace_mode(struct etmv4_config *config) 1379 { 1380 u32 mode; 1381 1382 mode = config->mode; 1383 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER); 1384 1385 /* excluding kernel AND user space doesn't make sense */ 1386 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)); 1387 1388 /* nothing to do if neither flags are set */ 1389 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER)) 1390 return; 1391 1392 etm4_set_victlr_access(config); 1393 } 1394 1395 static int etm4_online_cpu(unsigned int cpu) 1396 { 1397 if (!etmdrvdata[cpu]) 1398 return 0; 1399 1400 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable) 1401 coresight_enable(etmdrvdata[cpu]->csdev); 1402 return 0; 1403 } 1404 1405 static int etm4_starting_cpu(unsigned int cpu) 1406 { 1407 if (!etmdrvdata[cpu]) 1408 return 0; 1409 1410 spin_lock(&etmdrvdata[cpu]->spinlock); 1411 if (!etmdrvdata[cpu]->os_unlock) 1412 etm4_os_unlock(etmdrvdata[cpu]); 1413 1414 if (local_read(&etmdrvdata[cpu]->mode)) 1415 etm4_enable_hw(etmdrvdata[cpu]); 1416 spin_unlock(&etmdrvdata[cpu]->spinlock); 1417 return 0; 1418 } 1419 1420 static int etm4_dying_cpu(unsigned int cpu) 1421 { 1422 if (!etmdrvdata[cpu]) 1423 return 0; 1424 1425 spin_lock(&etmdrvdata[cpu]->spinlock); 1426 if (local_read(&etmdrvdata[cpu]->mode)) 1427 etm4_disable_hw(etmdrvdata[cpu]); 1428 spin_unlock(&etmdrvdata[cpu]->spinlock); 1429 return 0; 1430 } 1431 1432 static void etm4_init_trace_id(struct etmv4_drvdata *drvdata) 1433 { 1434 drvdata->trcid = coresight_get_trace_id(drvdata->cpu); 1435 } 1436 1437 static int etm4_cpu_save(struct etmv4_drvdata *drvdata) 1438 { 1439 int i, ret = 0; 1440 struct etmv4_save_state *state; 1441 struct coresight_device *csdev = drvdata->csdev; 1442 struct csdev_access *csa; 1443 struct device *etm_dev; 1444 1445 if (WARN_ON(!csdev)) 1446 return -ENODEV; 1447 1448 etm_dev = &csdev->dev; 1449 csa = &csdev->access; 1450 1451 /* 1452 * As recommended by 3.4.1 ("The procedure when powering down the PE") 1453 * of ARM IHI 0064D 1454 */ 1455 dsb(sy); 1456 isb(); 1457 1458 etm4_cs_unlock(drvdata, csa); 1459 /* Lock the OS lock to disable trace and external debugger access */ 1460 etm4_os_lock(drvdata); 1461 1462 /* wait for TRCSTATR.PMSTABLE to go up */ 1463 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) { 1464 dev_err(etm_dev, 1465 "timeout while waiting for PM Stable Status\n"); 1466 etm4_os_unlock(drvdata); 1467 ret = -EBUSY; 1468 goto out; 1469 } 1470 1471 state = drvdata->save_state; 1472 1473 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR); 1474 if (drvdata->nr_pe) 1475 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR); 1476 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR); 1477 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR); 1478 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R); 1479 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R); 1480 if (drvdata->stallctl) 1481 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR); 1482 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR); 1483 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR); 1484 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); 1485 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); 1486 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); 1487 state->trcqctlr = etm4x_read32(csa, TRCQCTLR); 1488 1489 state->trcvictlr = etm4x_read32(csa, TRCVICTLR); 1490 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); 1491 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR); 1492 if (drvdata->nr_pe_cmp) 1493 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); 1494 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR); 1495 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR); 1496 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR); 1497 1498 for (i = 0; i < drvdata->nrseqstate - 1; i++) 1499 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); 1500 1501 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); 1502 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); 1503 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR); 1504 1505 for (i = 0; i < drvdata->nr_cntr; i++) { 1506 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i)); 1507 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i)); 1508 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i)); 1509 } 1510 1511 for (i = 0; i < drvdata->nr_resource * 2; i++) 1512 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i)); 1513 1514 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1515 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); 1516 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i)); 1517 if (etm4x_sspcicrn_present(drvdata, i)) 1518 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i)); 1519 } 1520 1521 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 1522 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); 1523 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); 1524 } 1525 1526 /* 1527 * Data trace stream is architecturally prohibited for A profile cores 1528 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per 1529 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace 1530 * unit") of ARM IHI 0064D. 1531 */ 1532 1533 for (i = 0; i < drvdata->numcidc; i++) 1534 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); 1535 1536 for (i = 0; i < drvdata->numvmidc; i++) 1537 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); 1538 1539 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); 1540 if (drvdata->numcidc > 4) 1541 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1); 1542 1543 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); 1544 if (drvdata->numvmidc > 4) 1545 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); 1546 1547 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR); 1548 1549 if (!drvdata->skip_power_up) 1550 state->trcpdcr = etm4x_read32(csa, TRCPDCR); 1551 1552 /* wait for TRCSTATR.IDLE to go up */ 1553 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) { 1554 dev_err(etm_dev, 1555 "timeout while waiting for Idle Trace Status\n"); 1556 etm4_os_unlock(drvdata); 1557 ret = -EBUSY; 1558 goto out; 1559 } 1560 1561 drvdata->state_needs_restore = true; 1562 1563 /* 1564 * Power can be removed from the trace unit now. We do this to 1565 * potentially save power on systems that respect the TRCPDCR_PU 1566 * despite requesting software to save/restore state. 1567 */ 1568 if (!drvdata->skip_power_up) 1569 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), 1570 TRCPDCR); 1571 out: 1572 etm4_cs_lock(drvdata, csa); 1573 return ret; 1574 } 1575 1576 static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) 1577 { 1578 int i; 1579 struct etmv4_save_state *state = drvdata->save_state; 1580 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); 1581 struct csdev_access *csa = &tmp_csa; 1582 1583 etm4_cs_unlock(drvdata, csa); 1584 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 1585 1586 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR); 1587 if (drvdata->nr_pe) 1588 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); 1589 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); 1590 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); 1591 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); 1592 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); 1593 if (drvdata->stallctl) 1594 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); 1595 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); 1596 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); 1597 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); 1598 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); 1599 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); 1600 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); 1601 1602 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); 1603 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); 1604 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); 1605 if (drvdata->nr_pe_cmp) 1606 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); 1607 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR); 1608 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR); 1609 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR); 1610 1611 for (i = 0; i < drvdata->nrseqstate - 1; i++) 1612 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); 1613 1614 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); 1615 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); 1616 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); 1617 1618 for (i = 0; i < drvdata->nr_cntr; i++) { 1619 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); 1620 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); 1621 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); 1622 } 1623 1624 for (i = 0; i < drvdata->nr_resource * 2; i++) 1625 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); 1626 1627 for (i = 0; i < drvdata->nr_ss_cmp; i++) { 1628 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); 1629 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); 1630 if (etm4x_sspcicrn_present(drvdata, i)) 1631 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); 1632 } 1633 1634 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { 1635 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); 1636 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); 1637 } 1638 1639 for (i = 0; i < drvdata->numcidc; i++) 1640 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); 1641 1642 for (i = 0; i < drvdata->numvmidc; i++) 1643 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); 1644 1645 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); 1646 if (drvdata->numcidc > 4) 1647 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); 1648 1649 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); 1650 if (drvdata->numvmidc > 4) 1651 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); 1652 1653 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); 1654 1655 if (!drvdata->skip_power_up) 1656 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); 1657 1658 drvdata->state_needs_restore = false; 1659 1660 /* 1661 * As recommended by section 4.3.7 ("Synchronization when using the 1662 * memory-mapped interface") of ARM IHI 0064D 1663 */ 1664 dsb(sy); 1665 isb(); 1666 1667 /* Unlock the OS lock to re-enable trace and external debug access */ 1668 etm4_os_unlock(drvdata); 1669 etm4_cs_lock(drvdata, csa); 1670 } 1671 1672 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd, 1673 void *v) 1674 { 1675 struct etmv4_drvdata *drvdata; 1676 unsigned int cpu = smp_processor_id(); 1677 1678 if (!etmdrvdata[cpu]) 1679 return NOTIFY_OK; 1680 1681 drvdata = etmdrvdata[cpu]; 1682 1683 if (!drvdata->save_state) 1684 return NOTIFY_OK; 1685 1686 if (WARN_ON_ONCE(drvdata->cpu != cpu)) 1687 return NOTIFY_BAD; 1688 1689 switch (cmd) { 1690 case CPU_PM_ENTER: 1691 /* save the state if self-hosted coresight is in use */ 1692 if (local_read(&drvdata->mode)) 1693 if (etm4_cpu_save(drvdata)) 1694 return NOTIFY_BAD; 1695 break; 1696 case CPU_PM_EXIT: 1697 case CPU_PM_ENTER_FAILED: 1698 if (drvdata->state_needs_restore) 1699 etm4_cpu_restore(drvdata); 1700 break; 1701 default: 1702 return NOTIFY_DONE; 1703 } 1704 1705 return NOTIFY_OK; 1706 } 1707 1708 static struct notifier_block etm4_cpu_pm_nb = { 1709 .notifier_call = etm4_cpu_pm_notify, 1710 }; 1711 1712 /* Setup PM. Deals with error conditions and counts */ 1713 static int __init etm4_pm_setup(void) 1714 { 1715 int ret; 1716 1717 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb); 1718 if (ret) 1719 return ret; 1720 1721 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING, 1722 "arm/coresight4:starting", 1723 etm4_starting_cpu, etm4_dying_cpu); 1724 1725 if (ret) 1726 goto unregister_notifier; 1727 1728 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, 1729 "arm/coresight4:online", 1730 etm4_online_cpu, NULL); 1731 1732 /* HP dyn state ID returned in ret on success */ 1733 if (ret > 0) { 1734 hp_online = ret; 1735 return 0; 1736 } 1737 1738 /* failed dyn state - remove others */ 1739 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 1740 1741 unregister_notifier: 1742 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 1743 return ret; 1744 } 1745 1746 static void etm4_pm_clear(void) 1747 { 1748 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb); 1749 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING); 1750 if (hp_online) { 1751 cpuhp_remove_state_nocalls(hp_online); 1752 hp_online = 0; 1753 } 1754 } 1755 1756 static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) 1757 { 1758 int ret; 1759 struct coresight_platform_data *pdata = NULL; 1760 struct etmv4_drvdata *drvdata; 1761 struct coresight_desc desc = { 0 }; 1762 struct etm4_init_arg init_arg = { 0 }; 1763 1764 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 1765 if (!drvdata) 1766 return -ENOMEM; 1767 1768 dev_set_drvdata(dev, drvdata); 1769 1770 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE) 1771 pm_save_enable = coresight_loses_context_with_cpu(dev) ? 1772 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER; 1773 1774 if (pm_save_enable != PARAM_PM_SAVE_NEVER) { 1775 drvdata->save_state = devm_kmalloc(dev, 1776 sizeof(struct etmv4_save_state), GFP_KERNEL); 1777 if (!drvdata->save_state) 1778 return -ENOMEM; 1779 } 1780 1781 drvdata->base = base; 1782 1783 spin_lock_init(&drvdata->spinlock); 1784 1785 drvdata->cpu = coresight_get_cpu(dev); 1786 if (drvdata->cpu < 0) 1787 return drvdata->cpu; 1788 1789 desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu); 1790 if (!desc.name) 1791 return -ENOMEM; 1792 1793 init_arg.drvdata = drvdata; 1794 init_arg.csa = &desc.access; 1795 init_arg.pid = etm_pid; 1796 1797 if (smp_call_function_single(drvdata->cpu, 1798 etm4_init_arch_data, &init_arg, 1)) 1799 dev_err(dev, "ETM arch init failed\n"); 1800 1801 if (!drvdata->arch) 1802 return -EINVAL; 1803 1804 /* TRCPDCR is not accessible with system instructions. */ 1805 if (!desc.access.io_mem || 1806 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) 1807 drvdata->skip_power_up = true; 1808 1809 etm4_init_trace_id(drvdata); 1810 etm4_set_default(&drvdata->config); 1811 1812 pdata = coresight_get_platform_data(dev); 1813 if (IS_ERR(pdata)) 1814 return PTR_ERR(pdata); 1815 1816 dev->platform_data = pdata; 1817 1818 desc.type = CORESIGHT_DEV_TYPE_SOURCE; 1819 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC; 1820 desc.ops = &etm4_cs_ops; 1821 desc.pdata = pdata; 1822 desc.dev = dev; 1823 desc.groups = coresight_etmv4_groups; 1824 drvdata->csdev = coresight_register(&desc); 1825 if (IS_ERR(drvdata->csdev)) 1826 return PTR_ERR(drvdata->csdev); 1827 1828 ret = etm_perf_symlink(drvdata->csdev, true); 1829 if (ret) { 1830 coresight_unregister(drvdata->csdev); 1831 return ret; 1832 } 1833 1834 etmdrvdata[drvdata->cpu] = drvdata; 1835 1836 dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n", 1837 drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch), 1838 ETM_ARCH_MINOR_VERSION(drvdata->arch)); 1839 1840 if (boot_enable) { 1841 coresight_enable(drvdata->csdev); 1842 drvdata->boot_enable = true; 1843 } 1844 1845 return 0; 1846 } 1847 1848 static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id) 1849 { 1850 void __iomem *base; 1851 struct device *dev = &adev->dev; 1852 struct resource *res = &adev->res; 1853 int ret; 1854 1855 /* Validity for the resource is already checked by the AMBA core */ 1856 base = devm_ioremap_resource(dev, res); 1857 if (IS_ERR(base)) 1858 return PTR_ERR(base); 1859 1860 ret = etm4_probe(dev, base, id->id); 1861 if (!ret) 1862 pm_runtime_put(&adev->dev); 1863 1864 return ret; 1865 } 1866 1867 static int etm4_probe_platform_dev(struct platform_device *pdev) 1868 { 1869 int ret; 1870 1871 pm_runtime_get_noresume(&pdev->dev); 1872 pm_runtime_set_active(&pdev->dev); 1873 pm_runtime_enable(&pdev->dev); 1874 1875 /* 1876 * System register based devices could match the 1877 * HW by reading appropriate registers on the HW 1878 * and thus we could skip the PID. 1879 */ 1880 ret = etm4_probe(&pdev->dev, NULL, 0); 1881 1882 pm_runtime_put(&pdev->dev); 1883 return ret; 1884 } 1885 1886 static struct amba_cs_uci_id uci_id_etm4[] = { 1887 { 1888 /* ETMv4 UCI data */ 1889 .devarch = ETM_DEVARCH_ETMv4x_ARCH, 1890 .devarch_mask = ETM_DEVARCH_ID_MASK, 1891 .devtype = 0x00000013, 1892 } 1893 }; 1894 1895 static void clear_etmdrvdata(void *info) 1896 { 1897 int cpu = *(int *)info; 1898 1899 etmdrvdata[cpu] = NULL; 1900 } 1901 1902 static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata) 1903 { 1904 etm_perf_symlink(drvdata->csdev, false); 1905 /* 1906 * Taking hotplug lock here to avoid racing between etm4_remove_dev() 1907 * and CPU hotplug call backs. 1908 */ 1909 cpus_read_lock(); 1910 /* 1911 * The readers for etmdrvdata[] are CPU hotplug call backs 1912 * and PM notification call backs. Change etmdrvdata[i] on 1913 * CPU i ensures these call backs has consistent view 1914 * inside one call back function. 1915 */ 1916 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1)) 1917 etmdrvdata[drvdata->cpu] = NULL; 1918 1919 cpus_read_unlock(); 1920 1921 coresight_unregister(drvdata->csdev); 1922 1923 return 0; 1924 } 1925 1926 static void __exit etm4_remove_amba(struct amba_device *adev) 1927 { 1928 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev); 1929 1930 if (drvdata) 1931 etm4_remove_dev(drvdata); 1932 } 1933 1934 static int __exit etm4_remove_platform_dev(struct platform_device *pdev) 1935 { 1936 int ret = 0; 1937 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev); 1938 1939 if (drvdata) 1940 ret = etm4_remove_dev(drvdata); 1941 pm_runtime_disable(&pdev->dev); 1942 return ret; 1943 } 1944 1945 static const struct amba_id etm4_ids[] = { 1946 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */ 1947 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ 1948 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ 1949 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ 1950 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ 1951 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ 1952 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ 1953 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */ 1954 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */ 1955 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */ 1956 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */ 1957 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */ 1958 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */ 1959 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */ 1960 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */ 1961 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */ 1962 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */ 1963 {}, 1964 }; 1965 1966 MODULE_DEVICE_TABLE(amba, etm4_ids); 1967 1968 static struct amba_driver etm4x_amba_driver = { 1969 .drv = { 1970 .name = "coresight-etm4x", 1971 .owner = THIS_MODULE, 1972 .suppress_bind_attrs = true, 1973 }, 1974 .probe = etm4_probe_amba, 1975 .remove = etm4_remove_amba, 1976 .id_table = etm4_ids, 1977 }; 1978 1979 static const struct of_device_id etm4_sysreg_match[] = { 1980 { .compatible = "arm,coresight-etm4x-sysreg" }, 1981 {} 1982 }; 1983 1984 static struct platform_driver etm4_platform_driver = { 1985 .probe = etm4_probe_platform_dev, 1986 .remove = etm4_remove_platform_dev, 1987 .driver = { 1988 .name = "coresight-etm4x", 1989 .of_match_table = etm4_sysreg_match, 1990 .suppress_bind_attrs = true, 1991 }, 1992 }; 1993 1994 static int __init etm4x_init(void) 1995 { 1996 int ret; 1997 1998 ret = etm4_pm_setup(); 1999 2000 /* etm4_pm_setup() does its own cleanup - exit on error */ 2001 if (ret) 2002 return ret; 2003 2004 ret = amba_driver_register(&etm4x_amba_driver); 2005 if (ret) { 2006 pr_err("Error registering etm4x AMBA driver\n"); 2007 goto clear_pm; 2008 } 2009 2010 ret = platform_driver_register(&etm4_platform_driver); 2011 if (!ret) 2012 return 0; 2013 2014 pr_err("Error registering etm4x platform driver\n"); 2015 amba_driver_unregister(&etm4x_amba_driver); 2016 2017 clear_pm: 2018 etm4_pm_clear(); 2019 return ret; 2020 } 2021 2022 static void __exit etm4x_exit(void) 2023 { 2024 amba_driver_unregister(&etm4x_amba_driver); 2025 platform_driver_unregister(&etm4_platform_driver); 2026 etm4_pm_clear(); 2027 } 2028 2029 module_init(etm4x_init); 2030 module_exit(etm4x_exit); 2031 2032 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>"); 2033 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>"); 2034 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver"); 2035 MODULE_LICENSE("GPL v2"); 2036