1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight Embedded Trace Buffer driver 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/types.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/err.h> 15 #include <linux/fs.h> 16 #include <linux/miscdevice.h> 17 #include <linux/uaccess.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/seq_file.h> 22 #include <linux/coresight.h> 23 #include <linux/amba/bus.h> 24 #include <linux/clk.h> 25 #include <linux/circ_buf.h> 26 #include <linux/mm.h> 27 #include <linux/perf_event.h> 28 29 30 #include "coresight-priv.h" 31 #include "coresight-etm-perf.h" 32 33 #define ETB_RAM_DEPTH_REG 0x004 34 #define ETB_STATUS_REG 0x00c 35 #define ETB_RAM_READ_DATA_REG 0x010 36 #define ETB_RAM_READ_POINTER 0x014 37 #define ETB_RAM_WRITE_POINTER 0x018 38 #define ETB_TRG 0x01c 39 #define ETB_CTL_REG 0x020 40 #define ETB_RWD_REG 0x024 41 #define ETB_FFSR 0x300 42 #define ETB_FFCR 0x304 43 #define ETB_ITMISCOP0 0xee0 44 #define ETB_ITTRFLINACK 0xee4 45 #define ETB_ITTRFLIN 0xee8 46 #define ETB_ITATBDATA0 0xeeC 47 #define ETB_ITATBCTR2 0xef0 48 #define ETB_ITATBCTR1 0xef4 49 #define ETB_ITATBCTR0 0xef8 50 51 /* register description */ 52 /* STS - 0x00C */ 53 #define ETB_STATUS_RAM_FULL BIT(0) 54 /* CTL - 0x020 */ 55 #define ETB_CTL_CAPT_EN BIT(0) 56 /* FFCR - 0x304 */ 57 #define ETB_FFCR_EN_FTC BIT(0) 58 #define ETB_FFCR_FON_MAN BIT(6) 59 #define ETB_FFCR_STOP_FI BIT(12) 60 #define ETB_FFCR_STOP_TRIGGER BIT(13) 61 62 #define ETB_FFCR_BIT 6 63 #define ETB_FFSR_BIT 1 64 #define ETB_FRAME_SIZE_WORDS 4 65 66 /** 67 * struct etb_drvdata - specifics associated to an ETB component 68 * @base: memory mapped base address for this component. 69 * @dev: the device entity associated to this component. 70 * @atclk: optional clock for the core parts of the ETB. 71 * @csdev: component vitals needed by the framework. 72 * @miscdev: specifics to handle "/dev/xyz.etb" entry. 73 * @spinlock: only one at a time pls. 74 * @reading: synchronise user space access to etb buffer. 75 * @pid: Process ID of the process being monitored by the session 76 * that is using this component. 77 * @buf: area of memory where ETB buffer content gets sent. 78 * @mode: this ETB is being used. 79 * @buffer_depth: size of @buf. 80 * @trigger_cntr: amount of words to store after a trigger. 81 */ 82 struct etb_drvdata { 83 void __iomem *base; 84 struct device *dev; 85 struct clk *atclk; 86 struct coresight_device *csdev; 87 struct miscdevice miscdev; 88 spinlock_t spinlock; 89 local_t reading; 90 pid_t pid; 91 u8 *buf; 92 u32 mode; 93 u32 buffer_depth; 94 u32 trigger_cntr; 95 }; 96 97 static int etb_set_buffer(struct coresight_device *csdev, 98 struct perf_output_handle *handle); 99 100 static inline unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) 101 { 102 return readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); 103 } 104 105 static void __etb_enable_hw(struct etb_drvdata *drvdata) 106 { 107 int i; 108 u32 depth; 109 110 CS_UNLOCK(drvdata->base); 111 112 depth = drvdata->buffer_depth; 113 /* reset write RAM pointer address */ 114 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 115 /* clear entire RAM buffer */ 116 for (i = 0; i < depth; i++) 117 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); 118 119 /* reset write RAM pointer address */ 120 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 121 /* reset read RAM pointer address */ 122 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 123 124 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); 125 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER, 126 drvdata->base + ETB_FFCR); 127 /* ETB trace capture enable */ 128 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); 129 130 CS_LOCK(drvdata->base); 131 } 132 133 static int etb_enable_hw(struct etb_drvdata *drvdata) 134 { 135 int rc = coresight_claim_device(drvdata->base); 136 137 if (rc) 138 return rc; 139 140 __etb_enable_hw(drvdata); 141 return 0; 142 } 143 144 static int etb_enable_sysfs(struct coresight_device *csdev) 145 { 146 int ret = 0; 147 unsigned long flags; 148 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 149 150 spin_lock_irqsave(&drvdata->spinlock, flags); 151 152 /* Don't messup with perf sessions. */ 153 if (drvdata->mode == CS_MODE_PERF) { 154 ret = -EBUSY; 155 goto out; 156 } 157 158 if (drvdata->mode == CS_MODE_DISABLED) { 159 ret = etb_enable_hw(drvdata); 160 if (ret) 161 goto out; 162 163 drvdata->mode = CS_MODE_SYSFS; 164 } 165 166 atomic_inc(csdev->refcnt); 167 out: 168 spin_unlock_irqrestore(&drvdata->spinlock, flags); 169 return ret; 170 } 171 172 static int etb_enable_perf(struct coresight_device *csdev, void *data) 173 { 174 int ret = 0; 175 pid_t pid; 176 unsigned long flags; 177 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 178 struct perf_output_handle *handle = data; 179 180 spin_lock_irqsave(&drvdata->spinlock, flags); 181 182 /* No need to continue if the component is already in used by sysFS. */ 183 if (drvdata->mode == CS_MODE_SYSFS) { 184 ret = -EBUSY; 185 goto out; 186 } 187 188 /* Get a handle on the pid of the process to monitor */ 189 pid = task_pid_nr(handle->event->owner); 190 191 if (drvdata->pid != -1 && drvdata->pid != pid) { 192 ret = -EBUSY; 193 goto out; 194 } 195 196 /* 197 * No HW configuration is needed if the sink is already in 198 * use for this session. 199 */ 200 if (drvdata->pid == pid) { 201 atomic_inc(csdev->refcnt); 202 goto out; 203 } 204 205 /* 206 * We don't have an internal state to clean up if we fail to setup 207 * the perf buffer. So we can perform the step before we turn the 208 * ETB on and leave without cleaning up. 209 */ 210 ret = etb_set_buffer(csdev, handle); 211 if (ret) 212 goto out; 213 214 ret = etb_enable_hw(drvdata); 215 if (!ret) { 216 /* Associate with monitored process. */ 217 drvdata->pid = pid; 218 drvdata->mode = CS_MODE_PERF; 219 atomic_inc(csdev->refcnt); 220 } 221 222 out: 223 spin_unlock_irqrestore(&drvdata->spinlock, flags); 224 return ret; 225 } 226 227 static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) 228 { 229 int ret; 230 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 231 232 switch (mode) { 233 case CS_MODE_SYSFS: 234 ret = etb_enable_sysfs(csdev); 235 break; 236 case CS_MODE_PERF: 237 ret = etb_enable_perf(csdev, data); 238 break; 239 default: 240 ret = -EINVAL; 241 break; 242 } 243 244 if (ret) 245 return ret; 246 247 dev_dbg(drvdata->dev, "ETB enabled\n"); 248 return 0; 249 } 250 251 static void __etb_disable_hw(struct etb_drvdata *drvdata) 252 { 253 u32 ffcr; 254 255 CS_UNLOCK(drvdata->base); 256 257 ffcr = readl_relaxed(drvdata->base + ETB_FFCR); 258 /* stop formatter when a stop has completed */ 259 ffcr |= ETB_FFCR_STOP_FI; 260 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 261 /* manually generate a flush of the system */ 262 ffcr |= ETB_FFCR_FON_MAN; 263 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 264 265 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { 266 dev_err(drvdata->dev, 267 "timeout while waiting for completion of Manual Flush\n"); 268 } 269 270 /* disable trace capture */ 271 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); 272 273 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { 274 dev_err(drvdata->dev, 275 "timeout while waiting for Formatter to Stop\n"); 276 } 277 278 CS_LOCK(drvdata->base); 279 } 280 281 static void etb_dump_hw(struct etb_drvdata *drvdata) 282 { 283 bool lost = false; 284 int i; 285 u8 *buf_ptr; 286 u32 read_data, depth; 287 u32 read_ptr, write_ptr; 288 u32 frame_off, frame_endoff; 289 290 CS_UNLOCK(drvdata->base); 291 292 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 293 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 294 295 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS; 296 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off; 297 if (frame_off) { 298 dev_err(drvdata->dev, 299 "write_ptr: %lu not aligned to formatter frame size\n", 300 (unsigned long)write_ptr); 301 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n", 302 (unsigned long)frame_off, (unsigned long)frame_endoff); 303 write_ptr += frame_endoff; 304 } 305 306 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) 307 & ETB_STATUS_RAM_FULL) == 0) { 308 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 309 } else { 310 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); 311 lost = true; 312 } 313 314 depth = drvdata->buffer_depth; 315 buf_ptr = drvdata->buf; 316 for (i = 0; i < depth; i++) { 317 read_data = readl_relaxed(drvdata->base + 318 ETB_RAM_READ_DATA_REG); 319 *(u32 *)buf_ptr = read_data; 320 buf_ptr += 4; 321 } 322 323 if (lost) 324 coresight_insert_barrier_packet(drvdata->buf); 325 326 if (frame_off) { 327 buf_ptr -= (frame_endoff * 4); 328 for (i = 0; i < frame_endoff; i++) { 329 *buf_ptr++ = 0x0; 330 *buf_ptr++ = 0x0; 331 *buf_ptr++ = 0x0; 332 *buf_ptr++ = 0x0; 333 } 334 } 335 336 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 337 338 CS_LOCK(drvdata->base); 339 } 340 341 static void etb_disable_hw(struct etb_drvdata *drvdata) 342 { 343 __etb_disable_hw(drvdata); 344 etb_dump_hw(drvdata); 345 coresight_disclaim_device(drvdata->base); 346 } 347 348 static int etb_disable(struct coresight_device *csdev) 349 { 350 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 351 unsigned long flags; 352 353 spin_lock_irqsave(&drvdata->spinlock, flags); 354 355 if (atomic_dec_return(csdev->refcnt)) { 356 spin_unlock_irqrestore(&drvdata->spinlock, flags); 357 return -EBUSY; 358 } 359 360 /* Complain if we (somehow) got out of sync */ 361 WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED); 362 etb_disable_hw(drvdata); 363 /* Dissociate from monitored process. */ 364 drvdata->pid = -1; 365 drvdata->mode = CS_MODE_DISABLED; 366 spin_unlock_irqrestore(&drvdata->spinlock, flags); 367 368 dev_dbg(drvdata->dev, "ETB disabled\n"); 369 return 0; 370 } 371 372 static void *etb_alloc_buffer(struct coresight_device *csdev, 373 struct perf_event *event, void **pages, 374 int nr_pages, bool overwrite) 375 { 376 int node, cpu = event->cpu; 377 struct cs_buffers *buf; 378 379 if (cpu == -1) 380 cpu = smp_processor_id(); 381 node = cpu_to_node(cpu); 382 383 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); 384 if (!buf) 385 return NULL; 386 387 buf->snapshot = overwrite; 388 buf->nr_pages = nr_pages; 389 buf->data_pages = pages; 390 391 return buf; 392 } 393 394 static void etb_free_buffer(void *config) 395 { 396 struct cs_buffers *buf = config; 397 398 kfree(buf); 399 } 400 401 static int etb_set_buffer(struct coresight_device *csdev, 402 struct perf_output_handle *handle) 403 { 404 int ret = 0; 405 unsigned long head; 406 struct cs_buffers *buf = etm_perf_sink_config(handle); 407 408 if (!buf) 409 return -EINVAL; 410 411 /* wrap head around to the amount of space we have */ 412 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); 413 414 /* find the page to write to */ 415 buf->cur = head / PAGE_SIZE; 416 417 /* and offset within that page */ 418 buf->offset = head % PAGE_SIZE; 419 420 local_set(&buf->data_size, 0); 421 422 return ret; 423 } 424 425 static unsigned long etb_update_buffer(struct coresight_device *csdev, 426 struct perf_output_handle *handle, 427 void *sink_config) 428 { 429 bool lost = false; 430 int i, cur; 431 u8 *buf_ptr; 432 const u32 *barrier; 433 u32 read_ptr, write_ptr, capacity; 434 u32 status, read_data; 435 unsigned long offset, to_read = 0, flags; 436 struct cs_buffers *buf = sink_config; 437 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 438 439 if (!buf) 440 return 0; 441 442 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; 443 444 spin_lock_irqsave(&drvdata->spinlock, flags); 445 446 /* Don't do anything if another tracer is using this sink */ 447 if (atomic_read(csdev->refcnt) != 1) 448 goto out; 449 450 __etb_disable_hw(drvdata); 451 CS_UNLOCK(drvdata->base); 452 453 /* unit is in words, not bytes */ 454 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 455 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 456 457 /* 458 * Entries should be aligned to the frame size. If they are not 459 * go back to the last alignment point to give decoding tools a 460 * chance to fix things. 461 */ 462 if (write_ptr % ETB_FRAME_SIZE_WORDS) { 463 dev_err(drvdata->dev, 464 "write_ptr: %lu not aligned to formatter frame size\n", 465 (unsigned long)write_ptr); 466 467 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1); 468 lost = true; 469 } 470 471 /* 472 * Get a hold of the status register and see if a wrap around 473 * has occurred. If so adjust things accordingly. Otherwise 474 * start at the beginning and go until the write pointer has 475 * been reached. 476 */ 477 status = readl_relaxed(drvdata->base + ETB_STATUS_REG); 478 if (status & ETB_STATUS_RAM_FULL) { 479 lost = true; 480 to_read = capacity; 481 read_ptr = write_ptr; 482 } else { 483 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth); 484 to_read *= ETB_FRAME_SIZE_WORDS; 485 } 486 487 /* 488 * Make sure we don't overwrite data that hasn't been consumed yet. 489 * It is entirely possible that the HW buffer has more data than the 490 * ring buffer can currently handle. If so adjust the start address 491 * to take only the last traces. 492 * 493 * In snapshot mode we are looking to get the latest traces only and as 494 * such, we don't care about not overwriting data that hasn't been 495 * processed by user space. 496 */ 497 if (!buf->snapshot && to_read > handle->size) { 498 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1); 499 500 /* The new read pointer must be frame size aligned */ 501 to_read = handle->size & mask; 502 /* 503 * Move the RAM read pointer up, keeping in mind that 504 * everything is in frame size units. 505 */ 506 read_ptr = (write_ptr + drvdata->buffer_depth) - 507 to_read / ETB_FRAME_SIZE_WORDS; 508 /* Wrap around if need be*/ 509 if (read_ptr > (drvdata->buffer_depth - 1)) 510 read_ptr -= drvdata->buffer_depth; 511 /* let the decoder know we've skipped ahead */ 512 lost = true; 513 } 514 515 if (lost) 516 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); 517 518 /* finally tell HW where we want to start reading from */ 519 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 520 521 cur = buf->cur; 522 offset = buf->offset; 523 barrier = barrier_pkt; 524 525 for (i = 0; i < to_read; i += 4) { 526 buf_ptr = buf->data_pages[cur] + offset; 527 read_data = readl_relaxed(drvdata->base + 528 ETB_RAM_READ_DATA_REG); 529 if (lost && i < CORESIGHT_BARRIER_PKT_SIZE) { 530 read_data = *barrier; 531 barrier++; 532 } 533 534 *(u32 *)buf_ptr = read_data; 535 buf_ptr += 4; 536 537 offset += 4; 538 if (offset >= PAGE_SIZE) { 539 offset = 0; 540 cur++; 541 /* wrap around at the end of the buffer */ 542 cur &= buf->nr_pages - 1; 543 } 544 } 545 546 /* reset ETB buffer for next run */ 547 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 548 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 549 550 /* 551 * In snapshot mode we have to update the handle->head to point 552 * to the new location. 553 */ 554 if (buf->snapshot) { 555 handle->head = (cur * PAGE_SIZE) + offset; 556 to_read = buf->nr_pages << PAGE_SHIFT; 557 } 558 __etb_enable_hw(drvdata); 559 CS_LOCK(drvdata->base); 560 out: 561 spin_unlock_irqrestore(&drvdata->spinlock, flags); 562 563 return to_read; 564 } 565 566 static const struct coresight_ops_sink etb_sink_ops = { 567 .enable = etb_enable, 568 .disable = etb_disable, 569 .alloc_buffer = etb_alloc_buffer, 570 .free_buffer = etb_free_buffer, 571 .update_buffer = etb_update_buffer, 572 }; 573 574 static const struct coresight_ops etb_cs_ops = { 575 .sink_ops = &etb_sink_ops, 576 }; 577 578 static void etb_dump(struct etb_drvdata *drvdata) 579 { 580 unsigned long flags; 581 582 spin_lock_irqsave(&drvdata->spinlock, flags); 583 if (drvdata->mode == CS_MODE_SYSFS) { 584 __etb_disable_hw(drvdata); 585 etb_dump_hw(drvdata); 586 __etb_enable_hw(drvdata); 587 } 588 spin_unlock_irqrestore(&drvdata->spinlock, flags); 589 590 dev_dbg(drvdata->dev, "ETB dumped\n"); 591 } 592 593 static int etb_open(struct inode *inode, struct file *file) 594 { 595 struct etb_drvdata *drvdata = container_of(file->private_data, 596 struct etb_drvdata, miscdev); 597 598 if (local_cmpxchg(&drvdata->reading, 0, 1)) 599 return -EBUSY; 600 601 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__); 602 return 0; 603 } 604 605 static ssize_t etb_read(struct file *file, char __user *data, 606 size_t len, loff_t *ppos) 607 { 608 u32 depth; 609 struct etb_drvdata *drvdata = container_of(file->private_data, 610 struct etb_drvdata, miscdev); 611 612 etb_dump(drvdata); 613 614 depth = drvdata->buffer_depth; 615 if (*ppos + len > depth * 4) 616 len = depth * 4 - *ppos; 617 618 if (copy_to_user(data, drvdata->buf + *ppos, len)) { 619 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__); 620 return -EFAULT; 621 } 622 623 *ppos += len; 624 625 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n", 626 __func__, len, (int)(depth * 4 - *ppos)); 627 return len; 628 } 629 630 static int etb_release(struct inode *inode, struct file *file) 631 { 632 struct etb_drvdata *drvdata = container_of(file->private_data, 633 struct etb_drvdata, miscdev); 634 local_set(&drvdata->reading, 0); 635 636 dev_dbg(drvdata->dev, "%s: released\n", __func__); 637 return 0; 638 } 639 640 static const struct file_operations etb_fops = { 641 .owner = THIS_MODULE, 642 .open = etb_open, 643 .read = etb_read, 644 .release = etb_release, 645 .llseek = no_llseek, 646 }; 647 648 #define coresight_etb10_reg(name, offset) \ 649 coresight_simple_reg32(struct etb_drvdata, name, offset) 650 651 coresight_etb10_reg(rdp, ETB_RAM_DEPTH_REG); 652 coresight_etb10_reg(sts, ETB_STATUS_REG); 653 coresight_etb10_reg(rrp, ETB_RAM_READ_POINTER); 654 coresight_etb10_reg(rwp, ETB_RAM_WRITE_POINTER); 655 coresight_etb10_reg(trg, ETB_TRG); 656 coresight_etb10_reg(ctl, ETB_CTL_REG); 657 coresight_etb10_reg(ffsr, ETB_FFSR); 658 coresight_etb10_reg(ffcr, ETB_FFCR); 659 660 static struct attribute *coresight_etb_mgmt_attrs[] = { 661 &dev_attr_rdp.attr, 662 &dev_attr_sts.attr, 663 &dev_attr_rrp.attr, 664 &dev_attr_rwp.attr, 665 &dev_attr_trg.attr, 666 &dev_attr_ctl.attr, 667 &dev_attr_ffsr.attr, 668 &dev_attr_ffcr.attr, 669 NULL, 670 }; 671 672 static ssize_t trigger_cntr_show(struct device *dev, 673 struct device_attribute *attr, char *buf) 674 { 675 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 676 unsigned long val = drvdata->trigger_cntr; 677 678 return sprintf(buf, "%#lx\n", val); 679 } 680 681 static ssize_t trigger_cntr_store(struct device *dev, 682 struct device_attribute *attr, 683 const char *buf, size_t size) 684 { 685 int ret; 686 unsigned long val; 687 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 688 689 ret = kstrtoul(buf, 16, &val); 690 if (ret) 691 return ret; 692 693 drvdata->trigger_cntr = val; 694 return size; 695 } 696 static DEVICE_ATTR_RW(trigger_cntr); 697 698 static struct attribute *coresight_etb_attrs[] = { 699 &dev_attr_trigger_cntr.attr, 700 NULL, 701 }; 702 703 static const struct attribute_group coresight_etb_group = { 704 .attrs = coresight_etb_attrs, 705 }; 706 707 static const struct attribute_group coresight_etb_mgmt_group = { 708 .attrs = coresight_etb_mgmt_attrs, 709 .name = "mgmt", 710 }; 711 712 const struct attribute_group *coresight_etb_groups[] = { 713 &coresight_etb_group, 714 &coresight_etb_mgmt_group, 715 NULL, 716 }; 717 718 static int etb_probe(struct amba_device *adev, const struct amba_id *id) 719 { 720 int ret; 721 void __iomem *base; 722 struct device *dev = &adev->dev; 723 struct coresight_platform_data *pdata = NULL; 724 struct etb_drvdata *drvdata; 725 struct resource *res = &adev->res; 726 struct coresight_desc desc = { 0 }; 727 struct device_node *np = adev->dev.of_node; 728 729 if (np) { 730 pdata = of_get_coresight_platform_data(dev, np); 731 if (IS_ERR(pdata)) 732 return PTR_ERR(pdata); 733 adev->dev.platform_data = pdata; 734 } 735 736 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 737 if (!drvdata) 738 return -ENOMEM; 739 740 drvdata->dev = &adev->dev; 741 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 742 if (!IS_ERR(drvdata->atclk)) { 743 ret = clk_prepare_enable(drvdata->atclk); 744 if (ret) 745 return ret; 746 } 747 dev_set_drvdata(dev, drvdata); 748 749 /* validity for the resource is already checked by the AMBA core */ 750 base = devm_ioremap_resource(dev, res); 751 if (IS_ERR(base)) 752 return PTR_ERR(base); 753 754 drvdata->base = base; 755 756 spin_lock_init(&drvdata->spinlock); 757 758 drvdata->buffer_depth = etb_get_buffer_depth(drvdata); 759 760 if (drvdata->buffer_depth & 0x80000000) 761 return -EINVAL; 762 763 drvdata->buf = devm_kcalloc(dev, 764 drvdata->buffer_depth, 4, GFP_KERNEL); 765 if (!drvdata->buf) 766 return -ENOMEM; 767 768 /* This device is not associated with a session */ 769 drvdata->pid = -1; 770 771 desc.type = CORESIGHT_DEV_TYPE_SINK; 772 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 773 desc.ops = &etb_cs_ops; 774 desc.pdata = pdata; 775 desc.dev = dev; 776 desc.groups = coresight_etb_groups; 777 drvdata->csdev = coresight_register(&desc); 778 if (IS_ERR(drvdata->csdev)) 779 return PTR_ERR(drvdata->csdev); 780 781 drvdata->miscdev.name = pdata->name; 782 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; 783 drvdata->miscdev.fops = &etb_fops; 784 ret = misc_register(&drvdata->miscdev); 785 if (ret) 786 goto err_misc_register; 787 788 pm_runtime_put(&adev->dev); 789 return 0; 790 791 err_misc_register: 792 coresight_unregister(drvdata->csdev); 793 return ret; 794 } 795 796 #ifdef CONFIG_PM 797 static int etb_runtime_suspend(struct device *dev) 798 { 799 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 800 801 if (drvdata && !IS_ERR(drvdata->atclk)) 802 clk_disable_unprepare(drvdata->atclk); 803 804 return 0; 805 } 806 807 static int etb_runtime_resume(struct device *dev) 808 { 809 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 810 811 if (drvdata && !IS_ERR(drvdata->atclk)) 812 clk_prepare_enable(drvdata->atclk); 813 814 return 0; 815 } 816 #endif 817 818 static const struct dev_pm_ops etb_dev_pm_ops = { 819 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) 820 }; 821 822 static const struct amba_id etb_ids[] = { 823 { 824 .id = 0x000bb907, 825 .mask = 0x000fffff, 826 }, 827 { 0, 0}, 828 }; 829 830 static struct amba_driver etb_driver = { 831 .drv = { 832 .name = "coresight-etb10", 833 .owner = THIS_MODULE, 834 .pm = &etb_dev_pm_ops, 835 .suppress_bind_attrs = true, 836 837 }, 838 .probe = etb_probe, 839 .id_table = etb_ids, 840 }; 841 builtin_amba_driver(etb_driver); 842