1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 2 * 3 * Description: CoreSight Embedded Trace Buffer driver 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <asm/local.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/device.h> 20 #include <linux/io.h> 21 #include <linux/err.h> 22 #include <linux/fs.h> 23 #include <linux/miscdevice.h> 24 #include <linux/uaccess.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/seq_file.h> 29 #include <linux/coresight.h> 30 #include <linux/amba/bus.h> 31 #include <linux/clk.h> 32 #include <linux/circ_buf.h> 33 #include <linux/mm.h> 34 #include <linux/perf_event.h> 35 36 #include <asm/local.h> 37 38 #include "coresight-priv.h" 39 40 #define ETB_RAM_DEPTH_REG 0x004 41 #define ETB_STATUS_REG 0x00c 42 #define ETB_RAM_READ_DATA_REG 0x010 43 #define ETB_RAM_READ_POINTER 0x014 44 #define ETB_RAM_WRITE_POINTER 0x018 45 #define ETB_TRG 0x01c 46 #define ETB_CTL_REG 0x020 47 #define ETB_RWD_REG 0x024 48 #define ETB_FFSR 0x300 49 #define ETB_FFCR 0x304 50 #define ETB_ITMISCOP0 0xee0 51 #define ETB_ITTRFLINACK 0xee4 52 #define ETB_ITTRFLIN 0xee8 53 #define ETB_ITATBDATA0 0xeeC 54 #define ETB_ITATBCTR2 0xef0 55 #define ETB_ITATBCTR1 0xef4 56 #define ETB_ITATBCTR0 0xef8 57 58 /* register description */ 59 /* STS - 0x00C */ 60 #define ETB_STATUS_RAM_FULL BIT(0) 61 /* CTL - 0x020 */ 62 #define ETB_CTL_CAPT_EN BIT(0) 63 /* FFCR - 0x304 */ 64 #define ETB_FFCR_EN_FTC BIT(0) 65 #define ETB_FFCR_FON_MAN BIT(6) 66 #define ETB_FFCR_STOP_FI BIT(12) 67 #define ETB_FFCR_STOP_TRIGGER BIT(13) 68 69 #define ETB_FFCR_BIT 6 70 #define ETB_FFSR_BIT 1 71 #define ETB_FRAME_SIZE_WORDS 4 72 73 /** 74 * struct etb_drvdata - specifics associated to an ETB component 75 * @base: memory mapped base address for this component. 76 * @dev: the device entity associated to this component. 77 * @atclk: optional clock for the core parts of the ETB. 78 * @csdev: component vitals needed by the framework. 79 * @miscdev: specifics to handle "/dev/xyz.etb" entry. 80 * @spinlock: only one at a time pls. 81 * @reading: synchronise user space access to etb buffer. 82 * @mode: this ETB is being used. 83 * @buf: area of memory where ETB buffer content gets sent. 84 * @buffer_depth: size of @buf. 85 * @trigger_cntr: amount of words to store after a trigger. 86 */ 87 struct etb_drvdata { 88 void __iomem *base; 89 struct device *dev; 90 struct clk *atclk; 91 struct coresight_device *csdev; 92 struct miscdevice miscdev; 93 spinlock_t spinlock; 94 local_t reading; 95 local_t mode; 96 u8 *buf; 97 u32 buffer_depth; 98 u32 trigger_cntr; 99 }; 100 101 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) 102 { 103 u32 depth = 0; 104 105 pm_runtime_get_sync(drvdata->dev); 106 107 /* RO registers don't need locking */ 108 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); 109 110 pm_runtime_put(drvdata->dev); 111 return depth; 112 } 113 114 static void etb_enable_hw(struct etb_drvdata *drvdata) 115 { 116 int i; 117 u32 depth; 118 119 CS_UNLOCK(drvdata->base); 120 121 depth = drvdata->buffer_depth; 122 /* reset write RAM pointer address */ 123 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 124 /* clear entire RAM buffer */ 125 for (i = 0; i < depth; i++) 126 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); 127 128 /* reset write RAM pointer address */ 129 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 130 /* reset read RAM pointer address */ 131 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 132 133 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); 134 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER, 135 drvdata->base + ETB_FFCR); 136 /* ETB trace capture enable */ 137 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); 138 139 CS_LOCK(drvdata->base); 140 } 141 142 static int etb_enable(struct coresight_device *csdev, u32 mode) 143 { 144 u32 val; 145 unsigned long flags; 146 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 147 148 val = local_cmpxchg(&drvdata->mode, 149 CS_MODE_DISABLED, mode); 150 /* 151 * When accessing from Perf, a HW buffer can be handled 152 * by a single trace entity. In sysFS mode many tracers 153 * can be logging to the same HW buffer. 154 */ 155 if (val == CS_MODE_PERF) 156 return -EBUSY; 157 158 /* Nothing to do, the tracer is already enabled. */ 159 if (val == CS_MODE_SYSFS) 160 goto out; 161 162 spin_lock_irqsave(&drvdata->spinlock, flags); 163 etb_enable_hw(drvdata); 164 spin_unlock_irqrestore(&drvdata->spinlock, flags); 165 166 out: 167 dev_info(drvdata->dev, "ETB enabled\n"); 168 return 0; 169 } 170 171 static void etb_disable_hw(struct etb_drvdata *drvdata) 172 { 173 u32 ffcr; 174 175 CS_UNLOCK(drvdata->base); 176 177 ffcr = readl_relaxed(drvdata->base + ETB_FFCR); 178 /* stop formatter when a stop has completed */ 179 ffcr |= ETB_FFCR_STOP_FI; 180 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 181 /* manually generate a flush of the system */ 182 ffcr |= ETB_FFCR_FON_MAN; 183 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 184 185 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { 186 dev_err(drvdata->dev, 187 "timeout while waiting for completion of Manual Flush\n"); 188 } 189 190 /* disable trace capture */ 191 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); 192 193 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { 194 dev_err(drvdata->dev, 195 "timeout while waiting for Formatter to Stop\n"); 196 } 197 198 CS_LOCK(drvdata->base); 199 } 200 201 static void etb_dump_hw(struct etb_drvdata *drvdata) 202 { 203 bool lost = false; 204 int i; 205 u8 *buf_ptr; 206 const u32 *barrier; 207 u32 read_data, depth; 208 u32 read_ptr, write_ptr; 209 u32 frame_off, frame_endoff; 210 211 CS_UNLOCK(drvdata->base); 212 213 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 214 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 215 216 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS; 217 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off; 218 if (frame_off) { 219 dev_err(drvdata->dev, 220 "write_ptr: %lu not aligned to formatter frame size\n", 221 (unsigned long)write_ptr); 222 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n", 223 (unsigned long)frame_off, (unsigned long)frame_endoff); 224 write_ptr += frame_endoff; 225 } 226 227 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) 228 & ETB_STATUS_RAM_FULL) == 0) { 229 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 230 } else { 231 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); 232 lost = true; 233 } 234 235 depth = drvdata->buffer_depth; 236 buf_ptr = drvdata->buf; 237 barrier = barrier_pkt; 238 for (i = 0; i < depth; i++) { 239 read_data = readl_relaxed(drvdata->base + 240 ETB_RAM_READ_DATA_REG); 241 if (lost && *barrier) { 242 read_data = *barrier; 243 barrier++; 244 } 245 246 *(u32 *)buf_ptr = read_data; 247 buf_ptr += 4; 248 } 249 250 if (frame_off) { 251 buf_ptr -= (frame_endoff * 4); 252 for (i = 0; i < frame_endoff; i++) { 253 *buf_ptr++ = 0x0; 254 *buf_ptr++ = 0x0; 255 *buf_ptr++ = 0x0; 256 *buf_ptr++ = 0x0; 257 } 258 } 259 260 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 261 262 CS_LOCK(drvdata->base); 263 } 264 265 static void etb_disable(struct coresight_device *csdev) 266 { 267 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 268 unsigned long flags; 269 270 spin_lock_irqsave(&drvdata->spinlock, flags); 271 etb_disable_hw(drvdata); 272 etb_dump_hw(drvdata); 273 spin_unlock_irqrestore(&drvdata->spinlock, flags); 274 275 local_set(&drvdata->mode, CS_MODE_DISABLED); 276 277 dev_info(drvdata->dev, "ETB disabled\n"); 278 } 279 280 static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, 281 void **pages, int nr_pages, bool overwrite) 282 { 283 int node; 284 struct cs_buffers *buf; 285 286 if (cpu == -1) 287 cpu = smp_processor_id(); 288 node = cpu_to_node(cpu); 289 290 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); 291 if (!buf) 292 return NULL; 293 294 buf->snapshot = overwrite; 295 buf->nr_pages = nr_pages; 296 buf->data_pages = pages; 297 298 return buf; 299 } 300 301 static void etb_free_buffer(void *config) 302 { 303 struct cs_buffers *buf = config; 304 305 kfree(buf); 306 } 307 308 static int etb_set_buffer(struct coresight_device *csdev, 309 struct perf_output_handle *handle, 310 void *sink_config) 311 { 312 int ret = 0; 313 unsigned long head; 314 struct cs_buffers *buf = sink_config; 315 316 /* wrap head around to the amount of space we have */ 317 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); 318 319 /* find the page to write to */ 320 buf->cur = head / PAGE_SIZE; 321 322 /* and offset within that page */ 323 buf->offset = head % PAGE_SIZE; 324 325 local_set(&buf->data_size, 0); 326 327 return ret; 328 } 329 330 static unsigned long etb_reset_buffer(struct coresight_device *csdev, 331 struct perf_output_handle *handle, 332 void *sink_config) 333 { 334 unsigned long size = 0; 335 struct cs_buffers *buf = sink_config; 336 337 if (buf) { 338 /* 339 * In snapshot mode ->data_size holds the new address of the 340 * ring buffer's head. The size itself is the whole address 341 * range since we want the latest information. 342 */ 343 if (buf->snapshot) 344 handle->head = local_xchg(&buf->data_size, 345 buf->nr_pages << PAGE_SHIFT); 346 347 /* 348 * Tell the tracer PMU how much we got in this run and if 349 * something went wrong along the way. Nobody else can use 350 * this cs_buffers instance until we are done. As such 351 * resetting parameters here and squaring off with the ring 352 * buffer API in the tracer PMU is fine. 353 */ 354 size = local_xchg(&buf->data_size, 0); 355 } 356 357 return size; 358 } 359 360 static void etb_update_buffer(struct coresight_device *csdev, 361 struct perf_output_handle *handle, 362 void *sink_config) 363 { 364 bool lost = false; 365 int i, cur; 366 u8 *buf_ptr; 367 const u32 *barrier; 368 u32 read_ptr, write_ptr, capacity; 369 u32 status, read_data, to_read; 370 unsigned long offset; 371 struct cs_buffers *buf = sink_config; 372 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 373 374 if (!buf) 375 return; 376 377 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; 378 379 etb_disable_hw(drvdata); 380 CS_UNLOCK(drvdata->base); 381 382 /* unit is in words, not bytes */ 383 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 384 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 385 386 /* 387 * Entries should be aligned to the frame size. If they are not 388 * go back to the last alignment point to give decoding tools a 389 * chance to fix things. 390 */ 391 if (write_ptr % ETB_FRAME_SIZE_WORDS) { 392 dev_err(drvdata->dev, 393 "write_ptr: %lu not aligned to formatter frame size\n", 394 (unsigned long)write_ptr); 395 396 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1); 397 lost = true; 398 } 399 400 /* 401 * Get a hold of the status register and see if a wrap around 402 * has occurred. If so adjust things accordingly. Otherwise 403 * start at the beginning and go until the write pointer has 404 * been reached. 405 */ 406 status = readl_relaxed(drvdata->base + ETB_STATUS_REG); 407 if (status & ETB_STATUS_RAM_FULL) { 408 lost = true; 409 to_read = capacity; 410 read_ptr = write_ptr; 411 } else { 412 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth); 413 to_read *= ETB_FRAME_SIZE_WORDS; 414 } 415 416 /* 417 * Make sure we don't overwrite data that hasn't been consumed yet. 418 * It is entirely possible that the HW buffer has more data than the 419 * ring buffer can currently handle. If so adjust the start address 420 * to take only the last traces. 421 * 422 * In snapshot mode we are looking to get the latest traces only and as 423 * such, we don't care about not overwriting data that hasn't been 424 * processed by user space. 425 */ 426 if (!buf->snapshot && to_read > handle->size) { 427 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1); 428 429 /* The new read pointer must be frame size aligned */ 430 to_read = handle->size & mask; 431 /* 432 * Move the RAM read pointer up, keeping in mind that 433 * everything is in frame size units. 434 */ 435 read_ptr = (write_ptr + drvdata->buffer_depth) - 436 to_read / ETB_FRAME_SIZE_WORDS; 437 /* Wrap around if need be*/ 438 if (read_ptr > (drvdata->buffer_depth - 1)) 439 read_ptr -= drvdata->buffer_depth; 440 /* let the decoder know we've skipped ahead */ 441 lost = true; 442 } 443 444 if (lost) 445 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); 446 447 /* finally tell HW where we want to start reading from */ 448 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 449 450 cur = buf->cur; 451 offset = buf->offset; 452 barrier = barrier_pkt; 453 454 for (i = 0; i < to_read; i += 4) { 455 buf_ptr = buf->data_pages[cur] + offset; 456 read_data = readl_relaxed(drvdata->base + 457 ETB_RAM_READ_DATA_REG); 458 if (lost && *barrier) { 459 read_data = *barrier; 460 barrier++; 461 } 462 463 *(u32 *)buf_ptr = read_data; 464 buf_ptr += 4; 465 466 offset += 4; 467 if (offset >= PAGE_SIZE) { 468 offset = 0; 469 cur++; 470 /* wrap around at the end of the buffer */ 471 cur &= buf->nr_pages - 1; 472 } 473 } 474 475 /* reset ETB buffer for next run */ 476 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 477 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 478 479 /* 480 * In snapshot mode all we have to do is communicate to 481 * perf_aux_output_end() the address of the current head. In full 482 * trace mode the same function expects a size to move rb->aux_head 483 * forward. 484 */ 485 if (buf->snapshot) 486 local_set(&buf->data_size, (cur * PAGE_SIZE) + offset); 487 else 488 local_add(to_read, &buf->data_size); 489 490 etb_enable_hw(drvdata); 491 CS_LOCK(drvdata->base); 492 } 493 494 static const struct coresight_ops_sink etb_sink_ops = { 495 .enable = etb_enable, 496 .disable = etb_disable, 497 .alloc_buffer = etb_alloc_buffer, 498 .free_buffer = etb_free_buffer, 499 .set_buffer = etb_set_buffer, 500 .reset_buffer = etb_reset_buffer, 501 .update_buffer = etb_update_buffer, 502 }; 503 504 static const struct coresight_ops etb_cs_ops = { 505 .sink_ops = &etb_sink_ops, 506 }; 507 508 static void etb_dump(struct etb_drvdata *drvdata) 509 { 510 unsigned long flags; 511 512 spin_lock_irqsave(&drvdata->spinlock, flags); 513 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { 514 etb_disable_hw(drvdata); 515 etb_dump_hw(drvdata); 516 etb_enable_hw(drvdata); 517 } 518 spin_unlock_irqrestore(&drvdata->spinlock, flags); 519 520 dev_info(drvdata->dev, "ETB dumped\n"); 521 } 522 523 static int etb_open(struct inode *inode, struct file *file) 524 { 525 struct etb_drvdata *drvdata = container_of(file->private_data, 526 struct etb_drvdata, miscdev); 527 528 if (local_cmpxchg(&drvdata->reading, 0, 1)) 529 return -EBUSY; 530 531 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__); 532 return 0; 533 } 534 535 static ssize_t etb_read(struct file *file, char __user *data, 536 size_t len, loff_t *ppos) 537 { 538 u32 depth; 539 struct etb_drvdata *drvdata = container_of(file->private_data, 540 struct etb_drvdata, miscdev); 541 542 etb_dump(drvdata); 543 544 depth = drvdata->buffer_depth; 545 if (*ppos + len > depth * 4) 546 len = depth * 4 - *ppos; 547 548 if (copy_to_user(data, drvdata->buf + *ppos, len)) { 549 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__); 550 return -EFAULT; 551 } 552 553 *ppos += len; 554 555 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n", 556 __func__, len, (int)(depth * 4 - *ppos)); 557 return len; 558 } 559 560 static int etb_release(struct inode *inode, struct file *file) 561 { 562 struct etb_drvdata *drvdata = container_of(file->private_data, 563 struct etb_drvdata, miscdev); 564 local_set(&drvdata->reading, 0); 565 566 dev_dbg(drvdata->dev, "%s: released\n", __func__); 567 return 0; 568 } 569 570 static const struct file_operations etb_fops = { 571 .owner = THIS_MODULE, 572 .open = etb_open, 573 .read = etb_read, 574 .release = etb_release, 575 .llseek = no_llseek, 576 }; 577 578 #define coresight_etb10_reg(name, offset) \ 579 coresight_simple_reg32(struct etb_drvdata, name, offset) 580 581 coresight_etb10_reg(rdp, ETB_RAM_DEPTH_REG); 582 coresight_etb10_reg(sts, ETB_STATUS_REG); 583 coresight_etb10_reg(rrp, ETB_RAM_READ_POINTER); 584 coresight_etb10_reg(rwp, ETB_RAM_WRITE_POINTER); 585 coresight_etb10_reg(trg, ETB_TRG); 586 coresight_etb10_reg(ctl, ETB_CTL_REG); 587 coresight_etb10_reg(ffsr, ETB_FFSR); 588 coresight_etb10_reg(ffcr, ETB_FFCR); 589 590 static struct attribute *coresight_etb_mgmt_attrs[] = { 591 &dev_attr_rdp.attr, 592 &dev_attr_sts.attr, 593 &dev_attr_rrp.attr, 594 &dev_attr_rwp.attr, 595 &dev_attr_trg.attr, 596 &dev_attr_ctl.attr, 597 &dev_attr_ffsr.attr, 598 &dev_attr_ffcr.attr, 599 NULL, 600 }; 601 602 static ssize_t trigger_cntr_show(struct device *dev, 603 struct device_attribute *attr, char *buf) 604 { 605 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 606 unsigned long val = drvdata->trigger_cntr; 607 608 return sprintf(buf, "%#lx\n", val); 609 } 610 611 static ssize_t trigger_cntr_store(struct device *dev, 612 struct device_attribute *attr, 613 const char *buf, size_t size) 614 { 615 int ret; 616 unsigned long val; 617 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 618 619 ret = kstrtoul(buf, 16, &val); 620 if (ret) 621 return ret; 622 623 drvdata->trigger_cntr = val; 624 return size; 625 } 626 static DEVICE_ATTR_RW(trigger_cntr); 627 628 static struct attribute *coresight_etb_attrs[] = { 629 &dev_attr_trigger_cntr.attr, 630 NULL, 631 }; 632 633 static const struct attribute_group coresight_etb_group = { 634 .attrs = coresight_etb_attrs, 635 }; 636 637 static const struct attribute_group coresight_etb_mgmt_group = { 638 .attrs = coresight_etb_mgmt_attrs, 639 .name = "mgmt", 640 }; 641 642 const struct attribute_group *coresight_etb_groups[] = { 643 &coresight_etb_group, 644 &coresight_etb_mgmt_group, 645 NULL, 646 }; 647 648 static int etb_probe(struct amba_device *adev, const struct amba_id *id) 649 { 650 int ret; 651 void __iomem *base; 652 struct device *dev = &adev->dev; 653 struct coresight_platform_data *pdata = NULL; 654 struct etb_drvdata *drvdata; 655 struct resource *res = &adev->res; 656 struct coresight_desc desc = { 0 }; 657 struct device_node *np = adev->dev.of_node; 658 659 if (np) { 660 pdata = of_get_coresight_platform_data(dev, np); 661 if (IS_ERR(pdata)) 662 return PTR_ERR(pdata); 663 adev->dev.platform_data = pdata; 664 } 665 666 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 667 if (!drvdata) 668 return -ENOMEM; 669 670 drvdata->dev = &adev->dev; 671 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 672 if (!IS_ERR(drvdata->atclk)) { 673 ret = clk_prepare_enable(drvdata->atclk); 674 if (ret) 675 return ret; 676 } 677 dev_set_drvdata(dev, drvdata); 678 679 /* validity for the resource is already checked by the AMBA core */ 680 base = devm_ioremap_resource(dev, res); 681 if (IS_ERR(base)) 682 return PTR_ERR(base); 683 684 drvdata->base = base; 685 686 spin_lock_init(&drvdata->spinlock); 687 688 drvdata->buffer_depth = etb_get_buffer_depth(drvdata); 689 pm_runtime_put(&adev->dev); 690 691 if (drvdata->buffer_depth & 0x80000000) 692 return -EINVAL; 693 694 drvdata->buf = devm_kzalloc(dev, 695 drvdata->buffer_depth * 4, GFP_KERNEL); 696 if (!drvdata->buf) 697 return -ENOMEM; 698 699 desc.type = CORESIGHT_DEV_TYPE_SINK; 700 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 701 desc.ops = &etb_cs_ops; 702 desc.pdata = pdata; 703 desc.dev = dev; 704 desc.groups = coresight_etb_groups; 705 drvdata->csdev = coresight_register(&desc); 706 if (IS_ERR(drvdata->csdev)) 707 return PTR_ERR(drvdata->csdev); 708 709 drvdata->miscdev.name = pdata->name; 710 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; 711 drvdata->miscdev.fops = &etb_fops; 712 ret = misc_register(&drvdata->miscdev); 713 if (ret) 714 goto err_misc_register; 715 716 return 0; 717 718 err_misc_register: 719 coresight_unregister(drvdata->csdev); 720 return ret; 721 } 722 723 #ifdef CONFIG_PM 724 static int etb_runtime_suspend(struct device *dev) 725 { 726 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 727 728 if (drvdata && !IS_ERR(drvdata->atclk)) 729 clk_disable_unprepare(drvdata->atclk); 730 731 return 0; 732 } 733 734 static int etb_runtime_resume(struct device *dev) 735 { 736 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 737 738 if (drvdata && !IS_ERR(drvdata->atclk)) 739 clk_prepare_enable(drvdata->atclk); 740 741 return 0; 742 } 743 #endif 744 745 static const struct dev_pm_ops etb_dev_pm_ops = { 746 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) 747 }; 748 749 static const struct amba_id etb_ids[] = { 750 { 751 .id = 0x0003b907, 752 .mask = 0x0003ffff, 753 }, 754 { 0, 0}, 755 }; 756 757 static struct amba_driver etb_driver = { 758 .drv = { 759 .name = "coresight-etb10", 760 .owner = THIS_MODULE, 761 .pm = &etb_dev_pm_ops, 762 .suppress_bind_attrs = true, 763 764 }, 765 .probe = etb_probe, 766 .id_table = etb_ids, 767 }; 768 builtin_amba_driver(etb_driver); 769