1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 2 * 3 * Description: CoreSight Embedded Trace Buffer driver 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <asm/local.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/types.h> 19 #include <linux/device.h> 20 #include <linux/io.h> 21 #include <linux/err.h> 22 #include <linux/fs.h> 23 #include <linux/miscdevice.h> 24 #include <linux/uaccess.h> 25 #include <linux/slab.h> 26 #include <linux/spinlock.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/seq_file.h> 29 #include <linux/coresight.h> 30 #include <linux/amba/bus.h> 31 #include <linux/clk.h> 32 #include <linux/circ_buf.h> 33 #include <linux/mm.h> 34 #include <linux/perf_event.h> 35 36 37 #include "coresight-priv.h" 38 39 #define ETB_RAM_DEPTH_REG 0x004 40 #define ETB_STATUS_REG 0x00c 41 #define ETB_RAM_READ_DATA_REG 0x010 42 #define ETB_RAM_READ_POINTER 0x014 43 #define ETB_RAM_WRITE_POINTER 0x018 44 #define ETB_TRG 0x01c 45 #define ETB_CTL_REG 0x020 46 #define ETB_RWD_REG 0x024 47 #define ETB_FFSR 0x300 48 #define ETB_FFCR 0x304 49 #define ETB_ITMISCOP0 0xee0 50 #define ETB_ITTRFLINACK 0xee4 51 #define ETB_ITTRFLIN 0xee8 52 #define ETB_ITATBDATA0 0xeeC 53 #define ETB_ITATBCTR2 0xef0 54 #define ETB_ITATBCTR1 0xef4 55 #define ETB_ITATBCTR0 0xef8 56 57 /* register description */ 58 /* STS - 0x00C */ 59 #define ETB_STATUS_RAM_FULL BIT(0) 60 /* CTL - 0x020 */ 61 #define ETB_CTL_CAPT_EN BIT(0) 62 /* FFCR - 0x304 */ 63 #define ETB_FFCR_EN_FTC BIT(0) 64 #define ETB_FFCR_FON_MAN BIT(6) 65 #define ETB_FFCR_STOP_FI BIT(12) 66 #define ETB_FFCR_STOP_TRIGGER BIT(13) 67 68 #define ETB_FFCR_BIT 6 69 #define ETB_FFSR_BIT 1 70 #define ETB_FRAME_SIZE_WORDS 4 71 72 /** 73 * struct etb_drvdata - specifics associated to an ETB component 74 * @base: memory mapped base address for this component. 75 * @dev: the device entity associated to this component. 76 * @atclk: optional clock for the core parts of the ETB. 77 * @csdev: component vitals needed by the framework. 78 * @miscdev: specifics to handle "/dev/xyz.etb" entry. 79 * @spinlock: only one at a time pls. 80 * @reading: synchronise user space access to etb buffer. 81 * @mode: this ETB is being used. 82 * @buf: area of memory where ETB buffer content gets sent. 83 * @buffer_depth: size of @buf. 84 * @trigger_cntr: amount of words to store after a trigger. 85 */ 86 struct etb_drvdata { 87 void __iomem *base; 88 struct device *dev; 89 struct clk *atclk; 90 struct coresight_device *csdev; 91 struct miscdevice miscdev; 92 spinlock_t spinlock; 93 local_t reading; 94 local_t mode; 95 u8 *buf; 96 u32 buffer_depth; 97 u32 trigger_cntr; 98 }; 99 100 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) 101 { 102 u32 depth = 0; 103 104 pm_runtime_get_sync(drvdata->dev); 105 106 /* RO registers don't need locking */ 107 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); 108 109 pm_runtime_put(drvdata->dev); 110 return depth; 111 } 112 113 static void etb_enable_hw(struct etb_drvdata *drvdata) 114 { 115 int i; 116 u32 depth; 117 118 CS_UNLOCK(drvdata->base); 119 120 depth = drvdata->buffer_depth; 121 /* reset write RAM pointer address */ 122 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 123 /* clear entire RAM buffer */ 124 for (i = 0; i < depth; i++) 125 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); 126 127 /* reset write RAM pointer address */ 128 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 129 /* reset read RAM pointer address */ 130 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 131 132 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); 133 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER, 134 drvdata->base + ETB_FFCR); 135 /* ETB trace capture enable */ 136 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); 137 138 CS_LOCK(drvdata->base); 139 } 140 141 static int etb_enable(struct coresight_device *csdev, u32 mode) 142 { 143 u32 val; 144 unsigned long flags; 145 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 146 147 val = local_cmpxchg(&drvdata->mode, 148 CS_MODE_DISABLED, mode); 149 /* 150 * When accessing from Perf, a HW buffer can be handled 151 * by a single trace entity. In sysFS mode many tracers 152 * can be logging to the same HW buffer. 153 */ 154 if (val == CS_MODE_PERF) 155 return -EBUSY; 156 157 /* Nothing to do, the tracer is already enabled. */ 158 if (val == CS_MODE_SYSFS) 159 goto out; 160 161 spin_lock_irqsave(&drvdata->spinlock, flags); 162 etb_enable_hw(drvdata); 163 spin_unlock_irqrestore(&drvdata->spinlock, flags); 164 165 out: 166 dev_info(drvdata->dev, "ETB enabled\n"); 167 return 0; 168 } 169 170 static void etb_disable_hw(struct etb_drvdata *drvdata) 171 { 172 u32 ffcr; 173 174 CS_UNLOCK(drvdata->base); 175 176 ffcr = readl_relaxed(drvdata->base + ETB_FFCR); 177 /* stop formatter when a stop has completed */ 178 ffcr |= ETB_FFCR_STOP_FI; 179 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 180 /* manually generate a flush of the system */ 181 ffcr |= ETB_FFCR_FON_MAN; 182 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 183 184 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { 185 dev_err(drvdata->dev, 186 "timeout while waiting for completion of Manual Flush\n"); 187 } 188 189 /* disable trace capture */ 190 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); 191 192 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { 193 dev_err(drvdata->dev, 194 "timeout while waiting for Formatter to Stop\n"); 195 } 196 197 CS_LOCK(drvdata->base); 198 } 199 200 static void etb_dump_hw(struct etb_drvdata *drvdata) 201 { 202 bool lost = false; 203 int i; 204 u8 *buf_ptr; 205 const u32 *barrier; 206 u32 read_data, depth; 207 u32 read_ptr, write_ptr; 208 u32 frame_off, frame_endoff; 209 210 CS_UNLOCK(drvdata->base); 211 212 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 213 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 214 215 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS; 216 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off; 217 if (frame_off) { 218 dev_err(drvdata->dev, 219 "write_ptr: %lu not aligned to formatter frame size\n", 220 (unsigned long)write_ptr); 221 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n", 222 (unsigned long)frame_off, (unsigned long)frame_endoff); 223 write_ptr += frame_endoff; 224 } 225 226 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) 227 & ETB_STATUS_RAM_FULL) == 0) { 228 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 229 } else { 230 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); 231 lost = true; 232 } 233 234 depth = drvdata->buffer_depth; 235 buf_ptr = drvdata->buf; 236 barrier = barrier_pkt; 237 for (i = 0; i < depth; i++) { 238 read_data = readl_relaxed(drvdata->base + 239 ETB_RAM_READ_DATA_REG); 240 if (lost && *barrier) { 241 read_data = *barrier; 242 barrier++; 243 } 244 245 *(u32 *)buf_ptr = read_data; 246 buf_ptr += 4; 247 } 248 249 if (frame_off) { 250 buf_ptr -= (frame_endoff * 4); 251 for (i = 0; i < frame_endoff; i++) { 252 *buf_ptr++ = 0x0; 253 *buf_ptr++ = 0x0; 254 *buf_ptr++ = 0x0; 255 *buf_ptr++ = 0x0; 256 } 257 } 258 259 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 260 261 CS_LOCK(drvdata->base); 262 } 263 264 static void etb_disable(struct coresight_device *csdev) 265 { 266 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 267 unsigned long flags; 268 269 spin_lock_irqsave(&drvdata->spinlock, flags); 270 etb_disable_hw(drvdata); 271 etb_dump_hw(drvdata); 272 spin_unlock_irqrestore(&drvdata->spinlock, flags); 273 274 local_set(&drvdata->mode, CS_MODE_DISABLED); 275 276 dev_info(drvdata->dev, "ETB disabled\n"); 277 } 278 279 static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, 280 void **pages, int nr_pages, bool overwrite) 281 { 282 int node; 283 struct cs_buffers *buf; 284 285 if (cpu == -1) 286 cpu = smp_processor_id(); 287 node = cpu_to_node(cpu); 288 289 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); 290 if (!buf) 291 return NULL; 292 293 buf->snapshot = overwrite; 294 buf->nr_pages = nr_pages; 295 buf->data_pages = pages; 296 297 return buf; 298 } 299 300 static void etb_free_buffer(void *config) 301 { 302 struct cs_buffers *buf = config; 303 304 kfree(buf); 305 } 306 307 static int etb_set_buffer(struct coresight_device *csdev, 308 struct perf_output_handle *handle, 309 void *sink_config) 310 { 311 int ret = 0; 312 unsigned long head; 313 struct cs_buffers *buf = sink_config; 314 315 /* wrap head around to the amount of space we have */ 316 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); 317 318 /* find the page to write to */ 319 buf->cur = head / PAGE_SIZE; 320 321 /* and offset within that page */ 322 buf->offset = head % PAGE_SIZE; 323 324 local_set(&buf->data_size, 0); 325 326 return ret; 327 } 328 329 static unsigned long etb_reset_buffer(struct coresight_device *csdev, 330 struct perf_output_handle *handle, 331 void *sink_config) 332 { 333 unsigned long size = 0; 334 struct cs_buffers *buf = sink_config; 335 336 if (buf) { 337 /* 338 * In snapshot mode ->data_size holds the new address of the 339 * ring buffer's head. The size itself is the whole address 340 * range since we want the latest information. 341 */ 342 if (buf->snapshot) 343 handle->head = local_xchg(&buf->data_size, 344 buf->nr_pages << PAGE_SHIFT); 345 346 /* 347 * Tell the tracer PMU how much we got in this run and if 348 * something went wrong along the way. Nobody else can use 349 * this cs_buffers instance until we are done. As such 350 * resetting parameters here and squaring off with the ring 351 * buffer API in the tracer PMU is fine. 352 */ 353 size = local_xchg(&buf->data_size, 0); 354 } 355 356 return size; 357 } 358 359 static void etb_update_buffer(struct coresight_device *csdev, 360 struct perf_output_handle *handle, 361 void *sink_config) 362 { 363 bool lost = false; 364 int i, cur; 365 u8 *buf_ptr; 366 const u32 *barrier; 367 u32 read_ptr, write_ptr, capacity; 368 u32 status, read_data, to_read; 369 unsigned long offset; 370 struct cs_buffers *buf = sink_config; 371 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 372 373 if (!buf) 374 return; 375 376 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; 377 378 etb_disable_hw(drvdata); 379 CS_UNLOCK(drvdata->base); 380 381 /* unit is in words, not bytes */ 382 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 383 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 384 385 /* 386 * Entries should be aligned to the frame size. If they are not 387 * go back to the last alignment point to give decoding tools a 388 * chance to fix things. 389 */ 390 if (write_ptr % ETB_FRAME_SIZE_WORDS) { 391 dev_err(drvdata->dev, 392 "write_ptr: %lu not aligned to formatter frame size\n", 393 (unsigned long)write_ptr); 394 395 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1); 396 lost = true; 397 } 398 399 /* 400 * Get a hold of the status register and see if a wrap around 401 * has occurred. If so adjust things accordingly. Otherwise 402 * start at the beginning and go until the write pointer has 403 * been reached. 404 */ 405 status = readl_relaxed(drvdata->base + ETB_STATUS_REG); 406 if (status & ETB_STATUS_RAM_FULL) { 407 lost = true; 408 to_read = capacity; 409 read_ptr = write_ptr; 410 } else { 411 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth); 412 to_read *= ETB_FRAME_SIZE_WORDS; 413 } 414 415 /* 416 * Make sure we don't overwrite data that hasn't been consumed yet. 417 * It is entirely possible that the HW buffer has more data than the 418 * ring buffer can currently handle. If so adjust the start address 419 * to take only the last traces. 420 * 421 * In snapshot mode we are looking to get the latest traces only and as 422 * such, we don't care about not overwriting data that hasn't been 423 * processed by user space. 424 */ 425 if (!buf->snapshot && to_read > handle->size) { 426 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1); 427 428 /* The new read pointer must be frame size aligned */ 429 to_read = handle->size & mask; 430 /* 431 * Move the RAM read pointer up, keeping in mind that 432 * everything is in frame size units. 433 */ 434 read_ptr = (write_ptr + drvdata->buffer_depth) - 435 to_read / ETB_FRAME_SIZE_WORDS; 436 /* Wrap around if need be*/ 437 if (read_ptr > (drvdata->buffer_depth - 1)) 438 read_ptr -= drvdata->buffer_depth; 439 /* let the decoder know we've skipped ahead */ 440 lost = true; 441 } 442 443 if (lost) 444 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); 445 446 /* finally tell HW where we want to start reading from */ 447 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 448 449 cur = buf->cur; 450 offset = buf->offset; 451 barrier = barrier_pkt; 452 453 for (i = 0; i < to_read; i += 4) { 454 buf_ptr = buf->data_pages[cur] + offset; 455 read_data = readl_relaxed(drvdata->base + 456 ETB_RAM_READ_DATA_REG); 457 if (lost && *barrier) { 458 read_data = *barrier; 459 barrier++; 460 } 461 462 *(u32 *)buf_ptr = read_data; 463 buf_ptr += 4; 464 465 offset += 4; 466 if (offset >= PAGE_SIZE) { 467 offset = 0; 468 cur++; 469 /* wrap around at the end of the buffer */ 470 cur &= buf->nr_pages - 1; 471 } 472 } 473 474 /* reset ETB buffer for next run */ 475 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 476 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 477 478 /* 479 * In snapshot mode all we have to do is communicate to 480 * perf_aux_output_end() the address of the current head. In full 481 * trace mode the same function expects a size to move rb->aux_head 482 * forward. 483 */ 484 if (buf->snapshot) 485 local_set(&buf->data_size, (cur * PAGE_SIZE) + offset); 486 else 487 local_add(to_read, &buf->data_size); 488 489 etb_enable_hw(drvdata); 490 CS_LOCK(drvdata->base); 491 } 492 493 static const struct coresight_ops_sink etb_sink_ops = { 494 .enable = etb_enable, 495 .disable = etb_disable, 496 .alloc_buffer = etb_alloc_buffer, 497 .free_buffer = etb_free_buffer, 498 .set_buffer = etb_set_buffer, 499 .reset_buffer = etb_reset_buffer, 500 .update_buffer = etb_update_buffer, 501 }; 502 503 static const struct coresight_ops etb_cs_ops = { 504 .sink_ops = &etb_sink_ops, 505 }; 506 507 static void etb_dump(struct etb_drvdata *drvdata) 508 { 509 unsigned long flags; 510 511 spin_lock_irqsave(&drvdata->spinlock, flags); 512 if (local_read(&drvdata->mode) == CS_MODE_SYSFS) { 513 etb_disable_hw(drvdata); 514 etb_dump_hw(drvdata); 515 etb_enable_hw(drvdata); 516 } 517 spin_unlock_irqrestore(&drvdata->spinlock, flags); 518 519 dev_info(drvdata->dev, "ETB dumped\n"); 520 } 521 522 static int etb_open(struct inode *inode, struct file *file) 523 { 524 struct etb_drvdata *drvdata = container_of(file->private_data, 525 struct etb_drvdata, miscdev); 526 527 if (local_cmpxchg(&drvdata->reading, 0, 1)) 528 return -EBUSY; 529 530 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__); 531 return 0; 532 } 533 534 static ssize_t etb_read(struct file *file, char __user *data, 535 size_t len, loff_t *ppos) 536 { 537 u32 depth; 538 struct etb_drvdata *drvdata = container_of(file->private_data, 539 struct etb_drvdata, miscdev); 540 541 etb_dump(drvdata); 542 543 depth = drvdata->buffer_depth; 544 if (*ppos + len > depth * 4) 545 len = depth * 4 - *ppos; 546 547 if (copy_to_user(data, drvdata->buf + *ppos, len)) { 548 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__); 549 return -EFAULT; 550 } 551 552 *ppos += len; 553 554 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n", 555 __func__, len, (int)(depth * 4 - *ppos)); 556 return len; 557 } 558 559 static int etb_release(struct inode *inode, struct file *file) 560 { 561 struct etb_drvdata *drvdata = container_of(file->private_data, 562 struct etb_drvdata, miscdev); 563 local_set(&drvdata->reading, 0); 564 565 dev_dbg(drvdata->dev, "%s: released\n", __func__); 566 return 0; 567 } 568 569 static const struct file_operations etb_fops = { 570 .owner = THIS_MODULE, 571 .open = etb_open, 572 .read = etb_read, 573 .release = etb_release, 574 .llseek = no_llseek, 575 }; 576 577 #define coresight_etb10_reg(name, offset) \ 578 coresight_simple_reg32(struct etb_drvdata, name, offset) 579 580 coresight_etb10_reg(rdp, ETB_RAM_DEPTH_REG); 581 coresight_etb10_reg(sts, ETB_STATUS_REG); 582 coresight_etb10_reg(rrp, ETB_RAM_READ_POINTER); 583 coresight_etb10_reg(rwp, ETB_RAM_WRITE_POINTER); 584 coresight_etb10_reg(trg, ETB_TRG); 585 coresight_etb10_reg(ctl, ETB_CTL_REG); 586 coresight_etb10_reg(ffsr, ETB_FFSR); 587 coresight_etb10_reg(ffcr, ETB_FFCR); 588 589 static struct attribute *coresight_etb_mgmt_attrs[] = { 590 &dev_attr_rdp.attr, 591 &dev_attr_sts.attr, 592 &dev_attr_rrp.attr, 593 &dev_attr_rwp.attr, 594 &dev_attr_trg.attr, 595 &dev_attr_ctl.attr, 596 &dev_attr_ffsr.attr, 597 &dev_attr_ffcr.attr, 598 NULL, 599 }; 600 601 static ssize_t trigger_cntr_show(struct device *dev, 602 struct device_attribute *attr, char *buf) 603 { 604 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 605 unsigned long val = drvdata->trigger_cntr; 606 607 return sprintf(buf, "%#lx\n", val); 608 } 609 610 static ssize_t trigger_cntr_store(struct device *dev, 611 struct device_attribute *attr, 612 const char *buf, size_t size) 613 { 614 int ret; 615 unsigned long val; 616 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 617 618 ret = kstrtoul(buf, 16, &val); 619 if (ret) 620 return ret; 621 622 drvdata->trigger_cntr = val; 623 return size; 624 } 625 static DEVICE_ATTR_RW(trigger_cntr); 626 627 static struct attribute *coresight_etb_attrs[] = { 628 &dev_attr_trigger_cntr.attr, 629 NULL, 630 }; 631 632 static const struct attribute_group coresight_etb_group = { 633 .attrs = coresight_etb_attrs, 634 }; 635 636 static const struct attribute_group coresight_etb_mgmt_group = { 637 .attrs = coresight_etb_mgmt_attrs, 638 .name = "mgmt", 639 }; 640 641 const struct attribute_group *coresight_etb_groups[] = { 642 &coresight_etb_group, 643 &coresight_etb_mgmt_group, 644 NULL, 645 }; 646 647 static int etb_probe(struct amba_device *adev, const struct amba_id *id) 648 { 649 int ret; 650 void __iomem *base; 651 struct device *dev = &adev->dev; 652 struct coresight_platform_data *pdata = NULL; 653 struct etb_drvdata *drvdata; 654 struct resource *res = &adev->res; 655 struct coresight_desc desc = { 0 }; 656 struct device_node *np = adev->dev.of_node; 657 658 if (np) { 659 pdata = of_get_coresight_platform_data(dev, np); 660 if (IS_ERR(pdata)) 661 return PTR_ERR(pdata); 662 adev->dev.platform_data = pdata; 663 } 664 665 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 666 if (!drvdata) 667 return -ENOMEM; 668 669 drvdata->dev = &adev->dev; 670 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 671 if (!IS_ERR(drvdata->atclk)) { 672 ret = clk_prepare_enable(drvdata->atclk); 673 if (ret) 674 return ret; 675 } 676 dev_set_drvdata(dev, drvdata); 677 678 /* validity for the resource is already checked by the AMBA core */ 679 base = devm_ioremap_resource(dev, res); 680 if (IS_ERR(base)) 681 return PTR_ERR(base); 682 683 drvdata->base = base; 684 685 spin_lock_init(&drvdata->spinlock); 686 687 drvdata->buffer_depth = etb_get_buffer_depth(drvdata); 688 pm_runtime_put(&adev->dev); 689 690 if (drvdata->buffer_depth & 0x80000000) 691 return -EINVAL; 692 693 drvdata->buf = devm_kzalloc(dev, 694 drvdata->buffer_depth * 4, GFP_KERNEL); 695 if (!drvdata->buf) 696 return -ENOMEM; 697 698 desc.type = CORESIGHT_DEV_TYPE_SINK; 699 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 700 desc.ops = &etb_cs_ops; 701 desc.pdata = pdata; 702 desc.dev = dev; 703 desc.groups = coresight_etb_groups; 704 drvdata->csdev = coresight_register(&desc); 705 if (IS_ERR(drvdata->csdev)) 706 return PTR_ERR(drvdata->csdev); 707 708 drvdata->miscdev.name = pdata->name; 709 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; 710 drvdata->miscdev.fops = &etb_fops; 711 ret = misc_register(&drvdata->miscdev); 712 if (ret) 713 goto err_misc_register; 714 715 return 0; 716 717 err_misc_register: 718 coresight_unregister(drvdata->csdev); 719 return ret; 720 } 721 722 #ifdef CONFIG_PM 723 static int etb_runtime_suspend(struct device *dev) 724 { 725 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 726 727 if (drvdata && !IS_ERR(drvdata->atclk)) 728 clk_disable_unprepare(drvdata->atclk); 729 730 return 0; 731 } 732 733 static int etb_runtime_resume(struct device *dev) 734 { 735 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 736 737 if (drvdata && !IS_ERR(drvdata->atclk)) 738 clk_prepare_enable(drvdata->atclk); 739 740 return 0; 741 } 742 #endif 743 744 static const struct dev_pm_ops etb_dev_pm_ops = { 745 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) 746 }; 747 748 static const struct amba_id etb_ids[] = { 749 { 750 .id = 0x000bb907, 751 .mask = 0x000fffff, 752 }, 753 { 0, 0}, 754 }; 755 756 static struct amba_driver etb_driver = { 757 .drv = { 758 .name = "coresight-etb10", 759 .owner = THIS_MODULE, 760 .pm = &etb_dev_pm_ops, 761 .suppress_bind_attrs = true, 762 763 }, 764 .probe = etb_probe, 765 .id_table = etb_ids, 766 }; 767 builtin_amba_driver(etb_driver); 768