1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved. 4 * 5 * Description: CoreSight Embedded Trace Buffer driver 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/types.h> 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/err.h> 14 #include <linux/fs.h> 15 #include <linux/miscdevice.h> 16 #include <linux/uaccess.h> 17 #include <linux/slab.h> 18 #include <linux/spinlock.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/seq_file.h> 21 #include <linux/coresight.h> 22 #include <linux/amba/bus.h> 23 #include <linux/clk.h> 24 #include <linux/circ_buf.h> 25 #include <linux/mm.h> 26 #include <linux/perf_event.h> 27 28 29 #include "coresight-priv.h" 30 #include "coresight-etm-perf.h" 31 32 #define ETB_RAM_DEPTH_REG 0x004 33 #define ETB_STATUS_REG 0x00c 34 #define ETB_RAM_READ_DATA_REG 0x010 35 #define ETB_RAM_READ_POINTER 0x014 36 #define ETB_RAM_WRITE_POINTER 0x018 37 #define ETB_TRG 0x01c 38 #define ETB_CTL_REG 0x020 39 #define ETB_RWD_REG 0x024 40 #define ETB_FFSR 0x300 41 #define ETB_FFCR 0x304 42 #define ETB_ITMISCOP0 0xee0 43 #define ETB_ITTRFLINACK 0xee4 44 #define ETB_ITTRFLIN 0xee8 45 #define ETB_ITATBDATA0 0xeeC 46 #define ETB_ITATBCTR2 0xef0 47 #define ETB_ITATBCTR1 0xef4 48 #define ETB_ITATBCTR0 0xef8 49 50 /* register description */ 51 /* STS - 0x00C */ 52 #define ETB_STATUS_RAM_FULL BIT(0) 53 /* CTL - 0x020 */ 54 #define ETB_CTL_CAPT_EN BIT(0) 55 /* FFCR - 0x304 */ 56 #define ETB_FFCR_EN_FTC BIT(0) 57 #define ETB_FFCR_FON_MAN BIT(6) 58 #define ETB_FFCR_STOP_FI BIT(12) 59 #define ETB_FFCR_STOP_TRIGGER BIT(13) 60 61 #define ETB_FFCR_BIT 6 62 #define ETB_FFSR_BIT 1 63 #define ETB_FRAME_SIZE_WORDS 4 64 65 /** 66 * struct etb_drvdata - specifics associated to an ETB component 67 * @base: memory mapped base address for this component. 68 * @dev: the device entity associated to this component. 69 * @atclk: optional clock for the core parts of the ETB. 70 * @csdev: component vitals needed by the framework. 71 * @miscdev: specifics to handle "/dev/xyz.etb" entry. 72 * @spinlock: only one at a time pls. 73 * @reading: synchronise user space access to etb buffer. 74 * @buf: area of memory where ETB buffer content gets sent. 75 * @mode: this ETB is being used. 76 * @buffer_depth: size of @buf. 77 * @trigger_cntr: amount of words to store after a trigger. 78 */ 79 struct etb_drvdata { 80 void __iomem *base; 81 struct device *dev; 82 struct clk *atclk; 83 struct coresight_device *csdev; 84 struct miscdevice miscdev; 85 spinlock_t spinlock; 86 local_t reading; 87 u8 *buf; 88 u32 mode; 89 u32 buffer_depth; 90 u32 trigger_cntr; 91 }; 92 93 static int etb_set_buffer(struct coresight_device *csdev, 94 struct perf_output_handle *handle); 95 96 static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) 97 { 98 u32 depth = 0; 99 100 pm_runtime_get_sync(drvdata->dev); 101 102 /* RO registers don't need locking */ 103 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); 104 105 pm_runtime_put(drvdata->dev); 106 return depth; 107 } 108 109 static void __etb_enable_hw(struct etb_drvdata *drvdata) 110 { 111 int i; 112 u32 depth; 113 114 CS_UNLOCK(drvdata->base); 115 116 depth = drvdata->buffer_depth; 117 /* reset write RAM pointer address */ 118 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 119 /* clear entire RAM buffer */ 120 for (i = 0; i < depth; i++) 121 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); 122 123 /* reset write RAM pointer address */ 124 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 125 /* reset read RAM pointer address */ 126 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 127 128 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); 129 writel_relaxed(ETB_FFCR_EN_FTC | ETB_FFCR_STOP_TRIGGER, 130 drvdata->base + ETB_FFCR); 131 /* ETB trace capture enable */ 132 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); 133 134 CS_LOCK(drvdata->base); 135 } 136 137 static int etb_enable_hw(struct etb_drvdata *drvdata) 138 { 139 __etb_enable_hw(drvdata); 140 return 0; 141 } 142 143 static int etb_enable_sysfs(struct coresight_device *csdev) 144 { 145 int ret = 0; 146 unsigned long flags; 147 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 148 149 spin_lock_irqsave(&drvdata->spinlock, flags); 150 151 /* Don't messup with perf sessions. */ 152 if (drvdata->mode == CS_MODE_PERF) { 153 ret = -EBUSY; 154 goto out; 155 } 156 157 /* Nothing to do, the tracer is already enabled. */ 158 if (drvdata->mode == CS_MODE_SYSFS) 159 goto out; 160 161 ret = etb_enable_hw(drvdata); 162 if (!ret) 163 drvdata->mode = CS_MODE_SYSFS; 164 165 out: 166 spin_unlock_irqrestore(&drvdata->spinlock, flags); 167 return ret; 168 } 169 170 static int etb_enable_perf(struct coresight_device *csdev, void *data) 171 { 172 int ret = 0; 173 unsigned long flags; 174 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 175 176 spin_lock_irqsave(&drvdata->spinlock, flags); 177 178 /* No need to continue if the component is already in use. */ 179 if (drvdata->mode != CS_MODE_DISABLED) { 180 ret = -EBUSY; 181 goto out; 182 } 183 184 /* 185 * We don't have an internal state to clean up if we fail to setup 186 * the perf buffer. So we can perform the step before we turn the 187 * ETB on and leave without cleaning up. 188 */ 189 ret = etb_set_buffer(csdev, (struct perf_output_handle *)data); 190 if (ret) 191 goto out; 192 193 ret = etb_enable_hw(drvdata); 194 if (!ret) 195 drvdata->mode = CS_MODE_PERF; 196 197 out: 198 spin_unlock_irqrestore(&drvdata->spinlock, flags); 199 return ret; 200 } 201 202 static int etb_enable(struct coresight_device *csdev, u32 mode, void *data) 203 { 204 int ret; 205 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 206 207 switch (mode) { 208 case CS_MODE_SYSFS: 209 ret = etb_enable_sysfs(csdev); 210 break; 211 case CS_MODE_PERF: 212 ret = etb_enable_perf(csdev, data); 213 break; 214 default: 215 ret = -EINVAL; 216 break; 217 } 218 219 if (ret) 220 return ret; 221 222 dev_dbg(drvdata->dev, "ETB enabled\n"); 223 return 0; 224 } 225 226 static void etb_disable_hw(struct etb_drvdata *drvdata) 227 { 228 u32 ffcr; 229 230 CS_UNLOCK(drvdata->base); 231 232 ffcr = readl_relaxed(drvdata->base + ETB_FFCR); 233 /* stop formatter when a stop has completed */ 234 ffcr |= ETB_FFCR_STOP_FI; 235 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 236 /* manually generate a flush of the system */ 237 ffcr |= ETB_FFCR_FON_MAN; 238 writel_relaxed(ffcr, drvdata->base + ETB_FFCR); 239 240 if (coresight_timeout(drvdata->base, ETB_FFCR, ETB_FFCR_BIT, 0)) { 241 dev_err(drvdata->dev, 242 "timeout while waiting for completion of Manual Flush\n"); 243 } 244 245 /* disable trace capture */ 246 writel_relaxed(0x0, drvdata->base + ETB_CTL_REG); 247 248 if (coresight_timeout(drvdata->base, ETB_FFSR, ETB_FFSR_BIT, 1)) { 249 dev_err(drvdata->dev, 250 "timeout while waiting for Formatter to Stop\n"); 251 } 252 253 CS_LOCK(drvdata->base); 254 } 255 256 static void etb_dump_hw(struct etb_drvdata *drvdata) 257 { 258 bool lost = false; 259 int i; 260 u8 *buf_ptr; 261 u32 read_data, depth; 262 u32 read_ptr, write_ptr; 263 u32 frame_off, frame_endoff; 264 265 CS_UNLOCK(drvdata->base); 266 267 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 268 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 269 270 frame_off = write_ptr % ETB_FRAME_SIZE_WORDS; 271 frame_endoff = ETB_FRAME_SIZE_WORDS - frame_off; 272 if (frame_off) { 273 dev_err(drvdata->dev, 274 "write_ptr: %lu not aligned to formatter frame size\n", 275 (unsigned long)write_ptr); 276 dev_err(drvdata->dev, "frameoff: %lu, frame_endoff: %lu\n", 277 (unsigned long)frame_off, (unsigned long)frame_endoff); 278 write_ptr += frame_endoff; 279 } 280 281 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) 282 & ETB_STATUS_RAM_FULL) == 0) { 283 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 284 } else { 285 writel_relaxed(write_ptr, drvdata->base + ETB_RAM_READ_POINTER); 286 lost = true; 287 } 288 289 depth = drvdata->buffer_depth; 290 buf_ptr = drvdata->buf; 291 for (i = 0; i < depth; i++) { 292 read_data = readl_relaxed(drvdata->base + 293 ETB_RAM_READ_DATA_REG); 294 *(u32 *)buf_ptr = read_data; 295 buf_ptr += 4; 296 } 297 298 if (lost) 299 coresight_insert_barrier_packet(drvdata->buf); 300 301 if (frame_off) { 302 buf_ptr -= (frame_endoff * 4); 303 for (i = 0; i < frame_endoff; i++) { 304 *buf_ptr++ = 0x0; 305 *buf_ptr++ = 0x0; 306 *buf_ptr++ = 0x0; 307 *buf_ptr++ = 0x0; 308 } 309 } 310 311 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 312 313 CS_LOCK(drvdata->base); 314 } 315 316 static void etb_disable(struct coresight_device *csdev) 317 { 318 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 319 unsigned long flags; 320 321 spin_lock_irqsave(&drvdata->spinlock, flags); 322 323 /* Disable the ETB only if it needs to */ 324 if (drvdata->mode != CS_MODE_DISABLED) { 325 etb_disable_hw(drvdata); 326 etb_dump_hw(drvdata); 327 drvdata->mode = CS_MODE_DISABLED; 328 } 329 spin_unlock_irqrestore(&drvdata->spinlock, flags); 330 331 dev_dbg(drvdata->dev, "ETB disabled\n"); 332 } 333 334 static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, 335 void **pages, int nr_pages, bool overwrite) 336 { 337 int node; 338 struct cs_buffers *buf; 339 340 if (cpu == -1) 341 cpu = smp_processor_id(); 342 node = cpu_to_node(cpu); 343 344 buf = kzalloc_node(sizeof(struct cs_buffers), GFP_KERNEL, node); 345 if (!buf) 346 return NULL; 347 348 buf->snapshot = overwrite; 349 buf->nr_pages = nr_pages; 350 buf->data_pages = pages; 351 352 return buf; 353 } 354 355 static void etb_free_buffer(void *config) 356 { 357 struct cs_buffers *buf = config; 358 359 kfree(buf); 360 } 361 362 static int etb_set_buffer(struct coresight_device *csdev, 363 struct perf_output_handle *handle) 364 { 365 int ret = 0; 366 unsigned long head; 367 struct cs_buffers *buf = etm_perf_sink_config(handle); 368 369 if (!buf) 370 return -EINVAL; 371 372 /* wrap head around to the amount of space we have */ 373 head = handle->head & ((buf->nr_pages << PAGE_SHIFT) - 1); 374 375 /* find the page to write to */ 376 buf->cur = head / PAGE_SIZE; 377 378 /* and offset within that page */ 379 buf->offset = head % PAGE_SIZE; 380 381 local_set(&buf->data_size, 0); 382 383 return ret; 384 } 385 386 static unsigned long etb_update_buffer(struct coresight_device *csdev, 387 struct perf_output_handle *handle, 388 void *sink_config) 389 { 390 bool lost = false; 391 int i, cur; 392 u8 *buf_ptr; 393 const u32 *barrier; 394 u32 read_ptr, write_ptr, capacity; 395 u32 status, read_data; 396 unsigned long offset, to_read; 397 struct cs_buffers *buf = sink_config; 398 struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); 399 400 if (!buf) 401 return 0; 402 403 capacity = drvdata->buffer_depth * ETB_FRAME_SIZE_WORDS; 404 405 etb_disable_hw(drvdata); 406 CS_UNLOCK(drvdata->base); 407 408 /* unit is in words, not bytes */ 409 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); 410 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); 411 412 /* 413 * Entries should be aligned to the frame size. If they are not 414 * go back to the last alignment point to give decoding tools a 415 * chance to fix things. 416 */ 417 if (write_ptr % ETB_FRAME_SIZE_WORDS) { 418 dev_err(drvdata->dev, 419 "write_ptr: %lu not aligned to formatter frame size\n", 420 (unsigned long)write_ptr); 421 422 write_ptr &= ~(ETB_FRAME_SIZE_WORDS - 1); 423 lost = true; 424 } 425 426 /* 427 * Get a hold of the status register and see if a wrap around 428 * has occurred. If so adjust things accordingly. Otherwise 429 * start at the beginning and go until the write pointer has 430 * been reached. 431 */ 432 status = readl_relaxed(drvdata->base + ETB_STATUS_REG); 433 if (status & ETB_STATUS_RAM_FULL) { 434 lost = true; 435 to_read = capacity; 436 read_ptr = write_ptr; 437 } else { 438 to_read = CIRC_CNT(write_ptr, read_ptr, drvdata->buffer_depth); 439 to_read *= ETB_FRAME_SIZE_WORDS; 440 } 441 442 /* 443 * Make sure we don't overwrite data that hasn't been consumed yet. 444 * It is entirely possible that the HW buffer has more data than the 445 * ring buffer can currently handle. If so adjust the start address 446 * to take only the last traces. 447 * 448 * In snapshot mode we are looking to get the latest traces only and as 449 * such, we don't care about not overwriting data that hasn't been 450 * processed by user space. 451 */ 452 if (!buf->snapshot && to_read > handle->size) { 453 u32 mask = ~(ETB_FRAME_SIZE_WORDS - 1); 454 455 /* The new read pointer must be frame size aligned */ 456 to_read = handle->size & mask; 457 /* 458 * Move the RAM read pointer up, keeping in mind that 459 * everything is in frame size units. 460 */ 461 read_ptr = (write_ptr + drvdata->buffer_depth) - 462 to_read / ETB_FRAME_SIZE_WORDS; 463 /* Wrap around if need be*/ 464 if (read_ptr > (drvdata->buffer_depth - 1)) 465 read_ptr -= drvdata->buffer_depth; 466 /* let the decoder know we've skipped ahead */ 467 lost = true; 468 } 469 470 if (lost) 471 perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED); 472 473 /* finally tell HW where we want to start reading from */ 474 writel_relaxed(read_ptr, drvdata->base + ETB_RAM_READ_POINTER); 475 476 cur = buf->cur; 477 offset = buf->offset; 478 barrier = barrier_pkt; 479 480 for (i = 0; i < to_read; i += 4) { 481 buf_ptr = buf->data_pages[cur] + offset; 482 read_data = readl_relaxed(drvdata->base + 483 ETB_RAM_READ_DATA_REG); 484 if (lost && i < CORESIGHT_BARRIER_PKT_SIZE) { 485 read_data = *barrier; 486 barrier++; 487 } 488 489 *(u32 *)buf_ptr = read_data; 490 buf_ptr += 4; 491 492 offset += 4; 493 if (offset >= PAGE_SIZE) { 494 offset = 0; 495 cur++; 496 /* wrap around at the end of the buffer */ 497 cur &= buf->nr_pages - 1; 498 } 499 } 500 501 /* reset ETB buffer for next run */ 502 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); 503 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); 504 505 /* 506 * In snapshot mode we have to update the handle->head to point 507 * to the new location. 508 */ 509 if (buf->snapshot) { 510 handle->head = (cur * PAGE_SIZE) + offset; 511 to_read = buf->nr_pages << PAGE_SHIFT; 512 } 513 etb_enable_hw(drvdata); 514 CS_LOCK(drvdata->base); 515 516 return to_read; 517 } 518 519 static const struct coresight_ops_sink etb_sink_ops = { 520 .enable = etb_enable, 521 .disable = etb_disable, 522 .alloc_buffer = etb_alloc_buffer, 523 .free_buffer = etb_free_buffer, 524 .update_buffer = etb_update_buffer, 525 }; 526 527 static const struct coresight_ops etb_cs_ops = { 528 .sink_ops = &etb_sink_ops, 529 }; 530 531 static void etb_dump(struct etb_drvdata *drvdata) 532 { 533 unsigned long flags; 534 535 spin_lock_irqsave(&drvdata->spinlock, flags); 536 if (drvdata->mode == CS_MODE_SYSFS) { 537 etb_disable_hw(drvdata); 538 etb_dump_hw(drvdata); 539 etb_enable_hw(drvdata); 540 } 541 spin_unlock_irqrestore(&drvdata->spinlock, flags); 542 543 dev_dbg(drvdata->dev, "ETB dumped\n"); 544 } 545 546 static int etb_open(struct inode *inode, struct file *file) 547 { 548 struct etb_drvdata *drvdata = container_of(file->private_data, 549 struct etb_drvdata, miscdev); 550 551 if (local_cmpxchg(&drvdata->reading, 0, 1)) 552 return -EBUSY; 553 554 dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__); 555 return 0; 556 } 557 558 static ssize_t etb_read(struct file *file, char __user *data, 559 size_t len, loff_t *ppos) 560 { 561 u32 depth; 562 struct etb_drvdata *drvdata = container_of(file->private_data, 563 struct etb_drvdata, miscdev); 564 565 etb_dump(drvdata); 566 567 depth = drvdata->buffer_depth; 568 if (*ppos + len > depth * 4) 569 len = depth * 4 - *ppos; 570 571 if (copy_to_user(data, drvdata->buf + *ppos, len)) { 572 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__); 573 return -EFAULT; 574 } 575 576 *ppos += len; 577 578 dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n", 579 __func__, len, (int)(depth * 4 - *ppos)); 580 return len; 581 } 582 583 static int etb_release(struct inode *inode, struct file *file) 584 { 585 struct etb_drvdata *drvdata = container_of(file->private_data, 586 struct etb_drvdata, miscdev); 587 local_set(&drvdata->reading, 0); 588 589 dev_dbg(drvdata->dev, "%s: released\n", __func__); 590 return 0; 591 } 592 593 static const struct file_operations etb_fops = { 594 .owner = THIS_MODULE, 595 .open = etb_open, 596 .read = etb_read, 597 .release = etb_release, 598 .llseek = no_llseek, 599 }; 600 601 #define coresight_etb10_reg(name, offset) \ 602 coresight_simple_reg32(struct etb_drvdata, name, offset) 603 604 coresight_etb10_reg(rdp, ETB_RAM_DEPTH_REG); 605 coresight_etb10_reg(sts, ETB_STATUS_REG); 606 coresight_etb10_reg(rrp, ETB_RAM_READ_POINTER); 607 coresight_etb10_reg(rwp, ETB_RAM_WRITE_POINTER); 608 coresight_etb10_reg(trg, ETB_TRG); 609 coresight_etb10_reg(ctl, ETB_CTL_REG); 610 coresight_etb10_reg(ffsr, ETB_FFSR); 611 coresight_etb10_reg(ffcr, ETB_FFCR); 612 613 static struct attribute *coresight_etb_mgmt_attrs[] = { 614 &dev_attr_rdp.attr, 615 &dev_attr_sts.attr, 616 &dev_attr_rrp.attr, 617 &dev_attr_rwp.attr, 618 &dev_attr_trg.attr, 619 &dev_attr_ctl.attr, 620 &dev_attr_ffsr.attr, 621 &dev_attr_ffcr.attr, 622 NULL, 623 }; 624 625 static ssize_t trigger_cntr_show(struct device *dev, 626 struct device_attribute *attr, char *buf) 627 { 628 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 629 unsigned long val = drvdata->trigger_cntr; 630 631 return sprintf(buf, "%#lx\n", val); 632 } 633 634 static ssize_t trigger_cntr_store(struct device *dev, 635 struct device_attribute *attr, 636 const char *buf, size_t size) 637 { 638 int ret; 639 unsigned long val; 640 struct etb_drvdata *drvdata = dev_get_drvdata(dev->parent); 641 642 ret = kstrtoul(buf, 16, &val); 643 if (ret) 644 return ret; 645 646 drvdata->trigger_cntr = val; 647 return size; 648 } 649 static DEVICE_ATTR_RW(trigger_cntr); 650 651 static struct attribute *coresight_etb_attrs[] = { 652 &dev_attr_trigger_cntr.attr, 653 NULL, 654 }; 655 656 static const struct attribute_group coresight_etb_group = { 657 .attrs = coresight_etb_attrs, 658 }; 659 660 static const struct attribute_group coresight_etb_mgmt_group = { 661 .attrs = coresight_etb_mgmt_attrs, 662 .name = "mgmt", 663 }; 664 665 const struct attribute_group *coresight_etb_groups[] = { 666 &coresight_etb_group, 667 &coresight_etb_mgmt_group, 668 NULL, 669 }; 670 671 static int etb_probe(struct amba_device *adev, const struct amba_id *id) 672 { 673 int ret; 674 void __iomem *base; 675 struct device *dev = &adev->dev; 676 struct coresight_platform_data *pdata = NULL; 677 struct etb_drvdata *drvdata; 678 struct resource *res = &adev->res; 679 struct coresight_desc desc = { 0 }; 680 struct device_node *np = adev->dev.of_node; 681 682 if (np) { 683 pdata = of_get_coresight_platform_data(dev, np); 684 if (IS_ERR(pdata)) 685 return PTR_ERR(pdata); 686 adev->dev.platform_data = pdata; 687 } 688 689 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); 690 if (!drvdata) 691 return -ENOMEM; 692 693 drvdata->dev = &adev->dev; 694 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */ 695 if (!IS_ERR(drvdata->atclk)) { 696 ret = clk_prepare_enable(drvdata->atclk); 697 if (ret) 698 return ret; 699 } 700 dev_set_drvdata(dev, drvdata); 701 702 /* validity for the resource is already checked by the AMBA core */ 703 base = devm_ioremap_resource(dev, res); 704 if (IS_ERR(base)) 705 return PTR_ERR(base); 706 707 drvdata->base = base; 708 709 spin_lock_init(&drvdata->spinlock); 710 711 drvdata->buffer_depth = etb_get_buffer_depth(drvdata); 712 pm_runtime_put(&adev->dev); 713 714 if (drvdata->buffer_depth & 0x80000000) 715 return -EINVAL; 716 717 drvdata->buf = devm_kcalloc(dev, 718 drvdata->buffer_depth, 4, GFP_KERNEL); 719 if (!drvdata->buf) 720 return -ENOMEM; 721 722 desc.type = CORESIGHT_DEV_TYPE_SINK; 723 desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; 724 desc.ops = &etb_cs_ops; 725 desc.pdata = pdata; 726 desc.dev = dev; 727 desc.groups = coresight_etb_groups; 728 drvdata->csdev = coresight_register(&desc); 729 if (IS_ERR(drvdata->csdev)) 730 return PTR_ERR(drvdata->csdev); 731 732 drvdata->miscdev.name = pdata->name; 733 drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; 734 drvdata->miscdev.fops = &etb_fops; 735 ret = misc_register(&drvdata->miscdev); 736 if (ret) 737 goto err_misc_register; 738 739 return 0; 740 741 err_misc_register: 742 coresight_unregister(drvdata->csdev); 743 return ret; 744 } 745 746 #ifdef CONFIG_PM 747 static int etb_runtime_suspend(struct device *dev) 748 { 749 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 750 751 if (drvdata && !IS_ERR(drvdata->atclk)) 752 clk_disable_unprepare(drvdata->atclk); 753 754 return 0; 755 } 756 757 static int etb_runtime_resume(struct device *dev) 758 { 759 struct etb_drvdata *drvdata = dev_get_drvdata(dev); 760 761 if (drvdata && !IS_ERR(drvdata->atclk)) 762 clk_prepare_enable(drvdata->atclk); 763 764 return 0; 765 } 766 #endif 767 768 static const struct dev_pm_ops etb_dev_pm_ops = { 769 SET_RUNTIME_PM_OPS(etb_runtime_suspend, etb_runtime_resume, NULL) 770 }; 771 772 static const struct amba_id etb_ids[] = { 773 { 774 .id = 0x000bb907, 775 .mask = 0x000fffff, 776 }, 777 { 0, 0}, 778 }; 779 780 static struct amba_driver etb_driver = { 781 .drv = { 782 .name = "coresight-etb10", 783 .owner = THIS_MODULE, 784 .pm = &etb_dev_pm_ops, 785 .suppress_bind_attrs = true, 786 787 }, 788 .probe = etb_probe, 789 .id_table = etb_ids, 790 }; 791 builtin_amba_driver(etb_driver); 792