1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2018 Linaro Limited, All rights reserved. 4 * Author: Mike Leach <mike.leach@linaro.org> 5 */ 6 7 #ifndef _CORESIGHT_CORESIGHT_CTI_H 8 #define _CORESIGHT_CORESIGHT_CTI_H 9 10 #include <asm/local.h> 11 #include <linux/spinlock.h> 12 #include "coresight-priv.h" 13 14 /* 15 * Device registers 16 * 0x000 - 0x144: CTI programming and status 17 * 0xEDC - 0xEF8: CTI integration test. 18 * 0xF00 - 0xFFC: Coresight management registers. 19 */ 20 /* CTI programming registers */ 21 #define CTICONTROL 0x000 22 #define CTIINTACK 0x010 23 #define CTIAPPSET 0x014 24 #define CTIAPPCLEAR 0x018 25 #define CTIAPPPULSE 0x01C 26 #define CTIINEN(n) (0x020 + (4 * n)) 27 #define CTIOUTEN(n) (0x0A0 + (4 * n)) 28 #define CTITRIGINSTATUS 0x130 29 #define CTITRIGOUTSTATUS 0x134 30 #define CTICHINSTATUS 0x138 31 #define CTICHOUTSTATUS 0x13C 32 #define CTIGATE 0x140 33 #define ASICCTL 0x144 34 /* Integration test registers */ 35 #define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/ 36 #define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/ 37 #define ITCHOUT 0xEE4 /* WO RW-600 */ 38 #define ITTRIGOUT 0xEE8 /* WO RW-600 */ 39 #define ITCHOUTACK 0xEEC /* RO CTI CSSoc 400 only*/ 40 #define ITTRIGOUTACK 0xEF0 /* RO CTI CSSoc 400 only*/ 41 #define ITCHIN 0xEF4 /* RO */ 42 #define ITTRIGIN 0xEF8 /* RO */ 43 /* management registers */ 44 #define CTIDEVAFF0 0xFA8 45 #define CTIDEVAFF1 0xFAC 46 47 /* 48 * CTI CSSoc 600 has a max of 32 trigger signals per direction. 49 * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. 50 * Max of in and out defined in the DEVID register. 51 * - pick up actual number used from .dts parameters if present. 52 */ 53 #define CTIINOUTEN_MAX 32 54 55 /** 56 * Group of related trigger signals 57 * 58 * @nr_sigs: number of signals in the group. 59 * @used_mask: bitmask representing the signal indexes in the group. 60 * @sig_types: array of types for the signals, length nr_sigs. 61 */ 62 struct cti_trig_grp { 63 int nr_sigs; 64 u32 used_mask; 65 int sig_types[]; 66 }; 67 68 /** 69 * Trigger connection - connection between a CTI and other (coresight) device 70 * lists input and output trigger signals for the device 71 * 72 * @con_in: connected CTIIN signals for the device. 73 * @con_out: connected CTIOUT signals for the device. 74 * @con_dev: coresight device connected to the CTI, NULL if not CS device 75 * @con_dev_name: name of connected device (CS or CPU) 76 * @node: entry node in list of connections. 77 * @con_attrs: Dynamic sysfs attributes specific to this connection. 78 * @attr_group: Dynamic attribute group created for this connection. 79 */ 80 struct cti_trig_con { 81 struct cti_trig_grp *con_in; 82 struct cti_trig_grp *con_out; 83 struct coresight_device *con_dev; 84 const char *con_dev_name; 85 struct list_head node; 86 struct attribute **con_attrs; 87 struct attribute_group *attr_group; 88 }; 89 90 /** 91 * struct cti_device - description of CTI device properties. 92 * 93 * @nt_trig_con: Number of external devices connected to this device. 94 * @ctm_id: which CTM this device is connected to (by default it is 95 * assumed there is a single CTM per SoC, ID 0). 96 * @trig_cons: list of connections to this device. 97 * @cpu: CPU ID if associated with CPU, -1 otherwise. 98 * @con_groups: combined static and dynamic sysfs groups for trigger 99 * connections. 100 */ 101 struct cti_device { 102 int nr_trig_con; 103 u32 ctm_id; 104 struct list_head trig_cons; 105 int cpu; 106 const struct attribute_group **con_groups; 107 }; 108 109 /** 110 * struct cti_config - configuration of the CTI device hardware 111 * 112 * @nr_trig_max: Max number of trigger signals implemented on device. 113 * (max of trig_in or trig_out) - from ID register. 114 * @nr_ctm_channels: number of available CTM channels - from ID register. 115 * @enable_req_count: CTI is enabled alongside >=1 associated devices. 116 * @hw_enabled: true if hw is currently enabled. 117 * @hw_powered: true if associated cpu powered on, or no cpu. 118 * @trig_in_use: bitfield of in triggers registered as in use. 119 * @trig_out_use: bitfield of out triggers registered as in use. 120 * @trig_out_filter: bitfield of out triggers that are blocked if filter 121 * enabled. Typically this would be dbgreq / restart on 122 * a core CTI. 123 * @trig_filter_enable: 1 if filtering enabled. 124 * @xtrig_rchan_sel: channel selection for xtrigger connection show. 125 * @ctiappset: CTI Software application channel set. 126 * @ctiinout_sel: register selector for INEN and OUTEN regs. 127 * @ctiinen: enable input trigger to a channel. 128 * @ctiouten: enable output trigger from a channel. 129 * @ctigate: gate channel output from CTI to CTM. 130 * @asicctl: asic control register. 131 */ 132 struct cti_config { 133 /* hardware description */ 134 int nr_ctm_channels; 135 int nr_trig_max; 136 137 /* cti enable control */ 138 atomic_t enable_req_count; 139 bool hw_enabled; 140 bool hw_powered; 141 142 /* registered triggers and filtering */ 143 u32 trig_in_use; 144 u32 trig_out_use; 145 u32 trig_out_filter; 146 bool trig_filter_enable; 147 u8 xtrig_rchan_sel; 148 149 /* cti cross trig programmable regs */ 150 u32 ctiappset; 151 u8 ctiinout_sel; 152 u32 ctiinen[CTIINOUTEN_MAX]; 153 u32 ctiouten[CTIINOUTEN_MAX]; 154 u32 ctigate; 155 u32 asicctl; 156 }; 157 158 /** 159 * struct cti_drvdata - specifics for the CTI device 160 * @base: Memory mapped base address for this component.. 161 * @csdev: Standard CoreSight device information. 162 * @ctidev: Extra information needed by the CTI/CTM framework. 163 * @spinlock: Control data access to one at a time. 164 * @config: Configuration data for this CTI device. 165 * @node: List entry of this device in the list of CTI devices. 166 * @csdev_release: release function for underlying coresight_device. 167 */ 168 struct cti_drvdata { 169 void __iomem *base; 170 struct coresight_device *csdev; 171 struct cti_device ctidev; 172 spinlock_t spinlock; 173 struct cti_config config; 174 struct list_head node; 175 void (*csdev_release)(struct device *dev); 176 }; 177 178 /* 179 * Channel operation types. 180 */ 181 enum cti_chan_op { 182 CTI_CHAN_ATTACH, 183 CTI_CHAN_DETACH, 184 }; 185 186 enum cti_trig_dir { 187 CTI_TRIG_IN, 188 CTI_TRIG_OUT, 189 }; 190 191 enum cti_chan_gate_op { 192 CTI_GATE_CHAN_ENABLE, 193 CTI_GATE_CHAN_DISABLE, 194 }; 195 196 enum cti_chan_set_op { 197 CTI_CHAN_SET, 198 CTI_CHAN_CLR, 199 CTI_CHAN_PULSE, 200 }; 201 202 /* private cti driver fns & vars */ 203 extern const struct attribute_group *coresight_cti_groups[]; 204 int cti_add_default_connection(struct device *dev, 205 struct cti_drvdata *drvdata); 206 int cti_add_connection_entry(struct device *dev, struct cti_drvdata *drvdata, 207 struct cti_trig_con *tc, 208 struct coresight_device *csdev, 209 const char *assoc_dev_name); 210 struct cti_trig_con *cti_allocate_trig_con(struct device *dev, int in_sigs, 211 int out_sigs); 212 int cti_enable(struct coresight_device *csdev); 213 int cti_disable(struct coresight_device *csdev); 214 void cti_write_all_hw_regs(struct cti_drvdata *drvdata); 215 void cti_write_intack(struct device *dev, u32 ackval); 216 void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value); 217 int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, 218 enum cti_trig_dir direction, u32 channel_idx, 219 u32 trigger_idx); 220 int cti_channel_gate_op(struct device *dev, enum cti_chan_gate_op op, 221 u32 channel_idx); 222 int cti_channel_setop(struct device *dev, enum cti_chan_set_op op, 223 u32 channel_idx); 224 int cti_create_cons_sysfs(struct device *dev, struct cti_drvdata *drvdata); 225 struct coresight_platform_data * 226 coresight_cti_get_platform_data(struct device *dev); 227 const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); 228 229 /* cti powered and enabled */ 230 static inline bool cti_active(struct cti_config *cfg) 231 { 232 return cfg->hw_powered && cfg->hw_enabled; 233 } 234 235 #endif /* _CORESIGHT_CORESIGHT_CTI_H */ 236