1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Coresight configuration 4# 5menuconfig CORESIGHT 6 bool "CoreSight Tracing Support" 7 depends on ARM || ARM64 8 depends on OF || ACPI 9 select ARM_AMBA 10 select PERF_EVENTS 11 help 12 This framework provides a kernel interface for the CoreSight debug 13 and trace drivers to register themselves with. It's intended to build 14 a topological view of the CoreSight components based on a DT 15 specification and configure the right series of components when a 16 trace source gets enabled. 17 18if CORESIGHT 19config CORESIGHT_LINKS_AND_SINKS 20 bool "CoreSight Link and Sink drivers" 21 help 22 This enables support for CoreSight link and sink drivers that are 23 responsible for transporting and collecting the trace data 24 respectively. Link and sinks are dynamically aggregated with a trace 25 entity at run time to form a complete trace path. 26 27config CORESIGHT_LINK_AND_SINK_TMC 28 tristate "Coresight generic TMC driver" 29 30 depends on CORESIGHT_LINKS_AND_SINKS 31 help 32 This enables support for the Trace Memory Controller driver. 33 Depending on its configuration the device can act as a link (embedded 34 trace router - ETR) or sink (embedded trace FIFO). The driver 35 complies with the generic implementation of the component without 36 special enhancement or added features. 37 38 To compile this driver as a module, choose M here: the 39 module will be called coresight-tmc. 40 41config CORESIGHT_CATU 42 bool "Coresight Address Translation Unit (CATU) driver" 43 depends on CORESIGHT_LINK_AND_SINK_TMC 44 help 45 Enable support for the Coresight Address Translation Unit (CATU). 46 CATU supports a scatter gather table of 4K pages, with forward/backward 47 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace 48 buffer by translating the addresses used by ETR to the physical address 49 by looking up the provided table. CATU can also be used in pass-through 50 mode where the address is not translated. 51 52config CORESIGHT_SINK_TPIU 53 tristate "Coresight generic TPIU driver" 54 depends on CORESIGHT_LINKS_AND_SINKS 55 help 56 This enables support for the Trace Port Interface Unit driver, 57 responsible for bridging the gap between the on-chip coresight 58 components and a trace for bridging the gap between the on-chip 59 coresight components and a trace port collection engine, typically 60 connected to an external host for use case capturing more traces than 61 the on-board coresight memory can handle. 62 63 To compile this driver as a module, choose M here: the 64 module will be called coresight-tpiu. 65 66config CORESIGHT_SINK_ETBV10 67 tristate "Coresight ETBv1.0 driver" 68 depends on CORESIGHT_LINKS_AND_SINKS 69 help 70 This enables support for the Embedded Trace Buffer version 1.0 driver 71 that complies with the generic implementation of the component without 72 special enhancement or added features. 73 74 To compile this driver as a module, choose M here: the 75 module will be called coresight-etb10. 76 77config CORESIGHT_SOURCE_ETM3X 78 tristate "CoreSight Embedded Trace Macrocell 3.x driver" 79 depends on !ARM64 80 select CORESIGHT_LINKS_AND_SINKS 81 help 82 This driver provides support for processor ETM3.x and PTM1.x modules, 83 which allows tracing the instructions that a processor is executing 84 This is primarily useful for instruction level tracing. Depending 85 the ETM version data tracing may also be available. 86 87 To compile this driver as a module, choose M here: the 88 module will be called coresight-etm3x. 89 90config CORESIGHT_SOURCE_ETM4X 91 tristate "CoreSight Embedded Trace Macrocell 4.x driver" 92 depends on ARM64 93 select CORESIGHT_LINKS_AND_SINKS 94 select PID_IN_CONTEXTIDR 95 help 96 This driver provides support for the ETM4.x tracer module, tracing the 97 instructions that a processor is executing. This is primarily useful 98 for instruction level tracing. Depending on the implemented version 99 data tracing may also be available. 100 101 To compile this driver as a module, choose M here: the 102 module will be called coresight-etm4x. 103 104config CORESIGHT_STM 105 tristate "CoreSight System Trace Macrocell driver" 106 depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 107 select CORESIGHT_LINKS_AND_SINKS 108 select STM 109 help 110 This driver provides support for hardware assisted software 111 instrumentation based tracing. This is primarily used for 112 logging useful software events or data coming from various entities 113 in the system, possibly running different OSs 114 115 To compile this driver as a module, choose M here: the 116 module will be called coresight-stm. 117 118config CORESIGHT_CPU_DEBUG 119 tristate "CoreSight CPU Debug driver" 120 depends on ARM || ARM64 121 depends on DEBUG_FS 122 help 123 This driver provides support for coresight debugging module. This 124 is primarily used to dump sample-based profiling registers when 125 system triggers panic, the driver will parse context registers so 126 can quickly get to know program counter (PC), secure state, 127 exception level, etc. Before use debugging functionality, platform 128 needs to ensure the clock domain and power domain are enabled 129 properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst 130 for detailed description and the example for usage. 131 132 To compile this driver as a module, choose M here: the 133 module will be called coresight-cpu-debug. 134 135config CORESIGHT_CTI 136 bool "CoreSight Cross Trigger Interface (CTI) driver" 137 depends on ARM || ARM64 138 help 139 This driver provides support for CoreSight CTI and CTM components. 140 These provide hardware triggering events between CoreSight trace 141 source and sink components. These can be used to halt trace or 142 inject events into the trace stream. CTI also provides a software 143 control to trigger the same halt events. This can provide fast trace 144 halt compared to disabling sources and sinks normally in driver 145 software. 146 147config CORESIGHT_CTI_INTEGRATION_REGS 148 bool "Access CTI CoreSight Integration Registers" 149 depends on CORESIGHT_CTI 150 help 151 This option adds support for the CoreSight integration registers on 152 this device. The integration registers allow the exploration of the 153 CTI trigger connections between this and other devices.These 154 registers are not used in normal operation and can leave devices in 155 an inconsistent state. 156endif 157