1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Coresight configuration
4#
5menuconfig CORESIGHT
6	bool "CoreSight Tracing Support"
7	depends on ARM || ARM64
8	depends on OF || ACPI
9	select ARM_AMBA
10	select PERF_EVENTS
11	help
12	  This framework provides a kernel interface for the CoreSight debug
13	  and trace drivers to register themselves with. It's intended to build
14	  a topological view of the CoreSight components based on a DT
15	  specification and configure the right series of components when a
16	  trace source gets enabled.
17
18if CORESIGHT
19config CORESIGHT_LINKS_AND_SINKS
20	bool "CoreSight Link and Sink drivers"
21	help
22	  This enables support for CoreSight link and sink drivers that are
23	  responsible for transporting and collecting the trace data
24	  respectively.  Link and sinks are dynamically aggregated with a trace
25	  entity at run time to form a complete trace path.
26
27config CORESIGHT_LINK_AND_SINK_TMC
28	bool "Coresight generic TMC driver"
29	depends on CORESIGHT_LINKS_AND_SINKS
30	help
31	  This enables support for the Trace Memory Controller driver.
32	  Depending on its configuration the device can act as a link (embedded
33	  trace router - ETR) or sink (embedded trace FIFO).  The driver
34	  complies with the generic implementation of the component without
35	  special enhancement or added features.
36
37config CORESIGHT_CATU
38	bool "Coresight Address Translation Unit (CATU) driver"
39	depends on CORESIGHT_LINK_AND_SINK_TMC
40	help
41	   Enable support for the Coresight Address Translation Unit (CATU).
42	   CATU supports a scatter gather table of 4K pages, with forward/backward
43	   lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
44	   buffer by translating the addresses used by ETR to the physical address
45	   by looking up the provided table. CATU can also be used in pass-through
46	   mode where the address is not translated.
47
48config CORESIGHT_SINK_TPIU
49	tristate "Coresight generic TPIU driver"
50	depends on CORESIGHT_LINKS_AND_SINKS
51	help
52	  This enables support for the Trace Port Interface Unit driver,
53	  responsible for bridging the gap between the on-chip coresight
54	  components and a trace for bridging the gap between the on-chip
55	  coresight components and a trace port collection engine, typically
56	  connected to an external host for use case capturing more traces than
57	  the on-board coresight memory can handle.
58
59	  To compile this driver as a module, choose M here: the
60	  module will be called coresight-tpiu.
61
62config CORESIGHT_SINK_ETBV10
63	tristate "Coresight ETBv1.0 driver"
64	depends on CORESIGHT_LINKS_AND_SINKS
65	help
66	  This enables support for the Embedded Trace Buffer version 1.0 driver
67	  that complies with the generic implementation of the component without
68	  special enhancement or added features.
69
70	  To compile this driver as a module, choose M here: the
71	  module will be called coresight-etb10.
72
73config CORESIGHT_SOURCE_ETM3X
74	tristate "CoreSight Embedded Trace Macrocell 3.x driver"
75	depends on !ARM64
76	select CORESIGHT_LINKS_AND_SINKS
77	help
78	  This driver provides support for processor ETM3.x and PTM1.x modules,
79	  which allows tracing the instructions that a processor is executing
80	  This is primarily useful for instruction level tracing.  Depending
81	  the ETM version data tracing may also be available.
82
83	  To compile this driver as a module, choose M here: the
84	  module will be called coresight-etm3x.
85
86config CORESIGHT_SOURCE_ETM4X
87	tristate "CoreSight Embedded Trace Macrocell 4.x driver"
88	depends on ARM64
89	select CORESIGHT_LINKS_AND_SINKS
90	select PID_IN_CONTEXTIDR
91	help
92	  This driver provides support for the ETM4.x tracer module, tracing the
93	  instructions that a processor is executing. This is primarily useful
94	  for instruction level tracing. Depending on the implemented version
95	  data tracing may also be available.
96
97	  To compile this driver as a module, choose M here: the
98	  module will be called coresight-etm4x.
99
100config CORESIGHT_STM
101	tristate "CoreSight System Trace Macrocell driver"
102	depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
103	select CORESIGHT_LINKS_AND_SINKS
104	select STM
105	help
106	  This driver provides support for hardware assisted software
107	  instrumentation based tracing. This is primarily used for
108	  logging useful software events or data coming from various entities
109	  in the system, possibly running different OSs
110
111	  To compile this driver as a module, choose M here: the
112	  module will be called coresight-stm.
113
114config CORESIGHT_CPU_DEBUG
115	tristate "CoreSight CPU Debug driver"
116	depends on ARM || ARM64
117	depends on DEBUG_FS
118	help
119	  This driver provides support for coresight debugging module. This
120	  is primarily used to dump sample-based profiling registers when
121	  system triggers panic, the driver will parse context registers so
122	  can quickly get to know program counter (PC), secure state,
123	  exception level, etc. Before use debugging functionality, platform
124	  needs to ensure the clock domain and power domain are enabled
125	  properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst
126	  for detailed description and the example for usage.
127
128	  To compile this driver as a module, choose M here: the
129	  module will be called coresight-cpu-debug.
130
131config CORESIGHT_CTI
132	bool "CoreSight Cross Trigger Interface (CTI) driver"
133	depends on ARM || ARM64
134	help
135	  This driver provides support for CoreSight CTI and CTM components.
136	  These provide hardware triggering events between CoreSight trace
137	  source and sink components. These can be used to halt trace or
138	  inject events into the trace stream. CTI also provides a software
139	  control to trigger the same halt events. This can provide fast trace
140	  halt compared to disabling sources and sinks normally in driver
141	  software.
142
143config CORESIGHT_CTI_INTEGRATION_REGS
144	bool "Access CTI CoreSight Integration Registers"
145	depends on CORESIGHT_CTI
146	help
147	  This option adds support for the CoreSight integration registers on
148	  this device. The integration registers allow the exploration of the
149	  CTI trigger connections between this and other devices.These
150	  registers are not used in normal operation and can leave devices in
151	  an inconsistent state.
152endif
153