1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Coresight configuration 4# 5menuconfig CORESIGHT 6 bool "CoreSight Tracing Support" 7 depends on ARM || ARM64 8 depends on OF || ACPI 9 select ARM_AMBA 10 select PERF_EVENTS 11 help 12 This framework provides a kernel interface for the CoreSight debug 13 and trace drivers to register themselves with. It's intended to build 14 a topological view of the CoreSight components based on a DT 15 specification and configure the right series of components when a 16 trace source gets enabled. 17 18if CORESIGHT 19config CORESIGHT_LINKS_AND_SINKS 20 bool "CoreSight Link and Sink drivers" 21 help 22 This enables support for CoreSight link and sink drivers that are 23 responsible for transporting and collecting the trace data 24 respectively. Link and sinks are dynamically aggregated with a trace 25 entity at run time to form a complete trace path. 26 27config CORESIGHT_LINK_AND_SINK_TMC 28 bool "Coresight generic TMC driver" 29 depends on CORESIGHT_LINKS_AND_SINKS 30 help 31 This enables support for the Trace Memory Controller driver. 32 Depending on its configuration the device can act as a link (embedded 33 trace router - ETR) or sink (embedded trace FIFO). The driver 34 complies with the generic implementation of the component without 35 special enhancement or added features. 36 37config CORESIGHT_CATU 38 bool "Coresight Address Translation Unit (CATU) driver" 39 depends on CORESIGHT_LINK_AND_SINK_TMC 40 help 41 Enable support for the Coresight Address Translation Unit (CATU). 42 CATU supports a scatter gather table of 4K pages, with forward/backward 43 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace 44 buffer by translating the addresses used by ETR to the physical address 45 by looking up the provided table. CATU can also be used in pass-through 46 mode where the address is not translated. 47 48config CORESIGHT_SINK_TPIU 49 bool "Coresight generic TPIU driver" 50 depends on CORESIGHT_LINKS_AND_SINKS 51 help 52 This enables support for the Trace Port Interface Unit driver, 53 responsible for bridging the gap between the on-chip coresight 54 components and a trace for bridging the gap between the on-chip 55 coresight components and a trace port collection engine, typically 56 connected to an external host for use case capturing more traces than 57 the on-board coresight memory can handle. 58 59config CORESIGHT_SINK_ETBV10 60 tristate "Coresight ETBv1.0 driver" 61 depends on CORESIGHT_LINKS_AND_SINKS 62 help 63 This enables support for the Embedded Trace Buffer version 1.0 driver 64 that complies with the generic implementation of the component without 65 special enhancement or added features. 66 67 To compile this driver as a module, choose M here: the 68 module will be called coresight-etb10. 69 70config CORESIGHT_SOURCE_ETM3X 71 tristate "CoreSight Embedded Trace Macrocell 3.x driver" 72 depends on !ARM64 73 select CORESIGHT_LINKS_AND_SINKS 74 help 75 This driver provides support for processor ETM3.x and PTM1.x modules, 76 which allows tracing the instructions that a processor is executing 77 This is primarily useful for instruction level tracing. Depending 78 the ETM version data tracing may also be available. 79 80 To compile this driver as a module, choose M here: the 81 module will be called coresight-etm3x. 82 83config CORESIGHT_SOURCE_ETM4X 84 tristate "CoreSight Embedded Trace Macrocell 4.x driver" 85 depends on ARM64 86 select CORESIGHT_LINKS_AND_SINKS 87 select PID_IN_CONTEXTIDR 88 help 89 This driver provides support for the ETM4.x tracer module, tracing the 90 instructions that a processor is executing. This is primarily useful 91 for instruction level tracing. Depending on the implemented version 92 data tracing may also be available. 93 94 To compile this driver as a module, choose M here: the 95 module will be called coresight-etm4x. 96 97config CORESIGHT_STM 98 tristate "CoreSight System Trace Macrocell driver" 99 depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 100 select CORESIGHT_LINKS_AND_SINKS 101 select STM 102 help 103 This driver provides support for hardware assisted software 104 instrumentation based tracing. This is primarily used for 105 logging useful software events or data coming from various entities 106 in the system, possibly running different OSs 107 108 To compile this driver as a module, choose M here: the 109 module will be called coresight-stm. 110 111config CORESIGHT_CPU_DEBUG 112 tristate "CoreSight CPU Debug driver" 113 depends on ARM || ARM64 114 depends on DEBUG_FS 115 help 116 This driver provides support for coresight debugging module. This 117 is primarily used to dump sample-based profiling registers when 118 system triggers panic, the driver will parse context registers so 119 can quickly get to know program counter (PC), secure state, 120 exception level, etc. Before use debugging functionality, platform 121 needs to ensure the clock domain and power domain are enabled 122 properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst 123 for detailed description and the example for usage. 124 125 To compile this driver as a module, choose M here: the 126 module will be called coresight-cpu-debug. 127 128config CORESIGHT_CTI 129 bool "CoreSight Cross Trigger Interface (CTI) driver" 130 depends on ARM || ARM64 131 help 132 This driver provides support for CoreSight CTI and CTM components. 133 These provide hardware triggering events between CoreSight trace 134 source and sink components. These can be used to halt trace or 135 inject events into the trace stream. CTI also provides a software 136 control to trigger the same halt events. This can provide fast trace 137 halt compared to disabling sources and sinks normally in driver 138 software. 139 140config CORESIGHT_CTI_INTEGRATION_REGS 141 bool "Access CTI CoreSight Integration Registers" 142 depends on CORESIGHT_CTI 143 help 144 This option adds support for the CoreSight integration registers on 145 this device. The integration registers allow the exploration of the 146 CTI trigger connections between this and other devices.These 147 registers are not used in normal operation and can leave devices in 148 an inconsistent state. 149endif 150