1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Coresight configuration
4#
5menuconfig CORESIGHT
6	bool "CoreSight Tracing Support"
7	depends on OF || ACPI
8	select ARM_AMBA
9	select PERF_EVENTS
10	help
11	  This framework provides a kernel interface for the CoreSight debug
12	  and trace drivers to register themselves with. It's intended to build
13	  a topological view of the CoreSight components based on a DT
14	  specification and configure the right series of components when a
15	  trace source gets enabled.
16
17if CORESIGHT
18config CORESIGHT_LINKS_AND_SINKS
19	bool "CoreSight Link and Sink drivers"
20	help
21	  This enables support for CoreSight link and sink drivers that are
22	  responsible for transporting and collecting the trace data
23	  respectively.  Link and sinks are dynamically aggregated with a trace
24	  entity at run time to form a complete trace path.
25
26config CORESIGHT_LINK_AND_SINK_TMC
27	bool "Coresight generic TMC driver"
28	depends on CORESIGHT_LINKS_AND_SINKS
29	help
30	  This enables support for the Trace Memory Controller driver.
31	  Depending on its configuration the device can act as a link (embedded
32	  trace router - ETR) or sink (embedded trace FIFO).  The driver
33	  complies with the generic implementation of the component without
34	  special enhancement or added features.
35
36config CORESIGHT_CATU
37	bool "Coresight Address Translation Unit (CATU) driver"
38	depends on CORESIGHT_LINK_AND_SINK_TMC
39	help
40	   Enable support for the Coresight Address Translation Unit (CATU).
41	   CATU supports a scatter gather table of 4K pages, with forward/backward
42	   lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
43	   buffer by translating the addresses used by ETR to the physical address
44	   by looking up the provided table. CATU can also be used in pass-through
45	   mode where the address is not translated.
46
47config CORESIGHT_SINK_TPIU
48	bool "Coresight generic TPIU driver"
49	depends on CORESIGHT_LINKS_AND_SINKS
50	help
51	  This enables support for the Trace Port Interface Unit driver,
52	  responsible for bridging the gap between the on-chip coresight
53	  components and a trace for bridging the gap between the on-chip
54	  coresight components and a trace port collection engine, typically
55	  connected to an external host for use case capturing more traces than
56	  the on-board coresight memory can handle.
57
58config CORESIGHT_SINK_ETBV10
59	bool "Coresight ETBv1.0 driver"
60	depends on CORESIGHT_LINKS_AND_SINKS
61	help
62	  This enables support for the Embedded Trace Buffer version 1.0 driver
63	  that complies with the generic implementation of the component without
64	  special enhancement or added features.
65
66config CORESIGHT_SOURCE_ETM3X
67	bool "CoreSight Embedded Trace Macrocell 3.x driver"
68	depends on !ARM64
69	select CORESIGHT_LINKS_AND_SINKS
70	help
71	  This driver provides support for processor ETM3.x and PTM1.x modules,
72	  which allows tracing the instructions that a processor is executing
73	  This is primarily useful for instruction level tracing.  Depending
74	  the ETM version data tracing may also be available.
75
76config CORESIGHT_SOURCE_ETM4X
77	bool "CoreSight Embedded Trace Macrocell 4.x driver"
78	depends on ARM64
79	select CORESIGHT_LINKS_AND_SINKS
80	select PID_IN_CONTEXTIDR
81	help
82	  This driver provides support for the ETM4.x tracer module, tracing the
83	  instructions that a processor is executing. This is primarily useful
84	  for instruction level tracing. Depending on the implemented version
85	  data tracing may also be available.
86
87config CORESIGHT_STM
88	bool "CoreSight System Trace Macrocell driver"
89	depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
90	select CORESIGHT_LINKS_AND_SINKS
91	select STM
92	help
93	  This driver provides support for hardware assisted software
94	  instrumentation based tracing. This is primarily used for
95	  logging useful software events or data coming from various entities
96	  in the system, possibly running different OSs
97
98config CORESIGHT_CPU_DEBUG
99	tristate "CoreSight CPU Debug driver"
100	depends on ARM || ARM64
101	depends on DEBUG_FS
102	help
103	  This driver provides support for coresight debugging module. This
104	  is primarily used to dump sample-based profiling registers when
105	  system triggers panic, the driver will parse context registers so
106	  can quickly get to know program counter (PC), secure state,
107	  exception level, etc. Before use debugging functionality, platform
108	  needs to ensure the clock domain and power domain are enabled
109	  properly, please refer Documentation/trace/coresight-cpu-debug.txt
110	  for detailed description and the example for usage.
111
112endif
113