1# SPDX-License-Identifier: GPL-2.0-only 2# 3# Coresight configuration 4# 5menuconfig CORESIGHT 6 tristate "CoreSight Tracing Support" 7 depends on ARM || ARM64 8 depends on OF || ACPI 9 select ARM_AMBA 10 select PERF_EVENTS 11 help 12 This framework provides a kernel interface for the CoreSight debug 13 and trace drivers to register themselves with. It's intended to build 14 a topological view of the CoreSight components based on a DT 15 specification and configure the right series of components when a 16 trace source gets enabled. 17 18 To compile this driver as a module, choose M here: the 19 module will be called coresight. 20 21if CORESIGHT 22config CORESIGHT_LINKS_AND_SINKS 23 tristate "CoreSight Link and Sink drivers" 24 help 25 This enables support for CoreSight link and sink drivers that are 26 responsible for transporting and collecting the trace data 27 respectively. Link and sinks are dynamically aggregated with a trace 28 entity at run time to form a complete trace path. 29 30 To compile these drivers as modules, choose M here: the 31 modules will be called coresight-funnel and coresight-replicator. 32 33config CORESIGHT_LINK_AND_SINK_TMC 34 tristate "Coresight generic TMC driver" 35 36 depends on CORESIGHT_LINKS_AND_SINKS 37 help 38 This enables support for the Trace Memory Controller driver. 39 Depending on its configuration the device can act as a link (embedded 40 trace router - ETR) or sink (embedded trace FIFO). The driver 41 complies with the generic implementation of the component without 42 special enhancement or added features. 43 44 To compile this driver as a module, choose M here: the 45 module will be called coresight-tmc. 46 47config CORESIGHT_CATU 48 tristate "Coresight Address Translation Unit (CATU) driver" 49 depends on CORESIGHT_LINK_AND_SINK_TMC 50 help 51 Enable support for the Coresight Address Translation Unit (CATU). 52 CATU supports a scatter gather table of 4K pages, with forward/backward 53 lookup. CATU helps TMC ETR to use a large physically non-contiguous trace 54 buffer by translating the addresses used by ETR to the physical address 55 by looking up the provided table. CATU can also be used in pass-through 56 mode where the address is not translated. 57 58 To compile this driver as a module, choose M here: the 59 module will be called coresight-catu. 60 61config CORESIGHT_SINK_TPIU 62 tristate "Coresight generic TPIU driver" 63 depends on CORESIGHT_LINKS_AND_SINKS 64 help 65 This enables support for the Trace Port Interface Unit driver, 66 responsible for bridging the gap between the on-chip coresight 67 components and a trace for bridging the gap between the on-chip 68 coresight components and a trace port collection engine, typically 69 connected to an external host for use case capturing more traces than 70 the on-board coresight memory can handle. 71 72 To compile this driver as a module, choose M here: the 73 module will be called coresight-tpiu. 74 75config CORESIGHT_SINK_ETBV10 76 tristate "Coresight ETBv1.0 driver" 77 depends on CORESIGHT_LINKS_AND_SINKS 78 help 79 This enables support for the Embedded Trace Buffer version 1.0 driver 80 that complies with the generic implementation of the component without 81 special enhancement or added features. 82 83 To compile this driver as a module, choose M here: the 84 module will be called coresight-etb10. 85 86config CORESIGHT_SOURCE_ETM3X 87 tristate "CoreSight Embedded Trace Macrocell 3.x driver" 88 depends on !ARM64 89 select CORESIGHT_LINKS_AND_SINKS 90 help 91 This driver provides support for processor ETM3.x and PTM1.x modules, 92 which allows tracing the instructions that a processor is executing 93 This is primarily useful for instruction level tracing. Depending 94 the ETM version data tracing may also be available. 95 96 To compile this driver as a module, choose M here: the 97 module will be called coresight-etm3x. 98 99config CORESIGHT_SOURCE_ETM4X 100 tristate "CoreSight Embedded Trace Macrocell 4.x driver" 101 depends on ARM64 102 select CORESIGHT_LINKS_AND_SINKS 103 select PID_IN_CONTEXTIDR 104 help 105 This driver provides support for the ETM4.x tracer module, tracing the 106 instructions that a processor is executing. This is primarily useful 107 for instruction level tracing. Depending on the implemented version 108 data tracing may also be available. 109 110 To compile this driver as a module, choose M here: the 111 module will be called coresight-etm4x. 112 113config ETM4X_IMPDEF_FEATURE 114 bool "Control implementation defined overflow support in ETM 4.x driver" 115 depends on CORESIGHT_SOURCE_ETM4X 116 help 117 This control provides implementation define control for CoreSight 118 ETM 4.x tracer module that can't reduce commit rate automatically. 119 This avoids overflow between the ETM tracer module and the cpu core. 120 121config CORESIGHT_STM 122 tristate "CoreSight System Trace Macrocell driver" 123 depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64 124 select CORESIGHT_LINKS_AND_SINKS 125 select STM 126 help 127 This driver provides support for hardware assisted software 128 instrumentation based tracing. This is primarily used for 129 logging useful software events or data coming from various entities 130 in the system, possibly running different OSs 131 132 To compile this driver as a module, choose M here: the 133 module will be called coresight-stm. 134 135config CORESIGHT_CPU_DEBUG 136 tristate "CoreSight CPU Debug driver" 137 depends on ARM || ARM64 138 depends on DEBUG_FS 139 help 140 This driver provides support for coresight debugging module. This 141 is primarily used to dump sample-based profiling registers when 142 system triggers panic, the driver will parse context registers so 143 can quickly get to know program counter (PC), secure state, 144 exception level, etc. Before use debugging functionality, platform 145 needs to ensure the clock domain and power domain are enabled 146 properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst 147 for detailed description and the example for usage. 148 149 To compile this driver as a module, choose M here: the 150 module will be called coresight-cpu-debug. 151 152config CORESIGHT_CTI 153 tristate "CoreSight Cross Trigger Interface (CTI) driver" 154 depends on ARM || ARM64 155 help 156 This driver provides support for CoreSight CTI and CTM components. 157 These provide hardware triggering events between CoreSight trace 158 source and sink components. These can be used to halt trace or 159 inject events into the trace stream. CTI also provides a software 160 control to trigger the same halt events. This can provide fast trace 161 halt compared to disabling sources and sinks normally in driver 162 software. 163 164 To compile this driver as a module, choose M here: the 165 module will be called coresight-cti. 166 167config CORESIGHT_CTI_INTEGRATION_REGS 168 bool "Access CTI CoreSight Integration Registers" 169 depends on CORESIGHT_CTI 170 help 171 This option adds support for the CoreSight integration registers on 172 this device. The integration registers allow the exploration of the 173 CTI trigger connections between this and other devices.These 174 registers are not used in normal operation and can leave devices in 175 an inconsistent state. 176endif 177