1#
2# Coresight configuration
3#
4menuconfig CORESIGHT
5	bool "CoreSight Tracing Support"
6	select ARM_AMBA
7	select PERF_EVENTS
8	help
9	  This framework provides a kernel interface for the CoreSight debug
10	  and trace drivers to register themselves with. It's intended to build
11	  a topological view of the CoreSight components based on a DT
12	  specification and configure the right series of components when a
13	  trace source gets enabled.
14
15if CORESIGHT
16config CORESIGHT_LINKS_AND_SINKS
17	bool "CoreSight Link and Sink drivers"
18	help
19	  This enables support for CoreSight link and sink drivers that are
20	  responsible for transporting and collecting the trace data
21	  respectively.  Link and sinks are dynamically aggregated with a trace
22	  entity at run time to form a complete trace path.
23
24config CORESIGHT_LINK_AND_SINK_TMC
25	bool "Coresight generic TMC driver"
26	depends on CORESIGHT_LINKS_AND_SINKS
27	help
28	  This enables support for the Trace Memory Controller driver.
29	  Depending on its configuration the device can act as a link (embedded
30	  trace router - ETR) or sink (embedded trace FIFO).  The driver
31	  complies with the generic implementation of the component without
32	  special enhancement or added features.
33
34config CORESIGHT_SINK_TPIU
35	bool "Coresight generic TPIU driver"
36	depends on CORESIGHT_LINKS_AND_SINKS
37	help
38	  This enables support for the Trace Port Interface Unit driver,
39	  responsible for bridging the gap between the on-chip coresight
40	  components and a trace for bridging the gap between the on-chip
41	  coresight components and a trace port collection engine, typically
42	  connected to an external host for use case capturing more traces than
43	  the on-board coresight memory can handle.
44
45config CORESIGHT_SINK_ETBV10
46	bool "Coresight ETBv1.0 driver"
47	depends on CORESIGHT_LINKS_AND_SINKS
48	help
49	  This enables support for the Embedded Trace Buffer version 1.0 driver
50	  that complies with the generic implementation of the component without
51	  special enhancement or added features.
52
53config CORESIGHT_SOURCE_ETM3X
54	bool "CoreSight Embedded Trace Macrocell 3.x driver"
55	depends on !ARM64
56	select CORESIGHT_LINKS_AND_SINKS
57	help
58	  This driver provides support for processor ETM3.x and PTM1.x modules,
59	  which allows tracing the instructions that a processor is executing
60	  This is primarily useful for instruction level tracing.  Depending
61	  the ETM version data tracing may also be available.
62
63config CORESIGHT_SOURCE_ETM4X
64	bool "CoreSight Embedded Trace Macrocell 4.x driver"
65	depends on ARM64
66	select CORESIGHT_LINKS_AND_SINKS
67	help
68	  This driver provides support for the ETM4.x tracer module, tracing the
69	  instructions that a processor is executing. This is primarily useful
70	  for instruction level tracing. Depending on the implemented version
71	  data tracing may also be available.
72
73config CORESIGHT_QCOM_REPLICATOR
74	bool "Qualcomm CoreSight Replicator driver"
75	depends on CORESIGHT_LINKS_AND_SINKS
76	help
77	  This enables support for Qualcomm CoreSight link driver. The
78	  programmable ATB replicator sends the ATB trace stream from the
79	  ETB/ETF to the TPIUi and ETR.
80
81config CORESIGHT_STM
82	bool "CoreSight System Trace Macrocell driver"
83	depends on (ARM && !(CPU_32v3 || CPU_32v4 || CPU_32v4T)) || ARM64
84	select CORESIGHT_LINKS_AND_SINKS
85	select STM
86	help
87	  This driver provides support for hardware assisted software
88	  instrumentation based tracing. This is primarily used for
89	  logging useful software events or data coming from various entities
90	  in the system, possibly running different OSs
91
92config CORESIGHT_CPU_DEBUG
93	tristate "CoreSight CPU Debug driver"
94	depends on ARM || ARM64
95	depends on DEBUG_FS
96	help
97	  This driver provides support for coresight debugging module. This
98	  is primarily used to dump sample-based profiling registers when
99	  system triggers panic, the driver will parse context registers so
100	  can quickly get to know program counter (PC), secure state,
101	  exception level, etc. Before use debugging functionality, platform
102	  needs to ensure the clock domain and power domain are enabled
103	  properly, please refer Documentation/trace/coresight-cpu-debug.txt
104	  for detailed description and the example for usage.
105
106endif
107